diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-22 16:09:10 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2013-01-22 16:09:10 +0000 |
commit | 7dad51762decebe5d104fe7dad9eb23680cabd23 (patch) | |
tree | 4a123dae59fba7a45afa0683bedf9022cd3c6f89 /nuttx/arch/arm/src | |
parent | 9375b285f28c3636edab8bc60540f156aa11eaf7 (diff) | |
download | px4-firmware-7dad51762decebe5d104fe7dad9eb23680cabd23.tar.gz px4-firmware-7dad51762decebe5d104fe7dad9eb23680cabd23.tar.bz2 px4-firmware-7dad51762decebe5d104fe7dad9eb23680cabd23.zip |
Use of BASEPRI to control ARM interrupts is now functional
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5548 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src')
-rw-r--r-- | nuttx/arch/arm/src/kinetis/kinetis_irq.c | 32 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm/lm_irq.c | 32 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c | 21 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc17xx/lpc17_irq.c | 32 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_irq.c | 32 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam3u/sam3u_irq.c | 32 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_irq.c | 32 |
7 files changed, 115 insertions, 98 deletions
diff --git a/nuttx/arch/arm/src/kinetis/kinetis_irq.c b/nuttx/arch/arm/src/kinetis/kinetis_irq.c index 37a6a4a63..b0aea55d1 100644 --- a/nuttx/arch/arm/src/kinetis/kinetis_irq.c +++ b/nuttx/arch/arm/src/kinetis/kinetis_irq.c @@ -209,7 +209,7 @@ static int kinetis_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: kinetis_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -217,23 +217,17 @@ static int kinetis_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void kinetis_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -389,7 +383,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(KINETIS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(KINETIS_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + kinetis_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -528,11 +522,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < KINETIS_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= KINETIS_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/lm/lm_irq.c b/nuttx/arch/arm/src/lm/lm_irq.c index 7d8d2135a..d8c0852ed 100644 --- a/nuttx/arch/arm/src/lm/lm_irq.c +++ b/nuttx/arch/arm/src/lm/lm_irq.c @@ -191,7 +191,7 @@ static int lm_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: lm_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -199,23 +199,17 @@ static int lm_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void lm_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -347,7 +341,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(LM_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + lm_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -475,11 +469,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < LM_IRQ_INTERRUPTS) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= LM_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c index bf6d18287..0241d4bf7 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -104,11 +104,28 @@ #endif /* If the user did not specify a priority for Ethernet interrupts, set the - * interrupt priority to the maximum. + * interrupt priority to the maximum (unless CONFIG_ARMV7M_USEBASEPRI is + * defined, then set it to the maximum allowable priority). */ #ifndef CONFIG_NET_PRIORITY -# define CONFIG_NET_PRIORITY NVIC_SYSH_PRIORITY_MAX +# ifdef CONFIG_ARMV7M_USEBASEPRI +# define CONFIG_NET_PRIORITY NVIC_SYSH_DISABLE_PRIORITY +# else +# define CONFIG_NET_PRIORITY NVIC_SYSH_PRIORITY_MAX +# endif +#endif + +/* If the priority is set at the max (0) and CONFIG_ARMV7M_USEBASEPRI is + * defined, then silently drop the priority to NVIC_SYSH_DISABLE_PRIORITY. + * In this configuratin, nothing is permitted to run at priority zero + * except for the SVCALL handler. NVIC_SYSH_DISABLE_PRIORITY is the + * maximum allowable priority in that case. + */ + +#if CONFIG_NET_PRIORITY == 0 && defined(CONFIG_ARMV7M_USEBASEPRI) +# undef CONFIG_NET_PRIORITY +# define CONFIG_NET_PRIORITY NVIC_SYSH_DISABLE_PRIORITY #endif /* Debug Configuration *****************************************************/ diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c index c9b289d4e..6d96ff386 100644 --- a/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/nuttx/arch/arm/src/lpc17xx/lpc17_irq.c @@ -190,7 +190,7 @@ static int lpc17_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: lpc17_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -198,23 +198,17 @@ static int lpc17_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void lpc17_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -335,7 +329,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(LPC17_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + lpc17_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -490,11 +484,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < LPC17_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= LPC17_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c index 1867aa150..aa0e4cf09 100644 --- a/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_irq.c @@ -192,7 +192,7 @@ static int lpc43_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: lpc43_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -200,23 +200,17 @@ static int lpc43_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void lpc43_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -364,7 +358,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(LPC43_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + lpc43_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -519,11 +513,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < LPC43_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= LPC43_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/sam3u/sam3u_irq.c b/nuttx/arch/arm/src/sam3u/sam3u_irq.c index 690a075ef..ed424f91d 100644 --- a/nuttx/arch/arm/src/sam3u/sam3u_irq.c +++ b/nuttx/arch/arm/src/sam3u/sam3u_irq.c @@ -185,7 +185,7 @@ static int sam3u_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: sam3u_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -193,23 +193,17 @@ static int sam3u_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void sam3u_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -326,7 +320,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(SAM3U_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + sam3u_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -478,11 +472,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < SAM3U_IRQ_EXTINT) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= SAM3U_IRQ_EXTINT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index bff3eb2b7..a952c2486 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -195,7 +195,7 @@ static int stm32_reserved(int irq, FAR void *context) #endif /**************************************************************************** - * Name: up_prioritize_irq + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -203,23 +203,17 @@ static int stm32_reserved(int irq, FAR void *context) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI) -static int up_prioritize_irq(int irq, int priority) +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void stm32_prioritize_syscall(int priority) { - uint32_t regaddr; uint32_t regval; - int shift; - irq -= 4; - regaddr = NVIC_SYSH_PRIORITY(irq); - regval = getreg32(regaddr); - shift = ((irq & 3) << 3); - regval &= ~(0xff << shift); - regval |= (priority << shift); - putreg32(regval, regaddr); + /* SVCALL is system handler 11 */ - stm32_dumpnvic("prioritize", irq); - return OK; + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif @@ -365,7 +359,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif #ifdef CONFIG_ARMV7M_USEBASEPRI - up_prioritize_irq(STM32_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management @@ -493,11 +487,17 @@ int up_prioritize_irq(int irq, int priority) if (irq < STM32_IRQ_INTERRUPTS) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } |