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| author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2011-12-20 18:28:50 +0000 |
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| committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2011-12-20 18:28:50 +0000 |
| commit | 5a714f6d99806da8847905251e82a6105aa045c1 (patch) | |
| tree | 9980ed8c980faff4c6299ed381ca32314836aa9d /nuttx/configs/hymini-stm32v | |
| parent | 025c867f103a420a5147ae29ae1e6eae90cce42f (diff) | |
| download | px4-firmware-5a714f6d99806da8847905251e82a6105aa045c1.tar.gz px4-firmware-5a714f6d99806da8847905251e82a6105aa045c1.tar.bz2 px4-firmware-5a714f6d99806da8847905251e82a6105aa045c1.zip | |
Finishes the PWM driver for the STM32
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4206 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx/configs/hymini-stm32v')
| -rwxr-xr-x | nuttx/configs/hymini-stm32v/include/board.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/nuttx/configs/hymini-stm32v/include/board.h b/nuttx/configs/hymini-stm32v/include/board.h index fbecc0b6c..719ad1c74 100755 --- a/nuttx/configs/hymini-stm32v/include/board.h +++ b/nuttx/configs/hymini-stm32v/include/board.h @@ -88,11 +88,25 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + /* USB divider -- Divide PLL clock by 1.5 */ #define STM32_CFGR_USBPRE 0 |