diff options
author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-09-09 19:13:30 +0000 |
---|---|---|
committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2012-09-09 19:13:30 +0000 |
commit | 47683c485c76ab2595326d890604e9f54bb7d767 (patch) | |
tree | 9d4a819cae71f82b67fc68e0f3e8495f1a8009d9 /nuttx | |
parent | e2498c5e7646b64095fdccad37c2d2e850e97f65 (diff) | |
download | px4-firmware-47683c485c76ab2595326d890604e9f54bb7d767.tar.gz px4-firmware-47683c485c76ab2595326d890604e9f54bb7d767.tar.bz2 px4-firmware-47683c485c76ab2595326d890604e9f54bb7d767.zip |
Beginning of configuration for M3 Wildfire board
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5120 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx')
-rw-r--r-- | nuttx/ChangeLog | 3 | ||||
-rw-r--r-- | nuttx/Documentation/README.html | 2 | ||||
-rw-r--r-- | nuttx/README.txt | 2 | ||||
-rw-r--r-- | nuttx/configs/Kconfig | 14 | ||||
-rw-r--r-- | nuttx/configs/README.txt | 4 | ||||
-rw-r--r-- | nuttx/configs/fire-stm32v2/Kconfig | 6 | ||||
-rw-r--r-- | nuttx/configs/fire-stm32v2/README.txt | 727 | ||||
-rw-r--r-- | nuttx/configs/fire-stm32v2/include/board.h | 394 | ||||
-rw-r--r-- | nuttx/configs/fire-stm32v2/src/fire-internal.h | 229 | ||||
-rw-r--r-- | nuttx/configs/shenzhou/include/board.h | 31 |
10 files changed, 1412 insertions, 0 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index ef00bae87..614c14415 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3292,4 +3292,7 @@ is nothing in the source tree now that depends on the old way of doing things (if I am wrong, they will need a change to the linker script). + * configs/fire-stm32v2: Configuration for the M3 Wildfire board. I + don't know very much about this board other than is has an + STM32F103VET chip, LCD, touchscreen, and ENC28J60 network. diff --git a/nuttx/Documentation/README.html b/nuttx/Documentation/README.html index c18dd9ad8..135c4f359 100644 --- a/nuttx/Documentation/README.html +++ b/nuttx/Documentation/README.html @@ -85,6 +85,8 @@ | | | |- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/ez80f910200zco/ostest/README.txt?view=log">ostest/README.txt</a> | | | |- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/ez80f910200zco/poll/README.txt?view=log">poll/README.txt</a> | | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/ez80f910200zco/README.txt?view=log"><b><i>README.txt</i></b></a> + | | |- fire-stm32v2/ + | | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/fire-stm32v2/README.txt?view=log"><b><i>README.txt</i></b></a> | | |- hymini-stm32v/ | | | |- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/hymini-stm32v/include/README.txt?view=log">include/README.txt</a> | | | |- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/hymini-stm32v/RIDE/README.txt?view=log">RIDE/README.txt</a> diff --git a/nuttx/README.txt b/nuttx/README.txt index 596451128..b0aa5384c 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -654,6 +654,8 @@ nuttx | | |- ostest/README.txt | | |- poll/README.txt | | `- README.txt + | |- fire-stm32v2/ + | | `- README.txt | |- hymini-stm32v/ | | |- include/README.txt | | |- src/README.txt diff --git a/nuttx/configs/Kconfig b/nuttx/configs/Kconfig index f8470bc94..dabd32842 100644 --- a/nuttx/configs/Kconfig +++ b/nuttx/configs/Kconfig @@ -130,6 +130,16 @@ config ARCH_BOARD_EZ80F910200ZCO development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line tools. The development environment is Cygwin under WinXP. +config ARCH_BOARD_FIRE_STM32V2 + bool "M3 Wildfire STM32v2 board" + depends on ARCH_CHIP_STM32F103VET + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + A configuration for the M3 Wildfile board. This board is based on the + STM32F103VET chip. + config ARCH_BOARD_HYMINI_STM32V bool "HY-Mini STM32v board" depends on ARCH_CHIP_STM32F103VCT @@ -597,6 +607,7 @@ config ARCH_BOARD default "ekk-lm3s9b96" if ARCH_BOARD_EKK_LM3S9B96 default "ez80f0910200kitg" if ARCH_BOARD_EZ80F910200KITG default "ez80f0910200zco" if ARCH_BOARD_EZ80F910200ZCO + default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32V2 default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V default "kwikstik-k40" if ARCH_BOARD_KWIKSTIK_K40 default "lincoln60" if ARCH_BOARD_LINCOLN60 @@ -736,6 +747,9 @@ endif if ARCH_BOARD_EZ80F910200ZCO source "configs/ez80f910200zco/Kconfig" endif +if ARCH_BOARD_FIRE_STM32V2 +source "configs/fire-stm32v2/Kconfig" +endif if ARCH_BOARD_HYMINI_STM32V source "configs/hymini-stm32v/Kconfig" endif diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 3a059a62a..2f5894672 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1543,6 +1543,10 @@ configs/ez80f0910200zco development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line tools. The development environment is Cygwin under WinXP. +configs/fire-stm32v2 + A configuration for the M3 Wildfire STM32 board. This board is based on the + STM32F103VET chip. + configs/hymini-stm32v A configuration for the HY-Mini STM32v board. This board is based on the STM32F103VCT chip. diff --git a/nuttx/configs/fire-stm32v2/Kconfig b/nuttx/configs/fire-stm32v2/Kconfig new file mode 100644 index 000000000..3f4b857da --- /dev/null +++ b/nuttx/configs/fire-stm32v2/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +comment "M3 Wildfire Configuration" diff --git a/nuttx/configs/fire-stm32v2/README.txt b/nuttx/configs/fire-stm32v2/README.txt new file mode 100644 index 000000000..92bc9ecd2 --- /dev/null +++ b/nuttx/configs/fire-stm32v2/README.txt @@ -0,0 +1,727 @@ +README
+======
+
+This README discusses issues unique to NuttX configurations for the M3
+Wildfire development board (STM32F103VET).
+
+Contents
+========
+
+ - Pin Configuration
+ - Development Environment
+ - GNU Toolchain Options
+ - IDEs
+ - NuttX buildroot Toolchain
+ - DFU and JTAG
+ - OpenOCD
+ - LEDs
+ - RTC
+ - M3 Wildfire-specific Configuration Options
+ - Configurations
+
+Pin Configuration
+=================
+--- ------ -------------- -------------------------------------------------------------------
+PIN NAME SIGNAL NOTES
+--- ------ -------------- -------------------------------------------------------------------
+
+1 PE2 PE2-C-RCLK Camera (P9)
+2 PE3 PE3-USB-M USB2.0
+3 PE4 PE4-BEEP LS1 Bell
+4 PE5
+5 PE6
+6 VBAT BT1 Battery (BT1)
+7 PC13 PD13_LCD_LIGHT 2.4" TFT + Touchscreen
+8 PC14 PC14/OSC32-IN Y2 32.768KHz
+9 PC15 PC15/OSC32-OUT Y2 32.768KHz
+10 VSS_5 DGND
+11 VDD_5 3V3
+12 OSC_IN Y1 8MHz
+13 OSC_OUT Y1 8MHz
+14 NRST REST1 Reset switch
+15 PC0
+16 PC1 PC1/ADC123-IN11 Potentiometer (R16)
+17 PC2
+18 PC3 PC3-LED1 LED1, Active low (pulled high)
+19 VSSA DGND
+20 VREF- DGND
+21 VREF+ 3V3
+22 VDDA 3V3
+23 PA0 PA0-C-VSYNC Camera (P9)
+24 PA1 PC1/ADC123-IN11
+25 PA2 PA2-US2-TX MAX3232, DB9 D7
+
+--- ------ -------------- -------------------------------------------------------------------
+PIN NAME SIGNAL NOTES
+--- ------ -------------- -------------------------------------------------------------------
+
+26 PA3 PA3-US2-RX MAX3232, DB9 D7
+27 VSS_4 DGND
+28 VDD_4 3V3
+29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH
+30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
+31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
+32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
+33 PC4 PC4-LED2 LED2, Active low (pulled high)
+34 PC5 PC5-LED3 LED3, Active low (pulled high)
+35 PB0 PB0-KEY1 KEY1, Low when closed (pulled high if open)
+36 PB1 PB1-KEY2 KEY2, Low when closed (pulled high if open)
+37 PB2 BOOT1/DGND
+38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen
+39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen
+40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen
+41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen
+42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen
+43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen
+44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen
+45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen
+46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen
+47 PB10 PB10-C-DO_2 Camera (P9)
+48 PB11 PB11-MP3-RST MP3
+ PB11-C-DO_3 Camera (P9)
+49 VSS_1 DGND
+50 VDD_1 3V3
+
+--- ------ -------------- -------------------------------------------------------------------
+PIN NAME SIGNAL NOTES
+--- ------ -------------- -------------------------------------------------------------------
+
+51 PB12 PB12-SPI2-NSS MP3
+ PB12-C-DO_4 Camera (P9)
+52 PB13 PB13-SPI2-SCK MP3
+ PB13-C-DO_5 Camera (P9)
+53 PB14 PB14-SPI2-MISO MP3
+ PB14-C-DO_6 Camera (P9)
+54 PB15 PB15-SPI2-MOSI MP3
+ PB15-C-DO_7 Camera (P9)
+55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen
+56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen
+57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen
+58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen
+59 PD12 C-LED_EN Camera (P9)
+60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen
+61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen
+62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen
+63 PC6 PC6-MP3-XDCS MP3
+ PC6-C-SIO_C Camera (P9)
+64 PC7 PC7-MP3-DREQ MP3
+ PC7-C-SIO_D Camera (P9)
+65 PC8 PC8-SDIO-D0 SD card, pulled high
+66 PC9 PC9-SDIO-D1 SD card, pulled high
+67 PA8 PA8-C-XCLK Camera (P9)
+68 PA9 PA9-US1-TX MAX3232, DB9 D8
+69 PA10 PA10-US1-RX MAX3232, DB9 D8
+70 PA11 PA11-USBDM USB2.0
+71 PA12 PA12-USBDP USB2.0
+72 PA13 PA13-JTMS JTAG
+73 N/C
+74 VSS_2 DGND
+75 VDD_2 3V3
+
+--- ------ -------------- -------------------------------------------------------------------
+PIN NAME SIGNAL NOTES
+--- ------ -------------- -------------------------------------------------------------------
+
+76 PA14 PA14-JTCK JTAG
+77 PA15 PA15-JTDI JTAG
+78 PC10 PC10-SDIO-D2 SD card, pulled high
+79 PC11 PC10-SDIO-D3 SD card, pulled high
+80 PC12 PC12-SDIO-CLK SD card
+81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen
+82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen
+83 PD2 PD2-SDIO-CMD SD card, pulled high
+84 PD3 PD3-C-WEN Camera (P9)
+85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen
+86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen
+87 PD6 PD6-C-OE Camera (P9)
+88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen
+89 PB3 PB3-JTDO JTAG
+90 PB4 PB4-NJTRST JTAG
+91 PB5 PB5-C-WRST Camera (P9)
+92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02
+93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02
+94 BOOT0 SW3 3V3 or DGND
+95 PB8 PB8-CAN-RX CAN tranceiver, Header 2H
+ PB8-C-DO_0 Camera (P9)
+96 PB9 PB9-CAN-TX CAN tranceiver, Header 2H
+ PB9-C-DO_1 Camera (P9)
+97 PE0 PE0-C-RRST Camera (P9)
+98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen
+99 VSS_3 DGND
+100 VDD_3 3V3
+
+Development Environment
+=======================
+
+ Either Linux or Cygwin on Windows can be used for the development environment.
+ The source has been built only using the GNU toolchain (see below). Other
+ toolchains will likely cause problems. Testing was performed using the Cygwin
+ environment because the CodeSourcery Toolchain. The Raisonance R-Link
+ emulatator and some RIDE7 development tools were used and those tools works
+ only under Windows.
+
+GNU Toolchain Options
+=====================
+
+ The NuttX make system has been modified to support the following different
+ toolchain options.
+
+ 1. The CodeSourcery GNU toolchain,
+ 2. The devkitARM GNU toolchain,
+ 3. Raisonance GNU toolchain, or
+ 4. The NuttX buildroot Toolchain (see below).
+
+ All testing has been conducted using the NuttX buildroot toolchain. However,
+ the make system is setup to default to use the devkitARM toolchain. To use
+ the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to
+ add one of the following configuration options to your .config (or defconfig)
+ file:
+
+ CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows
+ CONFIG_STM32_CODESOURCERYL=y : CodeSourcery under Linux
+ CONFIG_STM32_DEVKITARM=y : devkitARM under Windows
+ CONFIG_STM32_RAISONANCE=y : Raisonance RIDE7 under Windows
+ CONFIG_STM32_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
+
+ If you are not using CONFIG_STM32_BUILDROOT, then you may also have to modify
+ the PATH in the setenv.h file if your make cannot find the tools.
+
+ NOTE: the CodeSourcery (for Windows), devkitARM, and Raisonance toolchains are
+ Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot
+ toolchains are Cygwin and/or Linux native toolchains. There are several limitations
+ to using a Windows based toolchain in a Cygwin environment. The three biggest are:
+
+ 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
+ performed automatically in the Cygwin makefiles using the 'cygpath' utility
+ but you might easily find some new path problems. If so, check out 'cygpath -w'
+
+ 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
+ are used in Nuttx (e.g., include/arch). The make system works around these
+ problems for the Windows tools by copying directories instead of linking them.
+ But this can also cause some confusion for you: For example, you may edit
+ a file in a "linked" directory and find that your changes had no effect.
+ That is because you are building the copy of the file in the "fake" symbolic
+ directory. If you use a Windows toolchain, you should get in the habit of
+ making like this:
+
+ make clean_context all
+
+ An alias in your .bashrc file might make that less painful.
+
+ 3. Dependencies are not made when using Windows versions of the GCC. This is
+ because the dependencies are generated using Windows pathes which do not
+ work with the Cygwin make.
+
+ Support has been added for making dependencies with the windows-native toolchains.
+ That support can be enabled by modifying your Make.defs file as follows:
+
+ - MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ + MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
+
+ If you have problems with the dependency build (for example, if you are not
+ building on C:), then you may need to modify tools/mkdeps.sh
+
+ NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
+ level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
+ -Os.
+
+ NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
+ the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
+ path or will get the wrong version of make.
+
+IDEs
+====
+
+ NuttX is built using command-line make. It can be used with an IDE, but some
+ effort will be required to create the project (There is a simple RIDE project
+ in the RIDE subdirectory).
+
+ Makefile Build
+ --------------
+ Under Eclipse, it is pretty easy to set up an "empty makefile project" and
+ simply use the NuttX makefile to build the system. That is almost for free
+ under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
+ makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
+ there is a lot of help on the internet).
+
+ Native Build
+ ------------
+ Here are a few tips before you start that effort:
+
+ 1) Select the toolchain that you will be using in your .config file
+ 2) Start the NuttX build at least one time from the Cygwin command line
+ before trying to create your project. This is necessary to create
+ certain auto-generated files and directories that will be needed.
+ 3) Set up include pathes: You will need include/, arch/arm/src/stm32,
+ arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
+ 4) All assembly files need to have the definition option -D __ASSEMBLY__
+ on the command line.
+
+ Startup files will probably cause you some headaches. The NuttX startup file
+ is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX
+ one time from the Cygwin command line in order to obtain the pre-built
+ startup object needed by RIDE.
+
+NuttX buildroot Toolchain
+=========================
+
+ A GNU GCC-based toolchain is assumed. The files */setenv.sh should
+ be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
+ different from the default in your PATH variable).
+
+ If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
+ SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
+ This GNU toolchain builds and executes in the Linux or Cygwin environment.
+
+ 1. You must have already configured Nuttx in <some-dir>/nuttx.
+
+ cd tools
+ ./configure.sh fire-stm32v2/<sub-dir>
+
+ 2. Download the latest buildroot package into <some-dir>
+
+ 3. unpack the buildroot tarball. The resulting directory may
+ have versioning information on it like buildroot-x.y.z. If so,
+ rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
+
+ 4. cd <some-dir>/buildroot
+
+ 5. cp configs/cortexm3-defconfig-4.3.3 .config
+
+ 6. make oldconfig
+
+ 7. make
+
+ 8. Edit setenv.h, if necessary, so that the PATH variable includes
+ the path to the newly built binaries.
+
+ See the file configs/README.txt in the buildroot source tree. That has more
+ detailed PLUS some special instructions that you will need to follow if you are
+ building a Cortex-M3 toolchain for Cygwin under Windows.
+
+DFU and JTAG
+============
+
+ Enbling Support for the DFU Bootloader
+ --------------------------------------
+ The linker files in these projects can be configured to indicate that you
+ will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
+ loader or via some JTAG emulator. You can specify the DFU bootloader by
+ adding the following line:
+
+ CONFIG_STM32_DFU=y
+
+ to your .config file. Most of the configurations in this directory are set
+ up to use the DFU loader.
+
+ If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning
+ of FLASH (0x08000000) but will be offset to 0x08003000. This offset is needed
+ to make space for the DFU loader and 0x08003000 is where the DFU loader expects
+ to find new applications at boot time. If you need to change that origin for some
+ other bootloader, you will need to edit the file(s) ld.script.dfu for the
+ configuration.
+
+ The DFU SE PC-based software is available from the STMicro website,
+ http://www.st.com. General usage instructions:
+
+ 1. Convert the NuttX Intel Hex file (nuttx.hex) into a special DFU
+ file (nuttx.dfu)... see below for details.
+ 2. Connect the M3 Wildfire board to your computer using a USB
+ cable.
+ 3. Start the DFU loader on the M3 Wildfire board. You do this by
+ resetting the board while holding the "Key" button. Windows should
+ recognize that the DFU loader has been installed.
+ 3. Run the DFU SE program to load nuttx.dfu into FLASH.
+
+ What if the DFU loader is not in FLASH? The loader code is available
+ inside of the Demo dirctory of the USBLib ZIP file that can be downloaded
+ from the STMicro Website. You can build it using RIDE (or other toolchains);
+ you will need a JTAG emulator to burn it into FLASH the first time.
+
+ In order to use STMicro's built-in DFU loader, you will have to get
+ the NuttX binary into a special format with a .dfu extension. The
+ DFU SE PC_based software installation includes a file "DFU File Manager"
+ conversion program that a file in Intel Hex format to the special DFU
+ format. When you successfully build NuttX, you will find a file called
+ nutt.hex in the top-level directory. That is the file that you should
+ provide to the DFU File Manager. You will end up with a file called
+ nuttx.dfu that you can use with the STMicro DFU SE program.
+
+ Enabling JTAG
+ -------------
+ If you are not using the DFU, then you will probably also need to enable
+ JTAG support. By default, all JTAG support is disabled but there NuttX
+ configuration options to enable JTAG in various different ways.
+
+ These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO
+ MAPR register. These bits are used to configure the SWJ and trace alternate function I/Os. The SWJ (SerialWire JTAG) supports JTAG or SWD access to the
+ Cortex debug port. The default state in this port is for all JTAG support
+ to be disable.
+
+ CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full
+ SWJ (JTAG-DP + SW-DP)
+
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable
+ full SWJ (JTAG-DP + SW-DP) but without JNTRST.
+
+ CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP
+ disabled and SW-DP enabled
+
+ The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
+ which disable JTAG-DP and SW-DP.
+
+OpenOCD
+=======
+
+I have also used OpenOCD with the M3 Wildfire. In this case, I used
+the Olimex USB ARM OCD. See the script in configs/fire-stm32v2/tools/oocd.sh
+for more information. Using the script:
+
+1) Start the OpenOCD GDB server
+
+ cd <nuttx-build-directory>
+ configs/fire-stm32v2/tools/oocd.sh $PWD
+
+2) Load Nuttx
+
+ cd <nuttx-built-directory>
+ arm-none-eabi-gdb nuttx
+ gdb> target remote localhost:3333
+ gdb> mon reset
+ gdb> mon halt
+ gdb> load nuttx
+
+3) Running NuttX
+
+ gdb> mon reset
+ gdb> c
+
+LEDs
+====
+
+The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. These LEDs are not
+used by the NuttX port unless CONFIG_ARCH_LEDS is defined. In that case, the
+usage by the board port is defined in include/board.h and src/up_autoleds.c.
+The LEDs are used to encode OS-related events as follows:
+
+ /* LED1 LED2 LED3 */
+ #define LED_STARTED 0 /* OFF OFF OFF */
+ #define LED_HEAPALLOCATE 1 /* ON OFF OFF */
+ #define LED_IRQSENABLED 2 /* OFF ON OFF */
+ #define LED_STACKCREATED 3 /* OFF OFF OFF */
+
+ #define LED_INIRQ 4 /* NC NC ON (momentary) */
+ #define LED_SIGNAL 5 /* NC NC ON (momentary) */
+ #define LED_ASSERTION 6 /* NC NC ON (momentary) */
+ #define LED_PANIC 7 /* NC NC ON (2Hz flashing) */
+ #undef LED_IDLE /* Sleep mode indication not supported */
+
+RTC
+===
+
+ The STM32 RTC may configured using the following settings.
+
+ CONFIG_RTC - Enables general support for a hardware RTC. Specific
+ architectures may require other specific settings.
+ CONFIG_RTC_HIRES - The typical RTC keeps time to resolution of 1
+ second, usually supporting a 32-bit time_t value. In this case,
+ the RTC is used to "seed" the normal NuttX timer and the
+ NuttX timer provides for higher resoution time. If CONFIG_RTC_HIRES
+ is enabled in the NuttX configuration, then the RTC provides higher
+ resolution time and completely replaces the system timer for purpose of
+ date and time.
+ CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the
+ frequency of the high resolution RTC must be provided. If CONFIG_RTC_HIRES
+ is not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
+ CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an alarm.
+ A callback function will be executed when the alarm goes off
+
+ In hi-res mode, the STM32 RTC operates only at 16384Hz. Overflow interrupts
+ are handled when the 32-bit RTC counter overflows every 3 days and 43 minutes.
+ A BKP register is incremented on each overflow interrupt creating, effectively,
+ a 48-bit RTC counter.
+
+ In the lo-res mode, the RTC operates at 1Hz. Overflow interrupts are not handled
+ (because the next overflow is not expected until the year 2106.
+
+ WARNING: Overflow interrupts are lost whenever the STM32 is powered down. The
+ overflow interrupt may be lost even if the STM32 is powered down only momentarily.
+ Therefore hi-res solution is only useful in systems where the power is always on.
+
+M3 Wildfire-specific Configuration Options
+============================================
+
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should
+ be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+ chip:
+
+ CONFIG_ARCH_CHIP_STM32
+ CONFIG_ARCH_CHIP_STM32F103ZET6
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=fire-stm32v2 (for the M3 Wildfire development board)
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_FIRE_STM32V2=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_DRAM_SIZE=0x00010000 (64Kb)
+
+ CONFIG_DRAM_START - The start address of installed DRAM
+
+ CONFIG_DRAM_START=0x20000000
+
+ CONFIG_ARCH_IRQPRIO - The STM32F103Z supports interrupt prioritization
+
+ CONFIG_ARCH_IRQPRIO=y
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+
+ CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+ cause a 100 second delay during boot-up. This 100 second delay
+ serves no purpose other than it allows you to calibratre
+ CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
+ the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
+ the delay actually is 100 seconds.
+
+ Individual subsystems can be enabled:
+ AHB
+ ---
+ CONFIG_STM32_DMA1
+ CONFIG_STM32_DMA2
+ CONFIG_STM32_CRC
+ CONFIG_STM32_FSMC
+ CONFIG_STM32_SDIO
+
+ APB1
+ ----
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_TIM5
+ CONFIG_STM32_TIM6
+ CONFIG_STM32_TIM7
+ CONFIG_STM32_WWDG
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_SPI4
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_UART4
+ CONFIG_STM32_UART5
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_USB
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_BKP
+ CONFIG_STM32_PWR
+ CONFIG_STM32_DAC1
+ CONFIG_STM32_DAC2
+ CONFIG_STM32_USB
+
+ APB2
+ ----
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_SPI1
+ CONFIG_STM32_TIM8
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC3
+
+ Timer and I2C devices may need to the following to force power to be applied
+ unconditionally at power up. (Otherwise, the device is powered when it is
+ initialized).
+
+ CONFIG_STM32_FORCEPOWER
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation, ADC conversion,
+ or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
+ to assign the timer (n) for used by the ADC or DAC, but then you also have to
+ configure which ADC or DAC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,8
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,8
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,8, m=1,..,3
+ CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,8
+ CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,8, m=1,..,2
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ Alternate pin mappings. The M3 Wildfire board requires only CAN1 remapping
+ On the M3 Wildfire board pin PB9 is wired as TX and pin PB8 is wired as RX.
+ Which then makes the proper connection through the CAN transiver SN65HVD230
+ out to the CAN D-type 9-pn male connector where pin 2 is CANL and pin 7 is CANH.
+
+ CONFIG_STM32_TIM1_FULL_REMAP
+ CONFIG_STM32_TIM1_PARTIAL_REMAP
+ CONFIG_STM32_TIM2_FULL_REMAP
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_1
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_2
+ CONFIG_STM32_TIM3_FULL_REMAP
+ CONFIG_STM32_TIM3_PARTIAL_REMAP
+ CONFIG_STM32_TIM4_REMAP
+ CONFIG_STM32_USART1_REMAP
+ CONFIG_STM32_USART2_REMAP
+ CONFIG_STM32_USART3_FULL_REMAP
+ CONFIG_STM32_USART3_PARTIAL_REMAP
+ CONFIG_STM32_SPI1_REMAP
+ CONFIG_STM32_SPI3_REMAP
+ CONFIG_STM32_I2C1_REMAP
+ CONFIG_STM32_CAN1_REMAP1
+ CONFIG_STM32_CAN1_REMAP2
+ CONFIG_STM32_CAN2_REMAP
+
+ JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STM32F103Z specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+ m (m=4,5) for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPI_DMA - Use DMA to improve SPI transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+ CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO
+ and CONFIG_STM32_DMA2.
+ CONFIG_SDIO_PRI - Select SDIO interrupt prority. Default: 128
+ CONFIG_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
+ Default: Medium
+ CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
+ 4-bit transfer mode.
+
+ M3 Wildfire CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
+ Standard 11-bit IDs.
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined.
+ CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2 is defined.
+ CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
+ CONFIG_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
+ CONFIG_CAN_REGDEBUG - If CONFIG_DEBUG is set, this will generate an
+ dump of all CAN registers.
+
+ M3 Wildfire LCD Hardware Configuration
+
+ CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
+ support. Default is this 320x240 "landscape" orientation
+ (this setting is informative only... not used).
+ CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
+ orientation support. In this orientation, the M3 Wildfire's
+ LCD ribbon cable is at the bottom of the display. Default is
+ 320x240 "landscape" orientation.
+ CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
+ portrait" orientation support. In this orientation, the
+ M3 Wildfire's LCD ribbon cable is at the top of the display.
+ Default is 320x240 "landscape" orientation.
+ CONFIG_LCD_BACKLIGHT - Define to support a backlight.
+ CONFIG_LCD_PWM - If CONFIG_STM32_TIM1 is also defined, then an
+ adjustable backlight will be provided using timer 1 to generate
+ various pulse widthes. The granularity of the settings is
+ determined by CONFIG_LCD_MAXPOWER. If CONFIG_LCD_PWM (or
+ CONFIG_STM32_TIM1) is not defined, then a simple on/off backlight
+ is provided.
+ CONFIG_LCD_RDSHIFT - When reading 16-bit gram data, there appears
+ to be a shift in the returned data. This value fixes the offset.
+ Default 5.
+
+ The LCD driver dynamically selects the LCD based on the reported LCD
+ ID value. However, code size can be reduced by suppressing support for
+ individual LCDs using:
+
+ CONFIG_STM32_AM240320_DISABLE
+ CONFIG_STM32_SPFD5408B_DISABLE
+ CONFIG_STM32_R61580_DISABLE
+
+Configurations
+==============
+
+Each M3 Wildfire configuration is maintained in a sudirectory and
+can be selected as follow:
+
+ cd tools
+ ./configure.sh fire-stm32v2/<subdir>
+ cd -
+ . ./setenv.sh
+
+Where <subdir> is one of the following:
+
+ nsh
+ ---
+ Configure the NuttShell (nsh) located at examples/nsh. The nsh configuration
+ contains support for some built-in applications that can be enabled by making
+ some additional minor change to the configuration file.
diff --git a/nuttx/configs/fire-stm32v2/include/board.h b/nuttx/configs/fire-stm32v2/include/board.h new file mode 100644 index 000000000..50a3d2985 --- /dev/null +++ b/nuttx/configs/fire-stm32v2/include/board.h @@ -0,0 +1,394 @@ +/************************************************************************************ + * configs/fire-stm32v2/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_FIRE_STM32V2_INCLUDE_BOARD_H +#define __CONFIGS_FIRE_STM32V2_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#ifndef __ASSEMBLY__ +# include <stdint.h> +#endif +#include "stm32_rcc.h" +#include "stm32_sdio.h" +#include "stm32_internal.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 */ + +#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions ******************************************************************/ +/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. These LEDs are not + * used by the NuttX port unless CONFIG_ARCH_LEDS is defined. In that case, the + * usage by the board port is defined in include/board.h and src/up_autoleds.c. + * The LEDs are used to encode OS-related events as follows: + *. + /* LED1 LED2 LED3 */ +#define LED_STARTED 0 /* OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* ON OFF OFF */ +#define LED_IRQSENABLED 2 /* OFF ON OFF */ +#define LED_STACKCREATED 3 /* OFF OFF OFF */ + +#define LED_INIRQ 4 /* NC NC ON (momentary) */ +#define LED_SIGNAL 5 /* NC NC ON (momentary) */ +#define LED_ASSERTION 6 /* NC NC ON (momentary) */ +#define LED_PANIC 7 /* NC NC ON (2Hz flashing) */ +#undef LED_IDLE /* Sleep mode indication not supported */ + +/* The M3 Wildfire supports several two user buttons: KEY1 and KEY2 */ + +#define BUTTON_KEY1 0 +#define BUTTON_KEY2 1 +#define NUM_BUTTONS 2 + +#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) +#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) + +/* Pin Remapping ********************************************************************/ +/* USB 2.0 + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 70 PA11 PA11-USBDM USB2.0 + * 71 PA12 PA12-USBDP USB2.0 + * 2 PE3 PE3-USB-M USB2.0 + */ + +/* 2.4" TFT + Touchscreen + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + * 7 PC13 PD13_LCD_LIGHT 2.4" TFT + Touchscreen + * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen + * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen + * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen + * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen + * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen + * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen + * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen + * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen + * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen + * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen + * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen + * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen + * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen + * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen + * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen + * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen + * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen + * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen + * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen + * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen + * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen + */ + +/* AT24C02 + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + */ + +/* Potentiometer/ADC + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 16 PC1 PC1/ADC123-IN11 Potentiometer (R16) + * 24 PA1 PC1/ADC123-IN11 + */ + +/* USARTs + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 25 PA2 PA2-US2-TX MAX3232, DB9 D7 + * 26 PA3 PA3-US2-RX MAX3232, DB9 D7 + * 68 PA9 PA9-US1-TX MAX3232, DB9 D8 + * 69 PA10 PA10-US1-RX MAX3232, DB9 D8 + */ + +/* ENC28J60 + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + */ + +/* MP3 + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 48 PB11 PB11-MP3-RST MP3 + * 51 PB12 PB12-SPI2-NSS MP3 + * 52 PB13 PB13-SPI2-SCK MP3 + * 53 PB14 PB14-SPI2-MISO MP3 + * 54 PB15 PB15-SPI2-MOSI MP3 + * 63 PC6 PC6-MP3-XDCS MP3 + * 64 PC7 PC7-MP3-DREQ MP3 + */ + +/* SD Card + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 65 PC8 PC8-SDIO-D0 SD card, pulled high + * 66 PC9 PC9-SDIO-D1 SD card, pulled high + * 78 PC10 PC10-SDIO-D2 SD card, pulled high + * 79 PC11 PC10-SDIO-D3 SD card, pulled high + * 80 PC12 PC12-SDIO-CLK SD card + * 83 PD2 PD2-SDIO-CMD SD card, pulled high + */ + +/* CAN + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 95 PB8 PB8-CAN-RX CAN tranceiver, Header 2H + * 96 PB9 PB9-CAN-TX CAN tranceiver, Header 2H + */ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +EXTERN void stm32_boardinitialize(void); + +/************************************************************************************ + * Button support. + * + * Description: + * up_buttoninit() must be called to initialize button resources. After + * that, up_buttons() may be called to collect the current state of all + * buttons or up_irqbutton() may be called to register button interrupt + * handlers. + * + * After up_buttoninit() has been called, up_buttons() may be called to + * collect the state of all buttons. up_buttons() returns an 8-bit bit set + * with each bit associated with a button. See the BUTTON_*_BIT and JOYSTICK_*_BIT + * definitions in board.h for the meaning of each bit. + * + * up_irqbutton() may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See the + * BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of enumeration + * value. The previous interrupt handler address is returned (so that it may + * restored, if so desired). + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_BUTTONS +EXTERN void up_buttoninit(void); +EXTERN uint8_t up_buttons(void); +#ifdef CONFIG_ARCH_IRQBUTTONS +EXTERN xcpt_t up_irqbutton(int id, xcpt_t irqhandler); +#endif +#endif + +/************************************************************************************ + * Name: stm32_ledinit, stm32_setled, and stm32_setleds + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If + * CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to + * control the LEDs from user applications. + * + ************************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +EXTERN void stm32_ledinit(void); +EXTERN void stm32_setled(int led, bool ledon); +EXTERN void stm32_setleds(uint8_t ledset); +#endif + +/************************************************************************************ + * Name: fire_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the M3 Wildfire board. Because + * of the various rotations, clearing the display in the normal way by writing a + * sequences of runs that covers the entire display can be very slow. Here the + * dispaly is cleared by simply setting all GRAM memory to the specified color. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +EXTERN void fire_lcdclear(uint16_t color); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_FIRE_STM32V2_INCLUDE_BOARD_H */ diff --git a/nuttx/configs/fire-stm32v2/src/fire-internal.h b/nuttx/configs/fire-stm32v2/src/fire-internal.h new file mode 100644 index 000000000..b3d6e145b --- /dev/null +++ b/nuttx/configs/fire-stm32v2/src/fire-internal.h @@ -0,0 +1,229 @@ +/************************************************************************************ + * configs/fire-stm32v2/src/fire-internal.h + * arch/arm/src/board/fire-internal.n + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_FIRE_STM32V2_SRC_FIRE_INTERNAL_H +#define __CONFIGS_FIRE_STM32V2_SRC_FIRE_INTERNAL_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <nuttx/compiler.h> +#include <stdint.h> + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* How many SPI modules does this chip support? Most support 2 SPI modules (others + * may support more -- in such case, the following must be expanded). + */ + +#if STM32_NSPI < 1 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32_SPI2 +#endif + +/* There is only CAN1 on the M3 Wildfire board */ + +#if defined(CONFIG_STM32_CAN2) +# warning "The M3 Wildfire only supports CAN1" +#endif + +/* M3 Wildfire GPIOs ****************************************************************/ +/* Camera + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 23 PA0 PA0-C-VSYNC Camera (P9) + * 67 PA8 PA8-C-XCLK Camera (P9) + * 91 PB5 PB5-C-WRST Camera (P9) + * 95 PB8 PB8-C-DO_0 Camera (P9) + * 96 PB9 PB9-C-DO_1 Camera (P9) + * 47 PB10 PB10-C-DO_2 Camera (P9) + * 48 PB11 PB11-C-DO_3 Camera (P9) + * 51 PB12 PB12-C-DO_4 Camera (P9) + * 52 PB13 PB13-C-DO_5 Camera (P9) + * 53 PB14 PB14-C-DO_6 Camera (P9) + * 54 PB15 PB15-C-DO_7 Camera (P9) + * 63 PC6 PC6-C-SIO_C Camera (P9) + * 64 PC7 PC7-C-SIO_D Camera (P9) + * 84 PD3 PD3-C-WEN Camera (P9) + * 87 PD6 PD6-C-OE Camera (P9) + * 59 PD12 C-LED_EN Camera (P9) + * 97 PE0 PE0-C-RRST Camera (P9) + * 1 PE2 PE2-C-RCLK Camera (P9) + */ + +/* Bell + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 3 PE4 PE4-BEEP LS1 Bell + */ + +/* 2.4" TFT + Touchscreen + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + * 7 PC13 PD13_LCD_LIGHT 2.4" TFT + Touchscreen + * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen + * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen + * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen + * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen + * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen + * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen + * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen + * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen + * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen + * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen + * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen + * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen + * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen + * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen + * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen + * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen + * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen + * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen + * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen + * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen + * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen + */ + +#define GPIO_LCD_BACKLIGHT (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTD|GPIO_PIN13) + +/* LEDs + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 18 PC3 PC3-LED1 LED1, Active low (pulled high) + * 33 PC4 PC4-LED2 LED2, Active low (pulled high) + * 34 PC5 PC5-LED3 LED3, Active low (pulled high) + */ + +#define GPIO_LED1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN3) +#define GPIO_LED2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN4) +#define GPIO_LED3 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +/* Buttons + * + * --- ------ -------------- ------------------------------------------------------------------- + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------------------------- + * + * 35 PB0 PB0-KEY1 KEY1, Low when closed (pulled high if open) + * 36 PB1 PB1-KEY2 KEY2, Low when closed (pulled high if open) + */ + +#define MIN_IRQBUTTON BUTTON_KEY1 +#define MAX_IRQBUTTON BUTTON_KEY2 +#define NUM_IRQBUTTONS (MAX_IRQBUTTON - MIN_IRQBUTTON + 1) + +#define GPIO_BTN_KEY1 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\ + GPIO_PORTB|GPIO_PIN0) +#define GPIO_BTN_KEY2 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\ + GPIO_PORTB|GPIO_PIN1) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the M3 Wildfire board. + * + ************************************************************************************/ + +void weak_function stm32_spiinitialize(void); + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the M3 Wildfire board. + * + ************************************************************************************/ + +void weak_function stm32_usbinitialize(void); + +/************************************************************************************ + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm32_selectlcd(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_FIRE_STM32V2_SRC_FIRE_INTERNAL_H */ + diff --git a/nuttx/configs/shenzhou/include/board.h b/nuttx/configs/shenzhou/include/board.h index 560fe1e00..2e82742ec 100644 --- a/nuttx/configs/shenzhou/include/board.h +++ b/nuttx/configs/shenzhou/include/board.h @@ -330,6 +330,37 @@ void stm32_board_clockconfig(void); #endif /************************************************************************************ + * Button support. + * + * Description: + * up_buttoninit() must be called to initialize button resources. After + * that, up_buttons() may be called to collect the current state of all + * buttons or up_irqbutton() may be called to register button interrupt + * handlers. + * + * After up_buttoninit() has been called, up_buttons() may be called to + * collect the state of all buttons. up_buttons() returns an 8-bit bit set + * with each bit associated with a button. See the BUTTON_*_BIT and JOYSTICK_*_BIT + * definitions in board.h for the meaning of each bit. + * + * up_irqbutton() may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See the + * BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of enumeration + * value. The previous interrupt handler address is returned (so that it may + * restored, if so desired). + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_BUTTONS +EXTERN void up_buttoninit(void); +EXTERN uint8_t up_buttons(void); +#ifdef CONFIG_ARCH_IRQBUTTONS +EXTERN xcpt_t up_irqbutton(int id, xcpt_t irqhandler); +#endif +#endif + +/************************************************************************************ * Name: stm32_ledinit, stm32_setled, and stm32_setleds * * Description: |