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| author | Andrew Tridgell <tridge@samba.org> | 2013-08-02 20:25:26 +1000 |
|---|---|---|
| committer | Lorenz Meier <lm@inf.ethz.ch> | 2013-08-04 16:13:48 +0200 |
| commit | 83189a85dacbd56c3aba6ef704d9dd25a85d33da (patch) | |
| tree | de42313502aa6c8ff95c66adaacf6cd31815387f /src/drivers/l3gd20 | |
| parent | c84cdf2ff627fd84c901c869a84d17751323eb97 (diff) | |
| download | px4-firmware-83189a85dacbd56c3aba6ef704d9dd25a85d33da.tar.gz px4-firmware-83189a85dacbd56c3aba6ef704d9dd25a85d33da.tar.bz2 px4-firmware-83189a85dacbd56c3aba6ef704d9dd25a85d33da.zip | |
l3gd20: disable the FIFO
the FIFO was not gaining us anything, and was adding latency. If we
use the FIFO we'd need to do multiple SPI transfers to ensure it is
drained
Diffstat (limited to 'src/drivers/l3gd20')
| -rw-r--r-- | src/drivers/l3gd20/l3gd20.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/drivers/l3gd20/l3gd20.cpp b/src/drivers/l3gd20/l3gd20.cpp index 9b4bda0ae..ce381807f 100644 --- a/src/drivers/l3gd20/l3gd20.cpp +++ b/src/drivers/l3gd20/l3gd20.cpp @@ -342,7 +342,11 @@ L3GD20::init() write_reg(ADDR_CTRL_REG5, 0); write_reg(ADDR_CTRL_REG5, REG5_FIFO_ENABLE); /* disable wake-on-interrupt */ - write_reg(ADDR_FIFO_CTRL_REG, FIFO_CTRL_STREAM_MODE); /* Enable FIFO, old data is overwritten */ + + /* disable FIFO. This makes things simpler and ensures we + * aren't getting stale data. It means we must run the hrt + * callback fast enough to not miss data. */ + write_reg(ADDR_FIFO_CTRL_REG, FIFO_CTRL_BYPASS_MODE); set_range(2000); /* default to 2000dps */ set_samplerate(0); /* max sample rate */ |