diff options
Diffstat (limited to 'nuttx/arch/arm/Kconfig')
| -rw-r--r-- | nuttx/arch/arm/Kconfig | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index 36343e319..5709f890f 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -46,7 +46,6 @@ config ARCH_CHIP_KINETIS bool "Freescale Kinetis" select ARCH_CORTEXM4 select ARCH_HAVE_MPU - select ARCH_IRQPRIO select ARCH_HAVE_RAMFUNCS select ARCH_RAMFUNCS ---help--- @@ -55,7 +54,6 @@ config ARCH_CHIP_KINETIS config ARCH_CHIP_LM bool "TI Stellaris" select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- TI Stellaris LMS3 architecutres (ARM Cortex-M3) @@ -63,7 +61,6 @@ config ARCH_CHIP_LPC17XX bool "NXP LPC17xx" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NXP LPC17xx architectures (ARM Cortex-M3) @@ -95,7 +92,6 @@ config ARCH_CHIP_LPC43XX select ARCH_HAVE_CMNVECTOR select ARMV7M_CMNVECTOR select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NPX LPC43XX architectures (ARM Cortex-M4). @@ -103,7 +99,6 @@ config ARCH_CHIP_SAM3U bool "Atmel AT91SAM3U" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- Atmel AT91SAM3U architectures (ARM Cortex-M3) @@ -112,7 +107,6 @@ config ARCH_CHIP_STM32 select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET - select ARCH_IRQPRIO ---help--- STMicro STM32 architectures (ARM Cortex-M3/4). @@ -136,9 +130,11 @@ config ARCH_ARM920T config ARCH_CORTEXM3 bool + select ARCH_IRQPRIO config ARCH_CORTEXM4 bool + select ARCH_IRQPRIO config ARCH_FAMILY string @@ -162,6 +158,17 @@ config ARCH_CHIP default "stm32" if ARCH_CHIP_STM32 default "str71x" if ARCH_CHIP_STR71X +config ARMV7M_USEBASEPRI + bool "Use BASEPRI Register" + default n + depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 + ---help--- + Use the BASEPRI register to enable and disable able interrupts. By + default, the PRIMASK register is used for this purpose. This + usually results in hardfaults that are properly handling by the + RTOS. Using the BASEPRI register will avoid these hardfault. + That is needed primarily for integration with some toolchains. + config ARCH_HAVE_CMNVECTOR bool |