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-rw-r--r--nuttx/arch/arm/include/armv7-m/irq.h146
-rw-r--r--nuttx/arch/arm/include/armv7-m/irq_cmnvector.h6
-rw-r--r--nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h6
-rw-r--r--nuttx/arch/arm/include/stm32/chip.h48
-rw-r--r--nuttx/arch/arm/include/types.h6
5 files changed, 150 insertions, 62 deletions
diff --git a/nuttx/arch/arm/include/armv7-m/irq.h b/nuttx/arch/arm/include/armv7-m/irq.h
index 606b3988f..8acec4c07 100644
--- a/nuttx/arch/arm/include/armv7-m/irq.h
+++ b/nuttx/arch/arm/include/armv7-m/irq.h
@@ -60,6 +60,10 @@
# include <arch/armv7-m/irq_lazyfpu.h>
#endif
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+# include <arch/chip/chip.h>
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -114,7 +118,11 @@ struct xcptcontext
*/
uint32_t saved_pc;
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ uint32_t saved_basepri;
+#else
uint32_t saved_primask;
+#endif
uint32_t saved_xpsr;
#endif
@@ -130,12 +138,75 @@ struct xcptcontext
#ifndef __ASSEMBLY__
+/* Get/set the PRIMASK register */
+
+static inline uint8_t getprimask(void) inline_function;
+static inline uint8_t getprimask(void)
+{
+ uint32_t primask;
+ __asm__ __volatile__
+ (
+ "\tmrs %0, primask\n"
+ : "=r" (primask)
+ :
+ : "memory");
+
+ return (uint8_t)primask;
+}
+
+static inline void setprimask(uint32_t primask) inline_function;
+static inline void setprimask(uint32_t primask)
+{
+ __asm__ __volatile__
+ (
+ "\tmsr primask, %0\n"
+ :
+ : "r" (primask)
+ : "memory");
+}
+
+/* Get/set the BASEPRI register. The BASEPRI register defines the minimum
+ * priority for exception processing. When BASEPRI is set to a nonzero
+ * value, it prevents the activation of all exceptions with the same or
+ * lower priority level as the BASEPRI value.
+ */
+
+static inline uint8_t getbasepri(void) inline_function;
+static inline uint8_t getbasepri(void)
+{
+ uint32_t basepri;
+
+ __asm__ __volatile__
+ (
+ "\tmrs %0, basepri\n"
+ : "=r" (basepri)
+ :
+ : "memory");
+
+ return (uint8_t)basepri;
+}
+
+static inline void setbasepri(uint32_t basepri) inline_function;
+static inline void setbasepri(uint32_t basepri)
+{
+ __asm__ __volatile__
+ (
+ "\tmsr basepri, %0\n"
+ :
+ : "r" (basepri)
+ : "memory");
+}
+
/* Disable IRQs */
static inline void irqdisable(void) inline_function;
static inline void irqdisable(void)
{
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
+#else
__asm__ __volatile__ ("\tcpsid i\n");
+#endif
}
/* Save the current primask state & disable IRQs */
@@ -143,6 +214,14 @@ static inline void irqdisable(void)
static inline irqstate_t irqsave(void) inline_function;
static inline irqstate_t irqsave(void)
{
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+
+ uint8_t basepri = getbasepri();
+ setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
+ return (irqstate_t)basepri;
+
+#else
+
unsigned short primask;
/* Return the current value of primask register and set
@@ -158,6 +237,7 @@ static inline irqstate_t irqsave(void)
: "memory");
return primask;
+#endif
}
/* Enable IRQs */
@@ -165,14 +245,18 @@ static inline irqstate_t irqsave(void)
static inline void irqenable(void) inline_function;
static inline void irqenable(void)
{
+ setbasepri(0);
__asm__ __volatile__ ("\tcpsie i\n");
}
/* Restore saved primask state */
-static inline void irqrestore(irqstate_t primask) inline_function;
-static inline void irqrestore(irqstate_t primask)
+static inline void irqrestore(irqstate_t flags) inline_function;
+static inline void irqrestore(irqstate_t flags)
{
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ setbasepri((uint32_t)flags);
+#else
/* If bit 0 of the primask is 0, then we need to restore
* interupts.
*/
@@ -184,63 +268,9 @@ static inline void irqrestore(irqstate_t primask)
"\tcpsie i\n"
"1:\n"
:
- : "r" (primask)
- : "memory");
-}
-
-/* Get/set the primask register */
-
-static inline uint8_t getprimask(void) inline_function;
-static inline uint8_t getprimask(void)
-{
- uint32_t primask;
- __asm__ __volatile__
- (
- "\tmrs %0, primask\n"
- : "=r" (primask)
- :
- : "memory");
-
- return (uint8_t)primask;
-}
-
-static inline void setprimask(uint32_t primask) inline_function;
-static inline void setprimask(uint32_t primask)
-{
- __asm__ __volatile__
- (
- "\tmsr primask, %0\n"
- :
- : "r" (primask)
- : "memory");
-}
-
-/* Get/set the basepri register */
-
-static inline uint8_t getbasepri(void) inline_function;
-static inline uint8_t getbasepri(void)
-{
- uint32_t basepri;
-
- __asm__ __volatile__
- (
- "\tmrs %0, basepri\n"
- : "=r" (basepri)
- :
- : "memory");
-
- return (uint8_t)basepri;
-}
-
-static inline void setbasepri(uint32_t basepri) inline_function;
-static inline void setbasepri(uint32_t basepri)
-{
- __asm__ __volatile__
- (
- "\tmsr basepri, %0\n"
- :
- : "r" (basepri)
+ : "r" (flags)
: "memory");
+#endif
}
/* Get/set IPSR */
diff --git a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h
index e646731eb..bc67004ed 100644
--- a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h
+++ b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h
@@ -51,7 +51,11 @@
*/
#define REG_R13 (0) /* R13 = SP at time of interrupt */
-#define REG_PRIMASK (1) /* PRIMASK */
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+# define REG_BASEPRI (1) /* BASEPRI */
+#else
+# define REG_PRIMASK (1) /* PRIMASK */
+#endif
#define REG_R4 (2) /* R4 */
#define REG_R5 (3) /* R5 */
#define REG_R6 (4) /* R6 */
diff --git a/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h b/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h
index 2c3600b7f..f2380cbb6 100644
--- a/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h
+++ b/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h
@@ -51,7 +51,11 @@
*/
#define REG_R13 (0) /* R13 = SP at time of interrupt */
-#define REG_PRIMASK (1) /* PRIMASK */
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+# define REG_BASEPRI (1) /* BASEPRI */
+#else
+# define REG_PRIMASK (1) /* PRIMASK */
+#endif
#define REG_R4 (2) /* R4 */
#define REG_R5 (3) /* R5 */
#define REG_R6 (4) /* R6 */
diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h
index d34c2eb4f..14d92ea3d 100644
--- a/nuttx/arch/arm/include/stm32/chip.h
+++ b/nuttx/arch/arm/include/stm32/chip.h
@@ -183,9 +183,43 @@
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+/* STM32 F103 Medium Density Family *************************************************/
+/* STM32F103RB is in the Medium-density performance line and is provided in 64 pin
+ * packages with 128K Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6)
+# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_VALUELINE /* STM32F100x */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
+# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
+# define STM32_NFSMC 0 /* FSMC */
+# define STM32_NATIM 1 /* One advanced timer TIM1 */
+# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
+# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */
+# define STM32_NDMA 1 /* DMA1 */
+# define STM32_NSPI 2 /* SPI1-2 */
+# define STM32_NI2S 0 /* No I2S (?) */
+# define STM32_NUSART 3 /* USART1-3 */
+# define STM32_NI2C 2 /* I2C1-2 */
+# define STM32_NCAN 1 /* bxCAN1 */
+# define STM32_NSDIO 0 /* No SDIO */
+# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
+# define STM32_NGPIO 51 /* GPIOA-E */
+# define STM32_NADC 2 /* ADC1-2 */
+# define STM32_NDAC 0 /* No DAC */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NTHERNET 0 /* No ethernet */
+# define STM32_NRNG 0 /* No random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+
/* STM32 F103 High Density Family ***************************************************/
-/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ
- * only in the available FLASH and SRAM.
+/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and
+ * differ only in the available FLASH and SRAM.
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
@@ -658,5 +692,15 @@
# error "Unsupported STM32 chip"
#endif
+/* NVIC priority levels *************************************************************/
+
+#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
+
+#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
+
#endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */
diff --git a/nuttx/arch/arm/include/types.h b/nuttx/arch/arm/include/types.h
index c06b28950..1d2ea4cfe 100644
--- a/nuttx/arch/arm/include/types.h
+++ b/nuttx/arch/arm/include/types.h
@@ -44,6 +44,8 @@
* Included Files
****************************************************************************/
+#include <nuttx/config.h>
+
/****************************************************************************
* Definitions
****************************************************************************/
@@ -87,7 +89,11 @@ typedef unsigned int _uintptr_t;
*/
#ifdef __thumb2__
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+typedef unsigned char irqstate_t;
+#else
typedef unsigned short irqstate_t;
+#endif
#else /* __thumb2__ */
typedef unsigned int irqstate_t;
#endif /* __thumb2__ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-13 17:40:04 +0000