diff options
Diffstat (limited to 'nuttx/arch/arm/src/stm32/stm32_irq.c')
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_irq.c | 48 |
1 files changed, 43 insertions, 5 deletions
diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 36a5cf5fa..a952c2486 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_irq.c * arch/arm/src/chip/stm32_irq.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -195,6 +195,29 @@ static int stm32_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: stm32_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void stm32_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** * Name: stm32_irqinfo * * Description: @@ -335,6 +358,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -365,8 +391,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } @@ -451,15 +476,28 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < STM32_IRQ_INTERRUPTS) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } |