diff options
Diffstat (limited to 'nuttx/arch')
32 files changed, 1136 insertions, 197 deletions
diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig index f19228143..c0f235c5d 100644 --- a/nuttx/arch/Kconfig +++ b/nuttx/arch/Kconfig @@ -16,6 +16,7 @@ config ARCH_8051 config ARCH_ARM bool "ARM" select ARCH_HAVE_INTERRUPTSTACK + select ARCH_HAVE_VFORK ---help--- The ARM architectures @@ -102,12 +103,141 @@ source arch/x86/Kconfig source arch/z16/Kconfig source arch/z80/Kconfig +comment "External Memory Configuration" + +config ARCH_HAVE_EXTNAND + bool + +config ARCH_HAVE_EXTNOR + bool + +config ARCH_HAVE_EXTDRAM + bool + +config ARCH_HAVE_EXTSRAM0 + bool + +config ARCH_HAVE_EXTSRAM1 + bool + +config ARCH_EXTNAND + bool "Configure external NAND" + default n + depends on ARCH_HAVE_EXTNAND + ---help--- + Configure external NAND memory and, if applicable, map then external + NAND into the memory map. + +if ARCH_EXTNAND + +config ARCH_EXTNANDSIZE + int "External NAND size" + default 0 + ---help--- + Size of the external NAND in bytes. + +endif + +config ARCH_EXTNOR + bool "Configure external NOR memory" + default n + depends on ARCH_HAVE_EXTNOR + ---help--- + Configure external NOR memory and, if applicable, map then external + NOR into the memory map. + +if ARCH_EXTNOR + +config ARCH_EXTNORSIZE + int "External NOR size" + default 0 + ---help--- + Size of the external NOR in bytes. + +endif + +config ARCH_EXTDRAM + bool "Configure external DRAM" + default n + depends on ARCH_HAVE_EXTDRAM + ---help--- + Configure external DRAM memory and, if applicable, map then external + DRAM into the memory map. + +if ARCH_EXTDRAM + +config ARCH_EXTDRAMSIZE + int "External SDRAM size" + default 0 + ---help--- + Size of the external SDRAM in bytes. + +config ARCH_EXTDRAMHEAP + bool "Add external SDRAM to the heap" + default y + ---help--- + Add the external SDRAM into the heap. + +endif + +config ARCH_EXTSRAM0 + bool "Configure external SRAM (Bank 0)" + default n + depends on ARCH_HAVE_EXTSRAM0 + ---help--- + Configure external SRAM Bank 0 memory and, if applicable, map then + external SRAM Bank 0 into the memory map. + +if ARCH_EXTSRAM0 + +config ARCH_EXTSRAM0SIZE + int "External SRAM size" + default 0 + ---help--- + Size of the external SRAM Bank 0 in bytes. + +config ARCH_EXTSRAM0HEAP + bool "Add external SRAM (Bank 0) to the heap" + default y + ---help--- + Add external SRAM Bank 0 into the heap. + +endif + +config ARCH_EXTSRAM1 + bool "Configure external SRAM (Bank 1)" + default n + depends on ARCH_HAVE_EXTSRAM1 + ---help--- + Configure external SRAM Bank 1 memory and, if applicable, map then + external SRAM Bank 1 into the memory map. + +if ARCH_EXTSRAM1 + +config ARCH_EXTSRAM1SIZE + int "External SRAM1 size" + default 0 + ---help--- + Size of the external SRAM Bank 1 in bytes. + +config ARCH_EXTSRAM1HEAP + bool "Add external SRAM (Bank 1) to the heap" + default y + ---help--- + Add external SRAM Bank 1 into the heap. + +endif + comment "Architecture Options" config ARCH_NOINTC bool default n +config ARCH_VECNOTIRQ + bool + default n + config ARCH_DMA bool default n @@ -124,6 +254,10 @@ config ADDRENV bool default n +config ARCH_HAVE_VFORK + bool + default n + config ARCH_STACKDUMP bool "Dump stack on assertions" default n @@ -136,6 +270,20 @@ config ENDIAN_BIG ---help--- Select if architecture operates using big-endian byte ordering. +config ARCH_HAVE_RAMFUNCS + bool + default n + +config ARCH_RAMFUNCS + bool "Copy functions to RAM on startup" + default n + depends on ARCH_HAVE_RAMFUNCS + ---help--- + Copy some functions to RAM at boot time. This is done in some + architectures to improve performance. In other cases, it is done + so that FLASH can be reconfigured while the MCU executes out of + SRAM. + comment "Board Settings" config BOARD_LOOPSPERMSEC diff --git a/nuttx/arch/README.txt b/nuttx/arch/README.txt index 67b99b255..14704aa76 100644 --- a/nuttx/arch/README.txt +++ b/nuttx/arch/README.txt @@ -170,12 +170,12 @@ arch/arm - ARM-based micro-controllers STATUS: This port has stalled because of development tool issues. Coding is complete on the basic port (timer, serial console, SPI). - arch/arm/include/lm3s and arch/arm/src/lm3s - These directories contain support for the Luminary LMS family, particularly - for the LM3S6918. The initial, release of this port was included in NuttX version - 0.4.6. The current port includes timer, serial console, Ethernet, SSI, and microSD - support. There are working configurations the NuttX OS test, to run the NuttShell - (NSH), the NuttX networking test, and the uIP web server. + arch/arm/include/lm and arch/arm/src/lm + These directories contain support for the Luminary LM3S/4F family. The + initial, release of this port was included in NuttX version 0.4.6. The + current port includes timer, serial console, Ethernet, SSI, and microSD + support. There are working configurations the NuttX OS test, to run the + NuttShell (NSH), the NuttX networking test, and the uIP web server. arch/arm/include/lpc214x and arch/arm/src/lpc214x These directories provide support for NXP LPC214x family of diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig index 4fce8efbf..5709f890f 100644 --- a/nuttx/arch/arm/Kconfig +++ b/nuttx/arch/arm/Kconfig @@ -46,15 +46,14 @@ config ARCH_CHIP_KINETIS bool "Freescale Kinetis" select ARCH_CORTEXM4 select ARCH_HAVE_MPU - select ARCH_IRQPRIO + select ARCH_HAVE_RAMFUNCS + select ARCH_RAMFUNCS ---help--- Freescale Kinetis Architectures (ARM Cortex-M4) -config ARCH_CHIP_LM3S +config ARCH_CHIP_LM bool "TI Stellaris" - select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- TI Stellaris LMS3 architecutres (ARM Cortex-M3) @@ -62,7 +61,6 @@ config ARCH_CHIP_LPC17XX bool "NXP LPC17xx" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NXP LPC17xx architectures (ARM Cortex-M3) @@ -94,7 +92,6 @@ config ARCH_CHIP_LPC43XX select ARCH_HAVE_CMNVECTOR select ARMV7M_CMNVECTOR select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- NPX LPC43XX architectures (ARM Cortex-M4). @@ -102,7 +99,6 @@ config ARCH_CHIP_SAM3U bool "Atmel AT91SAM3U" select ARCH_CORTEXM3 select ARCH_HAVE_MPU - select ARCH_IRQPRIO ---help--- Atmel AT91SAM3U architectures (ARM Cortex-M3) @@ -111,7 +107,6 @@ config ARCH_CHIP_STM32 select ARCH_HAVE_CMNVECTOR select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET - select ARCH_IRQPRIO ---help--- STMicro STM32 architectures (ARM Cortex-M3/4). @@ -135,9 +130,11 @@ config ARCH_ARM920T config ARCH_CORTEXM3 bool + select ARCH_IRQPRIO config ARCH_CORTEXM4 bool + select ARCH_IRQPRIO config ARCH_FAMILY string @@ -151,7 +148,7 @@ config ARCH_CHIP default "dm320" if ARCH_CHIP_DM320 default "imx" if ARCH_CHIP_IMX default "kinetis" if ARCH_CHIP_KINETIS - default "lm3s" if ARCH_CHIP_LM3S + default "lm" if ARCH_CHIP_LM default "lpc17xx" if ARCH_CHIP_LPC17XX default "lpc214x" if ARCH_CHIP_LPC214X default "lpc2378" if ARCH_CHIP_LPC2378 @@ -161,6 +158,17 @@ config ARCH_CHIP default "stm32" if ARCH_CHIP_STM32 default "str71x" if ARCH_CHIP_STR71X +config ARMV7M_USEBASEPRI + bool "Use BASEPRI Register" + default n + depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 + ---help--- + Use the BASEPRI register to enable and disable able interrupts. By + default, the PRIMASK register is used for this purpose. This + usually results in hardfaults that are properly handling by the + RTOS. Using the BASEPRI register will avoid these hardfault. + That is needed primarily for integration with some toolchains. + config ARCH_HAVE_CMNVECTOR bool @@ -274,8 +282,8 @@ endif if ARCH_CHIP_KINETIS source arch/arm/src/kinetis/Kconfig endif -if ARCH_CHIP_LM3S -source arch/arm/src/lm3s/Kconfig +if ARCH_CHIP_LM +source arch/arm/src/lm/Kconfig endif if ARCH_CHIP_LPC17XX source arch/arm/src/lpc17xx/Kconfig diff --git a/nuttx/arch/arm/include/armv7-m/irq.h b/nuttx/arch/arm/include/armv7-m/irq.h index 606b3988f..8acec4c07 100644 --- a/nuttx/arch/arm/include/armv7-m/irq.h +++ b/nuttx/arch/arm/include/armv7-m/irq.h @@ -60,6 +60,10 @@ # include <arch/armv7-m/irq_lazyfpu.h> #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI +# include <arch/chip/chip.h> +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -114,7 +118,11 @@ struct xcptcontext */ uint32_t saved_pc; +#ifdef CONFIG_ARMV7M_USEBASEPRI + uint32_t saved_basepri; +#else uint32_t saved_primask; +#endif uint32_t saved_xpsr; #endif @@ -130,12 +138,75 @@ struct xcptcontext #ifndef __ASSEMBLY__ +/* Get/set the PRIMASK register */ + +static inline uint8_t getprimask(void) inline_function; +static inline uint8_t getprimask(void) +{ + uint32_t primask; + __asm__ __volatile__ + ( + "\tmrs %0, primask\n" + : "=r" (primask) + : + : "memory"); + + return (uint8_t)primask; +} + +static inline void setprimask(uint32_t primask) inline_function; +static inline void setprimask(uint32_t primask) +{ + __asm__ __volatile__ + ( + "\tmsr primask, %0\n" + : + : "r" (primask) + : "memory"); +} + +/* Get/set the BASEPRI register. The BASEPRI register defines the minimum + * priority for exception processing. When BASEPRI is set to a nonzero + * value, it prevents the activation of all exceptions with the same or + * lower priority level as the BASEPRI value. + */ + +static inline uint8_t getbasepri(void) inline_function; +static inline uint8_t getbasepri(void) +{ + uint32_t basepri; + + __asm__ __volatile__ + ( + "\tmrs %0, basepri\n" + : "=r" (basepri) + : + : "memory"); + + return (uint8_t)basepri; +} + +static inline void setbasepri(uint32_t basepri) inline_function; +static inline void setbasepri(uint32_t basepri) +{ + __asm__ __volatile__ + ( + "\tmsr basepri, %0\n" + : + : "r" (basepri) + : "memory"); +} + /* Disable IRQs */ static inline void irqdisable(void) inline_function; static inline void irqdisable(void) { +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri(NVIC_SYSH_DISABLE_PRIORITY); +#else __asm__ __volatile__ ("\tcpsid i\n"); +#endif } /* Save the current primask state & disable IRQs */ @@ -143,6 +214,14 @@ static inline void irqdisable(void) static inline irqstate_t irqsave(void) inline_function; static inline irqstate_t irqsave(void) { +#ifdef CONFIG_ARMV7M_USEBASEPRI + + uint8_t basepri = getbasepri(); + setbasepri(NVIC_SYSH_DISABLE_PRIORITY); + return (irqstate_t)basepri; + +#else + unsigned short primask; /* Return the current value of primask register and set @@ -158,6 +237,7 @@ static inline irqstate_t irqsave(void) : "memory"); return primask; +#endif } /* Enable IRQs */ @@ -165,14 +245,18 @@ static inline irqstate_t irqsave(void) static inline void irqenable(void) inline_function; static inline void irqenable(void) { + setbasepri(0); __asm__ __volatile__ ("\tcpsie i\n"); } /* Restore saved primask state */ -static inline void irqrestore(irqstate_t primask) inline_function; -static inline void irqrestore(irqstate_t primask) +static inline void irqrestore(irqstate_t flags) inline_function; +static inline void irqrestore(irqstate_t flags) { +#ifdef CONFIG_ARMV7M_USEBASEPRI + setbasepri((uint32_t)flags); +#else /* If bit 0 of the primask is 0, then we need to restore * interupts. */ @@ -184,63 +268,9 @@ static inline void irqrestore(irqstate_t primask) "\tcpsie i\n" "1:\n" : - : "r" (primask) - : "memory"); -} - -/* Get/set the primask register */ - -static inline uint8_t getprimask(void) inline_function; -static inline uint8_t getprimask(void) -{ - uint32_t primask; - __asm__ __volatile__ - ( - "\tmrs %0, primask\n" - : "=r" (primask) - : - : "memory"); - - return (uint8_t)primask; -} - -static inline void setprimask(uint32_t primask) inline_function; -static inline void setprimask(uint32_t primask) -{ - __asm__ __volatile__ - ( - "\tmsr primask, %0\n" - : - : "r" (primask) - : "memory"); -} - -/* Get/set the basepri register */ - -static inline uint8_t getbasepri(void) inline_function; -static inline uint8_t getbasepri(void) -{ - uint32_t basepri; - - __asm__ __volatile__ - ( - "\tmrs %0, basepri\n" - : "=r" (basepri) - : - : "memory"); - - return (uint8_t)basepri; -} - -static inline void setbasepri(uint32_t basepri) inline_function; -static inline void setbasepri(uint32_t basepri) -{ - __asm__ __volatile__ - ( - "\tmsr basepri, %0\n" - : - : "r" (basepri) + : "r" (flags) : "memory"); +#endif } /* Get/set IPSR */ diff --git a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h index e646731eb..bc67004ed 100644 --- a/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h +++ b/nuttx/arch/arm/include/armv7-m/irq_cmnvector.h @@ -51,7 +51,11 @@ */ #define REG_R13 (0) /* R13 = SP at time of interrupt */ -#define REG_PRIMASK (1) /* PRIMASK */ +#ifdef CONFIG_ARMV7M_USEBASEPRI +# define REG_BASEPRI (1) /* BASEPRI */ +#else +# define REG_PRIMASK (1) /* PRIMASK */ +#endif #define REG_R4 (2) /* R4 */ #define REG_R5 (3) /* R5 */ #define REG_R6 (4) /* R6 */ diff --git a/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h b/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h index 2c3600b7f..f2380cbb6 100644 --- a/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h +++ b/nuttx/arch/arm/include/armv7-m/irq_lazyfpu.h @@ -51,7 +51,11 @@ */ #define REG_R13 (0) /* R13 = SP at time of interrupt */ -#define REG_PRIMASK (1) /* PRIMASK */ +#ifdef CONFIG_ARMV7M_USEBASEPRI +# define REG_BASEPRI (1) /* BASEPRI */ +#else +# define REG_PRIMASK (1) /* PRIMASK */ +#endif #define REG_R4 (2) /* R4 */ #define REG_R5 (3) /* R5 */ #define REG_R6 (4) /* R6 */ diff --git a/nuttx/arch/arm/include/stm32/chip.h b/nuttx/arch/arm/include/stm32/chip.h index d34c2eb4f..14d92ea3d 100644 --- a/nuttx/arch/arm/include/stm32/chip.h +++ b/nuttx/arch/arm/include/stm32/chip.h @@ -183,9 +183,43 @@ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ +/* STM32 F103 Medium Density Family *************************************************/ +/* STM32F103RB is in the Medium-density performance line and is provided in 64 pin + * packages with 128K Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6) +# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */ +# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */ +# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */ +# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */ +# undef CONFIG_STM32_VALUELINE /* STM32F100x */ +# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */ +# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */ +# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2,3,4 */ +# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NTHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + /* STM32 F103 High Density Family ***************************************************/ -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ - * only in the available FLASH and SRAM. +/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and + * differ only in the available FLASH and SRAM. */ #elif defined(CONFIG_ARCH_CHIP_STM32F103RET6) @@ -658,5 +692,15 @@ # error "Unsupported STM32 chip" #endif +/* NVIC priority levels *************************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX + #endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/nuttx/arch/arm/include/types.h b/nuttx/arch/arm/include/types.h index c06b28950..1d2ea4cfe 100644 --- a/nuttx/arch/arm/include/types.h +++ b/nuttx/arch/arm/include/types.h @@ -44,6 +44,8 @@ * Included Files ****************************************************************************/ +#include <nuttx/config.h> + /**************************************************************************** * Definitions ****************************************************************************/ @@ -87,7 +89,11 @@ typedef unsigned int _uintptr_t; */ #ifdef __thumb2__ +#ifdef CONFIG_ARMV7M_USEBASEPRI +typedef unsigned char irqstate_t; +#else typedef unsigned short irqstate_t; +#endif #else /* __thumb2__ */ typedef unsigned int irqstate_t; #endif /* __thumb2__ */ diff --git a/nuttx/arch/arm/src/armv7-m/Kconfig b/nuttx/arch/arm/src/armv7-m/Kconfig index dc5aa3915..a154a4c5c 100644 --- a/nuttx/arch/arm/src/armv7-m/Kconfig +++ b/nuttx/arch/arm/src/armv7-m/Kconfig @@ -49,3 +49,11 @@ config ARMV7M_TOOLCHAIN_RAISONANCE depends on HOST_WINDOWS endchoice + +config ARMV7M_OABI_TOOLCHAIN + bool "OABI (vs EABI)" + default y + depends on ARMV7M_TOOLCHAIN_BUILDROOT + ---help--- + Most of the older buildroot toolchains are OABI and are named arm-nuttx-elf- vs. arm-nuttx-eabi- + diff --git a/nuttx/arch/arm/src/armv7-m/Toolchain.defs b/nuttx/arch/arm/src/armv7-m/Toolchain.defs index e214ce8bd..45ee9e36c 100644 --- a/nuttx/arch/arm/src/armv7-m/Toolchain.defs +++ b/nuttx/arch/arm/src/armv7-m/Toolchain.defs @@ -53,7 +53,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_BUILDROOT) \ - $(CONFIG_LM3S_BUILDROOT) \ + $(CONFIG_LM_BUILDROOT) \ $(CONFIG_LPC17_BUILDROOT) \ $(CONFIG_LPC43_BUILDROOT) \ $(CONFIG_SAM3U_BUILDROOT) \ @@ -77,7 +77,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_CODESOURCERYL) \ - $(CONFIG_LM3S_CODESOURCERYL) \ + $(CONFIG_LM_CODESOURCERYL) \ $(CONFIG_LPC17_CODESOURCERYL) \ $(CONFIG_LPC43_CODESOURCERYL) \ $(CONFIG_SAM3U_CODESOURCERYL) \ @@ -88,7 +88,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_CODESOURCERYW) \ - $(CONFIG_LM3S_CODESOURCERYW) \ + $(CONFIG_LM_CODESOURCERYW) \ $(CONFIG_LPC17_CODESOURCERYW) \ $(CONFIG_LPC43_CODESOURCERYW) \ $(CONFIG_SAM3U_CODESOURCERYW) \ @@ -99,7 +99,7 @@ ifeq ($(filter y, \ endif ifeq ($(filter y, \ $(CONFIG_KINETIS_DEVKITARM) \ - $(CONFIG_LM3S_DEVKITARM) \ + $(CONFIG_LM_DEVKITARM) \ $(CONFIG_LPC17_DEVKITARM) \ $(CONFIG_LPC43_DEVKITARM) \ $(CONFIG_SAM3U_DEVKITARM) \ @@ -160,14 +160,15 @@ endif # NuttX buildroot under Linux or Cygwin ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),BUILDROOT) - # OABI - # CROSSDEV = arm-nuttx-elf- - # ARCROSSDEV = arm-nuttx-elf- - # ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft - # EABI +ifeq ($(CONFIG_ARMV7M_OABI_TOOLCHAIN),y) + CROSSDEV = arm-nuttx-elf- + ARCROSSDEV = arm-nuttx-elf- + ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft +else CROSSDEV = arm-nuttx-eabi- ARCROSSDEV = arm-nuttx-eabi- ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft +endif MAXOPTIMIZATION = -Os endif diff --git a/nuttx/arch/arm/src/armv7-m/up_assert.c b/nuttx/arch/arm/src/armv7-m/up_assert.c index 282ff6a57..ab30b09f3 100644 --- a/nuttx/arch/arm/src/armv7-m/up_assert.c +++ b/nuttx/arch/arm/src/armv7-m/up_assert.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_assert.c * - * Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -147,8 +147,13 @@ static inline void up_registerdump(void) current_regs[REG_R10], current_regs[REG_R11], current_regs[REG_R12], current_regs[REG_R13], current_regs[REG_R14], current_regs[REG_R15]); +#ifdef CONFIG_ARMV7M_USEBASEPRI + lldbg("xPSR: %08x BASEPRI: %08x\n", + current_regs[REG_XPSR], current_regs[REG_BASEPRI]); +#else lldbg("xPSR: %08x PRIMASK: %08x\n", current_regs[REG_XPSR], current_regs[REG_PRIMASK]); +#endif } } #else diff --git a/nuttx/arch/arm/src/armv7-m/up_doirq.c b/nuttx/arch/arm/src/armv7-m/up_doirq.c index 375054fba..6063f9ca1 100644 --- a/nuttx/arch/arm/src/armv7-m/up_doirq.c +++ b/nuttx/arch/arm/src/armv7-m/up_doirq.c @@ -79,9 +79,11 @@ uint32_t *up_doirq(int irq, uint32_t *regs) uint32_t *savestate; /* Nested interrupts are not supported in this implementation. If you want - * implemented nested interrupts, you would have to (1) change the way that - * current regs is handled and (2) the design associated with - * CONFIG_ARCH_INTERRUPTSTACK. + * to implement nested interrupts, you would have to (1) change the way that + * current_regs is handled and (2) the design associated with + * CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for + * that purpose as implemented here because only the outermost nested + * interrupt can result in a context switch (it can probably be deleted). */ /* Current regs non-zero indicates that we are processing an interrupt; diff --git a/nuttx/arch/arm/src/armv7-m/up_exception.S b/nuttx/arch/arm/src/armv7-m/up_exception.S index c9f216027..17344db41 100644 --- a/nuttx/arch/arm/src/armv7-m/up_exception.S +++ b/nuttx/arch/arm/src/armv7-m/up_exception.S @@ -2,7 +2,7 @@ * arch/arm/src/stm32/up_exception.S * arch/arm/src/chip/up_exception.S * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Copyright (C) 2012 Michael Smith. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * @@ -100,7 +100,11 @@ exception_common: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ /* (ignoring the xPSR[9] alignment bit) */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_ARCH_FPU @@ -205,7 +209,12 @@ exception_common: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) select the correct stack. diff --git a/nuttx/arch/arm/src/armv7-m/up_hardfault.c b/nuttx/arch/arm/src/armv7-m/up_hardfault.c index c30015ad2..fa750b525 100644 --- a/nuttx/arch/arm/src/armv7-m/up_hardfault.c +++ b/nuttx/arch/arm/src/armv7-m/up_hardfault.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_hardfault.c * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -55,7 +55,9 @@ * Pre-processor Definitions ****************************************************************************/ -/* Debug output from this file may interfere with context switching! */ +/* If CONFIG_ARMV7M_USEBASEPRI=n, then debug output from this file may + * interfere with context switching! + */ #ifdef CONFIG_DEBUG_HARDFAULT # define hfdbg(format, arg...) lldbg(format, ##arg) @@ -92,18 +94,19 @@ int up_hardfault(int irq, FAR void *context) { +#if defined(CONFIG_DEBUG_HARDFAULT) || !defined(CONFIG_ARMV7M_USEBASEPRI) uint32_t *regs = (uint32_t*)context; - uint16_t *pc; - uint16_t insn; +#endif /* Get the value of the program counter where the fault occurred */ - pc = (uint16_t*)regs[REG_PC] - 1; +#ifndef CONFIG_ARMV7M_USEBASEPRI + uint16_t *pc = (uint16_t*)regs[REG_PC] - 1; if ((void*)pc >= (void*)&_stext && (void*)pc < (void*)&_etext) { /* Fetch the instruction that caused the Hard fault */ - insn = *pc; + uint16_t insn = *pc; hfdbg(" PC: %p INSN: %04x\n", pc, insn); /* If this was the instruction 'svc 0', then forward processing @@ -116,6 +119,7 @@ int up_hardfault(int irq, FAR void *context) return up_svcall(irq, context); } } +#endif /* Dump some hard fault info */ @@ -133,7 +137,13 @@ int up_hardfault(int irq, FAR void *context) hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); - hfdbg(" PSR=%08x\n", regs[REG_XPSR]); +#ifdef CONFIG_ARMV7M_USEBASEPRI + hfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n", + current_regs[REG_XPSR], current_regs[REG_BASEPRI]); +#else + hfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n", + current_regs[REG_XPSR], current_regs[REG_PRIMASK]); +#endif (void)irqsave(); lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS)); diff --git a/nuttx/arch/arm/src/armv7-m/up_initialstate.c b/nuttx/arch/arm/src/armv7-m/up_initialstate.c index 52a2682a0..4af553f25 100644 --- a/nuttx/arch/arm/src/armv7-m/up_initialstate.c +++ b/nuttx/arch/arm/src/armv7-m/up_initialstate.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_initialstate.c * - * Copyright (C) 2009, 2011-2 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -156,7 +156,7 @@ void up_initial_state(_TCB *tcb) xcp->regs[REG_FPSCR] = 0; // XXX initial FPSCR should be configurable xcp->regs[REG_FPReserved] = 0; -#endif +#endif /* CONFIG_ARCH_FPU */ #ifdef CONFIG_NUTTX_KERNEL if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) @@ -165,7 +165,7 @@ void up_initial_state(_TCB *tcb) xcp->regs[REG_EXC_RETURN] = EXC_RETURN_PROCESS_STACK; } -#endif +#endif /* CONFIG_NUTTX_KERNEL */ #else /* CONFIG_ARMV7M_CMNVECTOR */ @@ -189,12 +189,16 @@ void up_initial_state(_TCB *tcb) xcp->regs[REG_EXC_RETURN] = EXC_RETURN_UNPRIVTHR; } -#endif +#endif /* CONFIG_NUTTX_KERNEL */ #endif /* CONFIG_ARMV7M_CMNVECTOR */ /* Enable or disable interrupts, based on user configuration */ #ifdef CONFIG_SUPPRESS_INTERRUPTS +#ifdef CONFIG_ARMV7M_USEBASEPRI + xcp->regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; +#else xcp->regs[REG_PRIMASK] = 1; #endif +#endif /* CONFIG_SUPPRESS_INTERRUPTS */ } diff --git a/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c b/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c index 9e6dbd14b..9221a69a2 100644 --- a/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c +++ b/nuttx/arch/arm/src/armv7-m/up_schedulesigaction.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_schedulesigaction.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -155,7 +155,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) tcb->xcp.sigdeliver = sigdeliver; tcb->xcp.saved_pc = current_regs[REG_PC]; +#ifdef CONFIG_ARMV7M_USEBASEPRI + tcb->xcp.saved_basepri = current_regs[REG_BASEPRI]; +#else tcb->xcp.saved_primask = current_regs[REG_PRIMASK]; +#endif tcb->xcp.saved_xpsr = current_regs[REG_XPSR]; /* Then set up to vector to the trampoline with interrupts @@ -163,7 +167,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) */ current_regs[REG_PC] = (uint32_t)up_sigdeliver; +#ifdef CONFIG_ARMV7M_USEBASEPRI + current_regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; +#else current_regs[REG_PRIMASK] = 1; +#endif current_regs[REG_XPSR] = ARMV7M_XPSR_T; /* And make sure that the saved context in the TCB @@ -189,7 +197,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) tcb->xcp.sigdeliver = sigdeliver; tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC]; +#ifdef CONFIG_ARMV7M_USEBASEPRI + tcb->xcp.saved_basepri = tcb->xcp.regs[REG_BASEPRI]; +#else tcb->xcp.saved_primask = tcb->xcp.regs[REG_PRIMASK]; +#endif tcb->xcp.saved_xpsr = tcb->xcp.regs[REG_XPSR]; /* Then set up to vector to the trampoline with interrupts @@ -197,7 +209,11 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver) */ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; +#ifdef CONFIG_ARMV7M_USEBASEPRI + tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY; +#else tcb->xcp.regs[REG_PRIMASK] = 1; +#endif tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T; } diff --git a/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c index 38673c41d..654214b39 100644 --- a/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/nuttx/arch/arm/src/armv7-m/up_sigdeliver.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-m/up_sigdeliver.c * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -102,7 +102,11 @@ void up_sigdeliver(void) up_copystate(regs, rtcb->xcp.regs); regs[REG_PC] = rtcb->xcp.saved_pc; +#ifdef CONFIG_ARMV7M_USEBASEPRI + regs[REG_BASEPRI] = rtcb->xcp.saved_basepri; +#else regs[REG_PRIMASK] = rtcb->xcp.saved_primask; +#endif regs[REG_XPSR] = rtcb->xcp.saved_xpsr; /* Get a local copy of the sigdeliver function pointer. We do this so that @@ -115,7 +119,11 @@ void up_sigdeliver(void) /* Then restore the task interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + irqrestore((uint8_t)regs[REG_BASEPRI]); +#else irqrestore((uint16_t)regs[REG_PRIMASK]); +#endif /* Deliver the signals */ diff --git a/nuttx/arch/arm/src/armv7-m/vfork.S b/nuttx/arch/arm/src/armv7-m/vfork.S new file mode 100644 index 000000000..f36ff23aa --- /dev/null +++ b/nuttx/arch/arm/src/armv7-m/vfork.S @@ -0,0 +1,142 @@ +/************************************************************************************ + * arch/arm/src/armv7-m/vfork.S + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "up_vfork.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Global Symbols + ************************************************************************************/ + + .syntax unified + .thumb + .file "vfork.S" + .globl up_vfork + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the behavior is + * undefined if the process created by vfork() either modifies any data other than + * a variable of type pid_t used to store the return value from vfork(), or returns + * from the function in which vfork() was called, or calls any other function before + * successfully calling _exit() or one of the exec family of functions. + * + * This thin layer implements vfork by simply calling up_vfork() with the vfork() + * context as an argument. The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * Input Paremeters: + * None + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and returns + * the process ID of the child process to the parent process. Otherwise, -1 is + * returned to the parent, no child process is created, and errno is set to + * indicate the error. + * + ************************************************************************************/ + + .thumb_func + .globl vfork + .type vfork, function +vfork: + /* Create a stack frame */ + + mov r0, sp /* Save the value of the stack on entry */ + sub sp, sp, #VFORK_SIZEOF /* Allocate the structure on the stack */ + + /* CPU registers */ + /* Save the volatile registers */ + + str r4, [sp, #VFORK_R4_OFFSET] + str r5, [sp, #VFORK_R5_OFFSET] + str r6, [sp, #VFORK_R6_OFFSET] + str r7, [sp, #VFORK_R7_OFFSET] + str r8, [sp, #VFORK_R8_OFFSET] + str r9, [sp, #VFORK_R9_OFFSET] + str r10, [sp, #VFORK_R10_OFFSET] + + /* Save the frame pointer, stack pointer, and return address */ + + str fp, [sp, #VFORK_FP_OFFSET] + str r0, [sp, #VFORK_SP_OFFSET] + str lr, [sp, #VFORK_LR_OFFSET] + + /* Floating point registers (not yet) */ + + /* Then, call up_vfork(), passing it a pointer to the stack structure */ + + mov r0, sp + bl up_vfork + + /* Release the stack data and return the value returned by up_vfork */ + + ldr lr, [sp, #VFORK_LR_OFFSET] + add sp, sp, #VFORK_SIZEOF + bx lr + .size vfork, .-vfork + .end + diff --git a/nuttx/arch/arm/src/common/up_internal.h b/nuttx/arch/arm/src/common/up_internal.h index 0d3c5b1f2..55071345f 100644 --- a/nuttx/arch/arm/src/common/up_internal.h +++ b/nuttx/arch/arm/src/common/up_internal.h @@ -188,7 +188,7 @@ extern uint32_t _ebss; /* End+1 of .bss */ * will create a function named foo that will execute from RAM. */ -#ifdef CONFIG_BOOT_RAMFUNCS +#ifdef CONFIG_ARCH_RAMFUNCS # define __ramfunc__ __attribute__ ((section(".ramfunc"))) @@ -204,7 +204,7 @@ extern const uint32_t _framfuncs; /* Copy source address in FLASH */ extern uint32_t _sramfuncs; /* Copy destination start address in RAM */ extern uint32_t _eramfuncs; /* Copy destination start address in RAM */ -#endif /* CONFIG_BOOT_RAMFUNCS */ +#endif /* CONFIG_ARCH_RAMFUNCS */ #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/nuttx/arch/arm/src/common/up_vfork.c b/nuttx/arch/arm/src/common/up_vfork.c new file mode 100644 index 000000000..3b653e317 --- /dev/null +++ b/nuttx/arch/arm/src/common/up_vfork.c @@ -0,0 +1,233 @@ +/**************************************************************************** + * arch/arm/src/common/up_vfork.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <errno.h> +#include <debug.h> + +#include <nuttx/sched.h> +#include <nuttx/arch.h> +#include <arch/irq.h> + +#include "up_vfork.h" +#include "os_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ARM requires at least a 4-byte stack alignment. For use with EABI and + * floating point, the stack must be aligned to 8-byte addresses. + */ + +#ifndef CONFIG_STACK_ALIGNMENT + +/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you + * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly! + */ + +# ifdef __ARM_EABI__ +# define CONFIG_STACK_ALIGNMENT 8 +# else +# define CONFIG_STACK_ALIGNMENT 4 +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * task_vforkabort() may be called if an error occurs between steps 3 and 6. + * + * Input Paremeters: + * context - Caller context information saved by vfork() + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and + * returns the process ID of the child process to the parent process. + * Otherwise, -1 is returned to the parent, no child process is created, + * and errno is set to indicate the error. + * + ****************************************************************************/ + +pid_t up_vfork(const struct vfork_s *context) +{ + _TCB *parent = (FAR _TCB *)g_readytorun.head; + _TCB *child; + size_t stacksize; + uint32_t newsp; + uint32_t newfp; + uint32_t stackutil; + int ret; + + svdbg("r4:%08x r5:%08x r6:%08x r7:%08x\n", + context->r4, context->r5, context->r6, context->r7); + svdbg("r8:%08x r9:%08x r10:%08x\n", + context->r8, context->r9, context->r10); + svdbg("fp:%08x sp:%08x lr:%08x\n", + context->fp, context->sp, context->lr); + + /* Allocate and initialize a TCB for the child task. */ + + child = task_vforksetup((start_t)(context->lr & ~1)); + if (!child) + { + sdbg("task_vforksetup failed\n"); + return (pid_t)ERROR; + } + + svdbg("Parent=%p Child=%p\n", parent, child); + + /* Get the size of the parent task's stack. Due to alignment operations, + * the adjusted stack size may be smaller than the stack size originally + * requrested. + */ + + stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1; + + /* Allocate the stack for the TCB */ + + ret = up_create_stack(child, stacksize); + if (ret != OK) + { + sdbg("up_create_stack failed: %d\n", ret); + task_vforkabort(child, -ret); + return (pid_t)ERROR; + } + + /* How much of the parent's stack was utilized? The ARM uses + * a push-down stack so that the current stack pointer should + * be lower than the initial, adjusted stack pointer. The + * stack usage should be the difference between those two. + */ + + DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); + stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; + + svdbg("stacksize:%d stackutil:%d\n", stacksize, stackutil); + + /* Make some feeble effort to perserve the stack contents. This is + * feeble because the stack surely contains invalid pointers and other + * content that will not work in the child context. However, if the + * user follows all of the caveats of vfor() usage, even this feeble + * effort is overkill. + */ + + newsp = (uint32_t)child->adj_stack_ptr - stackutil; + memcpy((void *)newsp, (const void *)context->sp, stackutil); + + /* Was there a frame pointer in place before? */ + + if (context->fp <= (uint32_t)parent->adj_stack_ptr && + context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize) + { + uint32_t frameutil = (uint32_t)parent->adj_stack_ptr - context->fp; + newfp = (uint32_t)child->adj_stack_ptr - frameutil; + } + else + { + newfp = context->fp; + } + + svdbg("Old stack base:%08x SP:%08x FP:%08x\n", + parent->adj_stack_ptr, context->sp, context->fp); + svdbg("New stack base:%08x SP:%08x FP:%08x\n", + child->adj_stack_ptr, newsp, newfp); + + /* Update the stack pointer, frame pointer, and volatile registers. When + * the child TCB was initialized, all of the values were set to zero. + * up_initial_state() altered a few values, but the return value in R0 + * should be cleared to zero, providing the indication to the newly started + * child thread. + */ + + child->xcp.regs[REG_R4] = context->r4; /* Volatile register r4 */ + child->xcp.regs[REG_R5] = context->r5; /* Volatile register r5 */ + child->xcp.regs[REG_R6] = context->r6; /* Volatile register r6 */ + child->xcp.regs[REG_R7] = context->r7; /* Volatile register r7 */ + child->xcp.regs[REG_R8] = context->r8; /* Volatile register r8 */ + child->xcp.regs[REG_R9] = context->r9; /* Volatile register r9 */ + child->xcp.regs[REG_R10] = context->r10; /* Volatile register r10 */ + child->xcp.regs[REG_FP] = newfp; /* Frame pointer */ + child->xcp.regs[REG_SP] = newsp; /* Stack pointer */ + + /* And, finally, start the child task. On a failure, task_vforkstart() + * will discard the TCB by calling task_vforkabort(). + */ + + return task_vforkstart(child); +} diff --git a/nuttx/arch/arm/src/common/up_vfork.h b/nuttx/arch/arm/src/common/up_vfork.h new file mode 100644 index 000000000..97edf9aaa --- /dev/null +++ b/nuttx/arch/arm/src/common/up_vfork.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/arm/src/common/up_vfork.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARM_VFORK_H +#define __ARCH_ARM_SRC_ARM_VFORK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define VFORK_R4_OFFSET (0*4) /* Volatile register r4 */ +#define VFORK_R5_OFFSET (1*4) /* Volatile register r5 */ +#define VFORK_R6_OFFSET (2*4) /* Volatile register r6 */ +#define VFORK_R7_OFFSET (3*4) /* Volatile register r7 */ +#define VFORK_R8_OFFSET (4*4) /* Volatile register r8 */ +#define VFORK_R9_OFFSET (5*4) /* Volatile register r9 */ +#define VFORK_R10_OFFSET (6*4) /* Volatile register r10 */ + +#define VFORK_FP_OFFSET (7*4) /* Frame pointer */ +#define VFORK_SP_OFFSET (8*4) /* Stack pointer*/ +#define VFORK_LR_OFFSET (9*4) /* Return address*/ + +#define VFORK_SIZEOF (10*4) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +struct vfork_s +{ + /* CPU registers */ + + uint32_t r4; /* Volatile register r4 */ + uint32_t r5; /* Volatile register r5 */ + uint32_t r6; /* Volatile register r6 */ + uint32_t r7; /* Volatile register r7 */ + uint32_t r8; /* Volatile register r8 */ + uint32_t r9; /* Volatile register r9 */ + uint32_t r10; /* Volatile register r10 */ + + uint32_t fp; /* Frame pointer */ + uint32_t sp; /* Stack pointer*/ + uint32_t lr; /* Return address*/ + + /* Floating point registers (not yet) */ +}; +#endif + +#endif /* __ARCH_ARM_SRC_ARM_VFORK_H */ diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 99dde3209..41724be2d 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -457,32 +457,38 @@ config STM32_USART1 bool "USART1" default n select ARCH_HAVE_USART1 + select STM32_USART config STM32_USART2 bool "USART2" default n select ARCH_HAVE_USART2 + select STM32_USART config STM32_USART3 bool "USART3" default n select ARCH_HAVE_USART3 + select STM32_USART config STM32_UART4 bool "UART4" default n select ARCH_HAVE_UART4 + select STM32_USART config STM32_UART5 bool "UART5" default n select ARCH_HAVE_UART5 + select STM32_USART config STM32_USART6 bool "USART6" default n depends on STM32_STM32F20XX || STM32_STM32F40XX select ARCH_HAVE_USART6 + select STM32_USART config STM32_USB bool "USB Device" @@ -1804,8 +1810,11 @@ config STM32_TIM14_DAC2 endchoice +config STM32_USART + bool + menu "U[S]ART Configuration" - depends on STM32_USART1 || STM32_USART2 || STM32_USART3 || STM32_USART4 || STM32_USART5 || STM32_USART6 + depends on STM32_USART config USART1_RS485 bool "RS-485 on USART1" @@ -1968,6 +1977,14 @@ config SERIAL_TERMIOS endmenu +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + default n + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + menu "SPI Configuration" depends on STM32_SPI diff --git a/nuttx/arch/arm/src/stm32/Make.defs b/nuttx/arch/arm/src/stm32/Make.defs index baa751c7d..940ff6517 100644 --- a/nuttx/arch/arm/src/stm32/Make.defs +++ b/nuttx/arch/arm/src/stm32/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/arm/src/stm32/Make.defs # -# Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt <gnutt@nuttx.org> # # Redistribution and use in source and binary forms, with or without @@ -39,15 +39,16 @@ else HEAD_ASRC = stm32_vectors.S endif -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S \ + vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c \ up_createstack.c up_mdelay.c up_udelay.c up_exit.c \ up_initialize.c up_initialstate.c up_interruptcontext.c \ up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \ up_releasepending.c up_releasestack.c up_reprioritizertr.c \ up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \ - up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \ - up_stackcheck.c + up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c \ + up_svcall.c up_stackcheck.c up_vfork.c ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) CMN_ASRCS += up_exception.S diff --git a/nuttx/arch/arm/src/stm32/chip.h b/nuttx/arch/arm/src/stm32/chip.h index 3fac597ef..41a87feae 100644 --- a/nuttx/arch/arm/src/stm32/chip.h +++ b/nuttx/arch/arm/src/stm32/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/chip.h * - * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/arch/arm/src/stm32/stm32.h b/nuttx/arch/arm/src/stm32/stm32.h index 44a23aece..95fd19779 100644 --- a/nuttx/arch/arm/src/stm32/stm32.h +++ b/nuttx/arch/arm/src/stm32/stm32.h @@ -68,12 +68,6 @@ # undef CONFIG_DEBUG_QENCODER #endif -/* NVIC priority levels *************************************************************/ - -#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ - /* Peripherals **********************************************************************/ #include "chip.h" diff --git a/nuttx/arch/arm/src/stm32/stm32_flash.c b/nuttx/arch/arm/src/stm32/stm32_flash.c index 83fcc6172..20b0cfe10 100644 --- a/nuttx/arch/arm/src/stm32/stm32_flash.c +++ b/nuttx/arch/arm/src/stm32/stm32_flash.c @@ -35,7 +35,7 @@ /* Provides standard flash access functions, to be used by the flash mtd driver. * The interface is defined in the include/nuttx/progmem.h - * + * * Requirements during write/erase operations on FLASH: * - HSI must be ON. * - Low Power Modes are not permitted during write/erase @@ -80,7 +80,7 @@ void stm32_flash_unlock(void) if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } @@ -112,6 +112,11 @@ uint16_t up_progmem_pagesize(uint16_t page) int up_progmem_getpage(uint32_t addr) { + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; @@ -131,14 +136,14 @@ int up_progmem_erasepage(uint16_t page) } /* Get flash ready and begin erasing single page */ - + if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION)) { return -EPERM; } - + stm32_flash_unlock(); - + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PER); putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR); modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); @@ -146,10 +151,10 @@ int up_progmem_erasepage(uint16_t page) while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste(); modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0); - + /* Verify */ - - for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; + + for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; count; count-=4, addr += 4) { if (getreg32(addr) != 0xffffffff) @@ -173,8 +178,8 @@ int up_progmem_ispageerased(uint16_t page) } /* Verify */ - - for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; + + for (addr = page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE, count = STM32_FLASH_PAGESIZE; count; count--, addr++) { if (getreg8(addr) != 0xff) @@ -200,6 +205,11 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count) /* Check for valid address range */ + if (addr >= STM32_FLASH_BASE) + { + addr -= STM32_FLASH_BASE; + } + if ((addr+count) >= STM32_FLASH_SIZE) { return -EFAULT; @@ -213,10 +223,10 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count) } stm32_flash_unlock(); - + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); - - for (addr += STM32_FLASH_BASE; count; count--, hword++, addr+=2) + + for (addr += STM32_FLASH_BASE; count; count-=2, hword++, addr+=2) { /* Write half-word and wait to complete */ @@ -237,7 +247,6 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count) modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); return -EIO; } - } modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); diff --git a/nuttx/arch/arm/src/stm32/stm32_irq.c b/nuttx/arch/arm/src/stm32/stm32_irq.c index 36a5cf5fa..a952c2486 100644 --- a/nuttx/arch/arm/src/stm32/stm32_irq.c +++ b/nuttx/arch/arm/src/stm32/stm32_irq.c @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_irq.c * arch/arm/src/chip/stm32_irq.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -195,6 +195,29 @@ static int stm32_reserved(int irq, FAR void *context) #endif /**************************************************************************** + * Name: stm32_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void stm32_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** * Name: stm32_irqinfo * * Description: @@ -335,6 +358,9 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_IRQPRIO /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif +#ifdef CONFIG_ARMV7M_USEBASEPRI + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -365,8 +391,7 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ - setbasepri(NVIC_SYSH_PRIORITY_MAX); - irqrestore(0); + irqenable(); #endif } @@ -451,15 +476,28 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#ifdef CONFIG_ARMV7M_USEBASEPRI + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + priority >= NVIC_SYSH_DISABLE_PRIORITY && + priority <= NVIC_SYSH_PRIORITY_MIN); +#else + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); +#endif if (irq < STM32_IRQ_INTERRUPTS) { - irq -= 4; + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; } else { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + irq -= STM32_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/nuttx/arch/arm/src/stm32/stm32_serial.c b/nuttx/arch/arm/src/stm32/stm32_serial.c index aa46a8987..6aaecb2d9 100644 --- a/nuttx/arch/arm/src/stm32/stm32_serial.c +++ b/nuttx/arch/arm/src/stm32/stm32_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_serial.c * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -79,22 +79,22 @@ #if SERIAL_HAVE_DMA -/* Verify that DMA has been enabled an the DMA channel has been defined. - * NOTE: These assignments may only be true for the F4. +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +/* Verify that DMA has been enabled and the DMA channel has been defined. */ -# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) -# ifndef CONFIG_STM32_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 +# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 +# endif # endif -# endif -# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ +# if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# ifndef CONFIG_STM32_DMA1 -# error STM32 USART2/3/4/5 receive DMA requires CONFIG_STM32_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5 receive DMA requires CONFIG_STM32_DMA1 +# endif # endif -# endif /* Currently RS-485 support cannot be enabled when RXDMA is in use due to lack * of testing - RS-485 support was developed on STM32F1x @@ -114,28 +114,52 @@ * the following in the board.h file. */ -# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) -# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" -# endif +# if defined(CONFIG_USART1_RXDMA) && !defined(DMAMAP_USART1_RX) +# error "USART1 DMA channel not defined (DMAMAP_USART1_RX)" +# endif -# if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX) -# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" -# endif +# if defined(CONFIG_USART2_RXDMA) && !defined(DMAMAP_USART2_RX) +# error "USART2 DMA channel not defined (DMAMAP_USART2_RX)" +# endif -# if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX) -# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" -# endif +# if defined(CONFIG_USART3_RXDMA) && !defined(DMAMAP_USART3_RX) +# error "USART3 DMA channel not defined (DMAMAP_USART3_RX)" +# endif -# if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX) -# error "UART4 DMA channel not defined (DMAMAP_UART4_RX)" -# endif +# if defined(CONFIG_UART4_RXDMA) && !defined(DMAMAP_UART4_RX) +# error "UART4 DMA channel not defined (DMAMAP_UART4_RX)" +# endif -# if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX) -# error "UART5 DMA channel not defined (DMAMAP_UART5_RX)" -# endif +# if defined(CONFIG_UART5_RXDMA) && !defined(DMAMAP_UART5_RX) +# error "UART5 DMA channel not defined (DMAMAP_UART5_RX)" +# endif + +# if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX) +# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" +# endif + +# elif defined(CONFIG_STM32_STM32F10XX) + +# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \ + defined(CONFIG_USART3_RXDMA) +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART1/2/3 receive DMA requires CONFIG_STM32_DMA1 +# endif +# endif + +# if defined(CONFIG_UART4_RXDMA) +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART4 receive DMA requires CONFIG_STM32_DMA2 +# endif +# endif + +/* There are no optional DMA channel assignments for the F1 */ + +# define DMAMAP_USART1_RX DMACHAN_USART1_RX +# define DMAMAP_USART2_RX DMACHAN_USART2_RX +# define DMAMAP_USART3_RX DMACHAN_USART3_RX +# define DMAMAP_UART4_RX DMACHAN_USART4_RX -# if defined(CONFIG_USART6_RXDMA) && !defined(DMAMAP_USART6_RX) -# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)" # endif /* The DMA buffer size when using RX DMA to emulate a FIFO. @@ -169,6 +193,27 @@ # error "Unknown STM32 DMA" # endif +/* DMA control word */ + +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_SCR_DIR_P2M | \ + DMA_SCR_CIRC | \ + DMA_SCR_MINC | \ + DMA_SCR_PSIZE_8BITS | \ + DMA_SCR_MSIZE_8BITS | \ + CONFIG_USART_DMAPRIO | \ + DMA_SCR_PBURST_SINGLE | \ + DMA_SCR_MBURST_SINGLE) +# else +# define SERIAL_DMA_CONTROL_WORD \ + (DMA_CCR_CIRC | \ + DMA_CCR_MINC | \ + DMA_CCR_PSIZE_8BITS | \ + DMA_CCR_MSIZE_8BITS | \ + CONFIG_USART_DMAPRIO) +# endif + #endif /* Power management definitions */ @@ -1115,14 +1160,7 @@ static int up_dma_setup(struct uart_dev_s *dev) priv->usartbase + STM32_USART_DR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, - DMA_SCR_DIR_P2M | - DMA_SCR_CIRC | - DMA_SCR_MINC | - DMA_SCR_PSIZE_8BITS | - DMA_SCR_MSIZE_8BITS | - CONFIG_USART_DMAPRIO | - DMA_SCR_PBURST_SINGLE | - DMA_SCR_MBURST_SINGLE); + SERIAL_DMA_CONTROL_WORD); /* Reset our DMA shadow pointer to match the address just * programmed above. @@ -1401,6 +1439,31 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) } break; +#ifdef CONFIG_STM32_USART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + /* Change the TX port to be open-drain/push-pull and enable/disable + * half-duplex mode. + */ + + uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET); + + if (arg == SER_SINGLEWIRE_ENABLED) + { + stm32_configgpio(priv->tx_gpio | GPIO_OPENDRAIN); + cr |= USART_CR3_HDSEL; + } + else + { + stm32_configgpio(priv->tx_gpio | GPIO_PUSHPULL); + cr &= ~USART_CR3_HDSEL; + } + + up_serialout(priv, STM32_USART_CR3_OFFSET, cr); + } + break; +#endif + #ifdef CONFIG_SERIAL_TERMIOS case TCGETS: { diff --git a/nuttx/arch/arm/src/stm32/stm32_uart.h b/nuttx/arch/arm/src/stm32/stm32_uart.h index 8ff6a9975..a26ea2009 100644 --- a/nuttx/arch/arm/src/stm32/stm32_uart.h +++ b/nuttx/arch/arm/src/stm32/stm32_uart.h @@ -140,12 +140,9 @@ # undef HAVE_CONSOLE #endif -/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration. - * Furthermore, DMA support is currently only implemented for the F4 (but could be - * extended to the F1 and F2 with a little effort in the DMA code. - */ +/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration */ -#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) || !defined(CONFIG_STM32_STM32F40XX) +#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) # undef CONFIG_USART1_RXDMA # undef CONFIG_USART2_RXDMA # undef CONFIG_USART3_RXDMA diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S index ab4dadb77..c9b62d762 100644 --- a/nuttx/arch/arm/src/stm32/stm32_vectors.S +++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S @@ -2,7 +2,7 @@ * arch/arm/src/stm32/stm32_vectors.S * arch/arm/src/chip/stm32_vectors.S * - * Copyright (C) 2009-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without @@ -235,7 +235,11 @@ stm32_common: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + mrs r3, basepri /* R3=Current BASEPRI setting */ +#else mrs r3, primask /* R3=Current PRIMASK setting */ +#endif #ifdef CONFIG_ARCH_FPU /* Skip over the block of memory reserved for floating pointer register save. @@ -248,8 +252,8 @@ stm32_common: #endif /* Save the the remaining registers on the stack after the registers pushed - * by the exception handling logic. r2=SP and r3=primask, r4-r11,r14=register - * values. + * by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11, + * r14=register values. */ #ifdef CONFIG_NUTTX_KERNEL @@ -349,7 +353,7 @@ stm32_common: * Here: * r1 = Address on the target thread's stack position at the start of * the registers saved by hardware - * r3 = primask + * r3 = primask or basepri * r4-r11 = restored register values */ 2: @@ -375,7 +379,12 @@ stm32_common: /* Restore the interrupt state */ +#ifdef CONFIG_ARMV7M_USEBASEPRI + msr basepri, r3 /* Restore interrupts priority masking*/ + cpsie i /* Re-enable interrupts */ +#else msr primask, r3 /* Restore interrupts */ +#endif /* Always return with R14 containing the special value that will: (1) * return to thread mode, and (2) continue to use the MSP diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c index 89b279bea..13324b8ac 100644 --- a/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_dma.c @@ -303,13 +303,13 @@ static int stm32_dmainterrupt(int irq, void *context) } dmach = &g_dma[chndx]; - /* Get the interrupt status (for this channel only) -- not currently used */ + /* Get the interrupt status (for this channel only) */ isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); - /* Disable the DMA channel */ + /* Clear the interrupts we are handling */ - stm32_dmachandisable(dmach); + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); /* Invoke the callback */ @@ -528,14 +528,34 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; - /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is - * set and an interrupt is generated if the Half-Transfer Interrupt Enable - * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag - * (TCIF) is set and an interrupt is generated if the Transfer Complete - * Interrupt Enable bit (TCIE) is set. + /* In normal mode, interrupt at either half or full completion. In circular mode, + * always interrupt on buffer wrap, and optionally interrupt at the halfway point. */ - ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE)); + if ((ccr & DMA_CCR_CIRC) == 0) + { + /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is + * set and an interrupt is generated if the Half-Transfer Interrupt Enable + * bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag + * (TCIF) is set and an interrupt is generated if the Transfer Complete + * Interrupt Enable bit (TCIE) is set. + */ + + ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE)); + + } + else + { + /* In nonstop mode, when the transfer completes it immediately resets + * and starts again. The transfer-complete interrupt is thus always + * enabled, and the half-complete interrupt can be used in circular + * mode to determine when the buffer is half-full, or in double-buffered + * mode to determine when one of the two buffers is full. + */ + + ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; + } + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); } @@ -559,6 +579,24 @@ void stm32_dmastop(DMA_HANDLE handle) } /**************************************************************************** + * Name: stm32_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by stm32_dmachannel() + * + ****************************************************************************/ + +size_t stm32_dmaresidual(DMA_HANDLE handle) +{ + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); +} + +/**************************************************************************** * Name: stm32_dmasample * * Description: diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c index dcbbf1856..40fce8cb5 100644 --- a/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -94,7 +94,6 @@ struct stm32_dma_s uint8_t irq; /* DMA stream IRQ number */ uint8_t shift; /* ISR/IFCR bit shift value */ uint8_t channel; /* DMA channel number (0-7) */ - bool nonstop; /* Stream is configured in a non-stopping mode. */ sem_t sem; /* Used to wait for DMA channel to become available */ uint32_t base; /* DMA register channel base address */ dma_callback_t callback; /* Callback invoked when the DMA completes */ @@ -728,7 +727,6 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DMA_SCR_DBM|DMA_SCR_CIRC| DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK); regval |= scr; - dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0; dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval); } @@ -764,7 +762,12 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET); scr |= DMA_SCR_EN; - if (!dmast->nonstop) + /* In normal mode, interrupt at either half or full completion. In circular + * and double-buffered modes, always interrupt on buffer wrap, and optionally + * interrupt at the halfway point. + */ + + if ((scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) == 0) { /* Once half of the bytes are transferred, the half-transfer flag (HTIF) is * set and an interrupt is generated if the Half-Transfer Interrupt Enable @@ -777,7 +780,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool } else { - /* In nonstop mode, when the transfer completes it immediately resets + /* In non-stop modes, when the transfer completes it immediately resets * and starts again. The transfer-complete interrupt is thus always * enabled, and the half-complete interrupt can be used in circular * mode to determine when the buffer is half-full, or in double-buffered |