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author | Gregory Nutt <gnutt@nuttx.org> | 2013-09-01 11:29:51 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-09-01 11:29:51 -0600 |
commit | 0650ae513bff63d00af8728a5265890cfbf95d37 (patch) | |
tree | 854ddc6a100a68376d31d533d4b5eaecbdd94dd9 | |
parent | 7a57dd91fe66f1c4b42f12dc531db62b4c1bf383 (diff) | |
download | px4-nuttx-0650ae513bff63d00af8728a5265890cfbf95d37.tar.gz px4-nuttx-0650ae513bff63d00af8728a5265890cfbf95d37.tar.bz2 px4-nuttx-0650ae513bff63d00af8728a5265890cfbf95d37.zip |
SAMA5 UDPHS: Support USPHS clock configuration
-rw-r--r-- | nuttx/ChangeLog | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_clockconfig.c | 14 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_periphclks.h | 4 | ||||
-rw-r--r-- | nuttx/configs/sama5d3x-ek/include/board_384mhz.h | 9 | ||||
-rw-r--r-- | nuttx/configs/sama5d3x-ek/include/board_396mhz.h | 5 |
5 files changed, 25 insertions, 9 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index c15340ec8..804091845 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -5485,4 +5485,6 @@ function. From Alan Carvalho de Assis (2013-8-31). * drivers/usbdev/cdcacm_desc.c: Fixed some compilation errors that only occur when dual speed support is enabled (2013-9-1). + * arch/arm/src/sama5/sam_clockconfig.c and configs/sama5d3x-ek/include/board_*mhz.h: + Add logic to support UDPHS clocking (2013-9-13). diff --git a/nuttx/arch/arm/src/sama5/sam_clockconfig.c b/nuttx/arch/arm/src/sama5/sam_clockconfig.c index 1c82e9e3e..a8c0613ef 100644 --- a/nuttx/arch/arm/src/sama5/sam_clockconfig.c +++ b/nuttx/arch/arm/src/sama5/sam_clockconfig.c @@ -330,7 +330,14 @@ static inline void sam_selectplla(void) static inline void sam_usbclockconfig(void) { -#if defined(CONFIG_SAMA5_EHCI) +#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \ + defined(CONFIG_SAMA5_UDPHS) + + /* We can either get the clock from the UPLL or from PLLA. In this latter + * case, however, the PLLACK frequency must be a multiple of 48MHz. + */ + +#if defined(BOARD_USE_UPLL) uint32_t regval; /* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the @@ -395,7 +402,7 @@ static inline void sam_usbclockconfig(void) regval |= PMC_USB_USBDIV(9); putreg32(regval, SAM_PMC_USB); -#elif defined(CONFIG_SAMA5_OHCI) +#else /* BOARD_USE_UPLL */ /* For OHCI Full-speed operations only, the user has to perform the * following: * @@ -415,7 +422,8 @@ static inline void sam_usbclockconfig(void) putreg32(BOARD_OHCI_INPUT | BOARD_OHCI_DIVIDER << PMC_USB_USBDIV_SHIFT, SAM_PMC_USB); -#endif +#endif /* BOARD_USE_UPLL */ +#endif /* CONFIG_SAMA5_EHCI ||CONFIG_SAMA5_OHCI) || CONFIG_SAMA5_UDPHS */ } /**************************************************************************** diff --git a/nuttx/arch/arm/src/sama5/sam_periphclks.h b/nuttx/arch/arm/src/sama5/sam_periphclks.h index a89d0f95f..2d188378b 100644 --- a/nuttx/arch/arm/src/sama5/sam_periphclks.h +++ b/nuttx/arch/arm/src/sama5/sam_periphclks.h @@ -52,8 +52,8 @@ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) #define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) -#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0) -#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1) +#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0) +#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1) #define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0) #define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0) diff --git a/nuttx/configs/sama5d3x-ek/include/board_384mhz.h b/nuttx/configs/sama5d3x-ek/include/board_384mhz.h index 8f94da2ed..e52e76e24 100644 --- a/nuttx/configs/sama5d3x-ek/include/board_384mhz.h +++ b/nuttx/configs/sama5d3x-ek/include/board_384mhz.h @@ -100,7 +100,9 @@ #define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2 #define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3 -#ifdef CONFIG_SAMA5_OHCI +#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \ + defined(CONFIG_SAMA5_UDPHS) + /* For OHCI Full-speed operations, the user has to perform the following: * * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER @@ -132,8 +134,9 @@ * frame rate. I cannot explain the factor of 2 difference. */ -# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA -# define BOARD_OHCI_DIVIDER (7) +# undef BOARD_USE_UPLL /* Use PLLA as source clock */ +# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA /* Input is PLLACK */ +# define BOARD_OHCI_DIVIDER (7) /* Divided by 8 */ #endif /* Resulting frequencies */ diff --git a/nuttx/configs/sama5d3x-ek/include/board_396mhz.h b/nuttx/configs/sama5d3x-ek/include/board_396mhz.h index ac3ae724e..16dfb2e10 100644 --- a/nuttx/configs/sama5d3x-ek/include/board_396mhz.h +++ b/nuttx/configs/sama5d3x-ek/include/board_396mhz.h @@ -106,7 +106,9 @@ #define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */ #define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */ -#ifdef CONFIG_SAMA5_EHCI +#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \ + defined(CONFIG_SAMA5_UDPHS) + /* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either @@ -132,6 +134,7 @@ * driver is initialized. */ +# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ # define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ # define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ #endif |