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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-08-22 01:35:53 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-08-22 01:35:53 +0000 |
commit | 93362e94215a997b3dd1323cba42ea40d3483575 (patch) | |
tree | d193da2aa4b48fc6027001cbb1711640c6ff980e | |
parent | 44f7e698d820f2f73c43e53422a431c84031a5fd (diff) | |
download | px4-nuttx-93362e94215a997b3dd1323cba42ea40d3483575.tar.gz px4-nuttx-93362e94215a997b3dd1323cba42ea40d3483575.tar.bz2 px4-nuttx-93362e94215a997b3dd1323cba42ea40d3483575.zip |
simplification
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2878 42af7a65-404d-4744-a932-0658087f49c3
-rw-r--r-- | nuttx/arch/arm/src/arm/pg_macros.h | 61 | ||||
-rw-r--r-- | nuttx/arch/arm/src/arm/up_head.S | 24 |
2 files changed, 24 insertions, 61 deletions
diff --git a/nuttx/arch/arm/src/arm/pg_macros.h b/nuttx/arch/arm/src/arm/pg_macros.h index 73bbb93b3..8119ef941 100644 --- a/nuttx/arch/arm/src/arm/pg_macros.h +++ b/nuttx/arch/arm/src/arm/pg_macros.h @@ -131,6 +131,8 @@ * table. */ +#define PG_L1_LOCKED_PADDR (PGTABLE_BASE_PADDR + ((PG_LOCKED_VBASE >> 20) << 2)) +#define PG_L1_LOCKED_VADDR (PGTABLE_BASE_VADDR + ((PG_LOCKED_VBASE >> 20) << 2)) #define PG_L2_LOCKED_PADDR PG_L2_BASE_PADDR #define PG_L2_LOCKED_VADDR PG_L2_BASE_VADDR #define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED) @@ -138,19 +140,25 @@ /* We position the paged region PTEs immediately after the locked * region PTEs. */ - + +#define PG_L1_PAGED_PADDR (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2)) +#define PG_L1_PAGED_VADDR (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2)) #define PG_L2_PAGED_PADDR (PG_L2_BASE_PADDR + PG_L2_LOCKED_SIZE) #define PG_L2_PAGED_VADDR (PG_L2_BASE_VADDR + PG_L2_LOCKED_SIZE) #define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NPPAGED) /* This describes the overall text region */ +#define PG_L1_TEXT_PADDR PG_L1_LOCKED_PADDR +#define PG_L1_TEXT_VADDR PG_L1_LOCKED_VADDR #define PG_L2_TEXT_PADDR PG_L2_LOCKED_PADDR #define PG_L2_TEXT_VADDR PG_L2_LOCKED_VADDR #define PG_L2_TEXT_SIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_SIZE) /* We position the data section PTEs just after the text region PTE's */ +#define PG_L1_DATA_PADDR (PGTABLE_BASE_PADDR + ((PG_DATA_VBASE >> 20) << 2)) +#define PG_L1_DATA_VADDR (PGTABLE_BASE_VADDR + ((PG_DATA_VBASE >> 20) << 2)) #define PG_L2_DATA_PADDR (PG_L2_BASE_PADDR + PG_L2_TEXT_SIZE) #define PG_L2_DATA_VADDR (PG_L2_BASE_VADDR + PG_L2_TEXT_SIZE) #define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES) @@ -161,6 +169,8 @@ */ #define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT) +#define PG_L1_PGTABLE_PADDR (PGTABLE_BASE_PADDR + ((PGTABLE_BASE_VADDR >> 20) << 2)) +#define PG_L1_PGTABLE_VADDR (PGTABLE_BASE_VADDR + ((PGTABLE_BASE_VADDR >> 20) << 2)) #define PG_L2_PGTABLE_PADDR (PG_L2_DATA_PADDR + PG_L2_DATA_SIZE) #define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE) #define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES) @@ -368,12 +378,10 @@ * macro is used when CONFIG_PAGING is enable. This case, it is used as * follows: * - * ldr r0, =PGTABLE_BASE_PADDR <-- Address in L1 table - * ldr r1, =PG_LOCKED_VBASE <-- Virtual address of region - * pg_l1addr r0, r1, r0 - * ldr r1, =PG_LOCKED_PBASE <-- Physical address of region - * ldr r1, =(CONFIG_PAGING_NLOCKED+CONFIG_PAGING_NVPAGED) <-- number of pages - * ldr r3, =MMU_FLAGS <-- L1 MMU flags + * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table + * ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table + * ldr r2, =PG_PGTABLE_NPAGES <-- Number of pages + * ldr r3, =MMU_L1_PGTABFLAGS <-- L1 MMU flags * pg_l1span r0, r1, r2, r3, r4 * * Inputs (unmodified unless noted): @@ -431,45 +439,6 @@ bgt 1b .endm -/**************************************************************************** - * Name: pg_l1addr - * - * Description: - * Given the start of an L1 table and a virtual address, return the offset - * address into the L1 table for that address. - * - * ldr r0, =PGTABLE_BASE_PADDR - * ldr r1, =PG_LOCKED_VBASE - * pg_l1addr r0, r1, r0 - * - * Inputs (unmodified unless noted): - * l1 - The physical or virtual address of the start of the L1 table - * vaddr - The virtual address of the start of the region to span. Must - * be aligned to 1Mb section boundaries (modified) - * npages - Number of pages to required to span that memory region (modified) - * mmuflags - L1 MMU flags to use - * - * Scratch registers (modified): vaddr - * - * Return: - * The offset L1 table address is returned in result. - * - * Assumptions: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PAGING - .macro pg_l1addr, l1, vaddr, result - - /* Get result = the L1 table address coresponding to a virtual - * address. - */ - - lsr \vaddr, \vaddr, #20 - add \result, \l1, \vaddr, lsl #2 - .endm - #endif /* CONFIG_PAGING */ #endif /* __ASSEMBLY__ */ diff --git a/nuttx/arch/arm/src/arm/up_head.S b/nuttx/arch/arm/src/arm/up_head.S index cca34eae7..6cf16e168 100644 --- a/nuttx/arch/arm/src/arm/up_head.S +++ b/nuttx/arch/arm/src/arm/up_head.S @@ -191,9 +191,8 @@ __start: */ adr r0, .Ltxtspan - ldmia r0, {r0, r1, r2, r3, r4} - pg_l1addr r0, r1, r0 - pg_l1span r0, r2, r3, r4, r1 + ldmia r0, {r0, r1, r2, r3} + pg_l1span r0, r1, r2, r3, r4 /* Then populate the L2 table for the locked text region only. */ @@ -206,9 +205,8 @@ __start: */ adr r0, .Lptabspan - ldmia r0, {r0, r1, r2, r3, r4} - pg_l1addr r0, r1, r0 - pg_l1span r0, r2, r3, r4, r1 + ldmia r0, {r0, r1, r2, r3} + pg_l1span r0, r1, r2, r3, r4 /* Then populate the L2 table. */ @@ -352,8 +350,7 @@ __start: #ifdef CONFIG_PAGING .Ltxtspan: - .long PGTABLE_BASE_PADDR /* Physical address of L1 table */ - .long PG_L2_TEXT_VADDR /* Virtual address of the L2 page table */ + .long PG_L1_TEXT_PADDR /* Physical address in the L1 table */ .long PG_L2_TEXT_PADDR /* Physical address of the L2 page table */ .long PG_TEXT_NVPAGES /* Total (virtual) text pages to be mapped */ .long MMU_L1_TEXTFLAGS /* L1 MMU flags to use */ @@ -365,8 +362,7 @@ __start: .long MMU_L2_TEXTFLAGS /* L2 MMU flags to use */ .Lptabspan: - .long PGTABLE_BASE_PADDR /* Physical address of L1 table */ - .long PG_L2_PGTABLE_VADDR /* Virtual address of the L2 page table */ + .long PG_L1_PGTABLE_PADDR /* Physical address in the L1 table */ .long PG_L2_PGTABLE_PADDR /* Physical address of the L2 page table */ .long PG_PGTABLE_NPAGES /* Total mapped page table pages */ .long MMU_L1_PGTABFLAGS /* L1 MMU flags to use */ @@ -407,9 +403,8 @@ __start: /* Populate the L1 table for the data regions */ adr r0, .Ldataspan - ldmia r0, {r0, r1, r2, r3, r4} - pg_l1addr r0, r1, r0 - pg_l1span r0, r2, r3, r4, r1 + ldmia r0, {r0, r1, r2, r3} + pg_l1span r0, r1, r2, r3, r4 /* Populate the L2 table for the data region */ @@ -513,8 +508,7 @@ __start: #ifdef CONFIG_PAGING .Ldataspan: - .long PGTABLE_BASE_VADDR /* Virtual address of the L1 table */ - .long PG_L2_DATA_VADDR /* Virtual address of the L2 page table */ + .long PG_L1_DATA_VADDR /* Virtual address in the L1 table */ .long PG_L2_DATA_PADDR /* Physical address of the L2 page table */ .long PG_DATA_NPAGED /* Number of pages in the data region */ .long MMU_L1_DATAFLAGS /* L1 MMU flags to use */ |