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author | Gregory Nutt <gnutt@nuttx.org> | 2013-07-22 14:42:05 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-07-22 14:42:05 -0600 |
commit | 3e3f1fcdf06f73c648ade9c538fd80af73aaaeca (patch) | |
tree | cfb560a2bb3a9243a2751fc7df2b6690e4d5c5a6 | |
parent | bd010e1e39749c4132ed12d50040c3958b84c6fe (diff) | |
download | px4-nuttx-3e3f1fcdf06f73c648ade9c538fd80af73aaaeca.tar.gz px4-nuttx-3e3f1fcdf06f73c648ade9c538fd80af73aaaeca.tar.bz2 px4-nuttx-3e3f1fcdf06f73c648ade9c538fd80af73aaaeca.zip |
Add SAMA5 clock logic. Cloned from SAM3U and not yet verified
-rw-r--r-- | nuttx/ChangeLog | 3 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/Make.defs | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/chip/sam_matrix.h | 321 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/chip/sam_pmc.h | 399 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/chip/sam_wdt.h | 103 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sama5/sam_clockconfig.c | 284 | ||||
-rw-r--r-- | nuttx/configs/sama5d3x-ek/README.txt | 12 | ||||
-rw-r--r-- | nuttx/configs/sama5d3x-ek/include/board.h | 84 | ||||
-rwxr-xr-x | nuttx/configs/sama5d3x-ek/ostest/setenv.sh | 3 |
10 files changed, 1202 insertions, 11 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 2497cd581..c9c5231d7 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -5151,4 +5151,7 @@ to the SAMA5D3x-EK board (2013-7-21). * arch/arm/src/sama5/sam_irq.c: SAMA5 interrupt handling logic (2013-7-22). + * arch/arm/src/sama5/sam_clockconfig.c: Add SAMA5 PLL configuration + logic (plus associated header files). Initiali checkin is for the + SAM3U which is very similar but needs to be verified (2013-7-22). diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h index fe6e1ffb7..d04150008 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -500,7 +500,7 @@ # define PMC_PCR_DIV1 (0 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */ # define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */ # define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */ -# define PMC_PCR_EN (1 << 0) /* Bit 0: Enable */ +# define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */ #endif /* Oscillator Calibration Register */ diff --git a/nuttx/arch/arm/src/sama5/Make.defs b/nuttx/arch/arm/src/sama5/Make.defs index 1abd1c686..ddfb66348 100644 --- a/nuttx/arch/arm/src/sama5/Make.defs +++ b/nuttx/arch/arm/src/sama5/Make.defs @@ -62,4 +62,4 @@ endif CHIP_ASRCS = -CHIP_CSRCS = sam_boot.c sam_irq.c sam_timerisr.c +CHIP_CSRCS = sam_boot.c sam_clockconfig.c sam_irq.c sam_timerisr.c diff --git a/nuttx/arch/arm/src/sama5/chip/sam_matrix.h b/nuttx/arch/arm/src/sama5/chip/sam_matrix.h new file mode 100644 index 000000000..69df69b6b --- /dev/null +++ b/nuttx/arch/arm/src/sama5/chip/sam_matrix.h @@ -0,0 +1,321 @@ +/**************************************************************************************** + * arch/arm/src/sama5/chip/sam_matrix.h + * Bux matrix definitions for the SAMA5 + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MATRIX_H +#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MATRIX_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* MATRIX register offsets **************************************************************/ + +#define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2) +#define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */ +#define SAM_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */ +#define SAM_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */ +#define SAM_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */ +#define SAM_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */ +#define SAM_MATRIX_MCFG5_OFFSET 0x0014 /* Master Configuration Register 5 */ +#define SAM_MATRIX_MCFG6_OFFSET 0x0018 /* Master Configuration Register 6 */ +#define SAM_MATRIX_MCFG7_OFFSET 0x001c /* Master Configuration Register 7 */ +#define SAM_MATRIX_MCFG8_OFFSET 0x0020 /* Master Configuration Register 8 */ +#define SAM_MATRIX_MCFG9_OFFSET 0x0024 /* Master Configuration Register 9 */ +#define SAM_MATRIX_MCFG10_OFFSET 0x0028 /* Master Configuration Register 10 */ +#define SAM_MATRIX_MCFG11_OFFSET 0x002c /* Master Configuration Register 11 */ +#define SAM_MATRIX_MCFG12_OFFSET 0x0030 /* Master Configuration Register 12 */ +#define SAM_MATRIX_MCFG13_OFFSET 0x0034 /* Master Configuration Register 13 */ +#define SAM_MATRIX_MCFG14_OFFSET 0x0038 /* Master Configuration Register 14 */ +#define SAM_MATRIX_MCFG15_OFFSET 0x003c /* Master Configuration Register 15 */ + /* 0x0018-0x003c: Reserved */ +#define SAM_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2)) +#define SAM_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */ +#define SAM_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */ +#define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ +#define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ +#define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */ +#define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */ +#define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */ +#define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */ +#define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */ +#define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */ +#define SAM_MATRIX_SCFG10_OFFSET 0x0068 /* Slave Configuration Register 10 */ +#define SAM_MATRIX_SCFG11_OFFSET 0x006c /* Slave Configuration Register 11 */ +#define SAM_MATRIX_SCFG12_OFFSET 0x0070 /* Slave Configuration Register 12 */ +#define SAM_MATRIX_SCFG13_OFFSET 0x0074 /* Slave Configuration Register 13 */ +#define SAM_MATRIX_SCFG14_OFFSET 0x0078 /* Slave Configuration Register 14 */ +#define SAM_MATRIX_SCFG15_OFFSET 0x007c /* Slave Configuration Register 15 */ + +#define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3)) +#define SAM_MATRIX_PRBS_OFFSET(n) (0x0084+((n)<<3)) +#define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */ +#define SAM_MATRIX_PRBS0_OFFSET 0x0084 /* Priority Register B for Slave 0 */ +#define SAM_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */ +#define SAM_MATRIX_PRBS1_OFFSET 0x008c /* Priority Register B for Slave 1 */ +#define SAM_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */ +#define SAM_MATRIX_PRBS2_OFFSET 0x0094 /* Priority Register B for Slave 2 */ +#define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */ +#define SAM_MATRIX_PRBS3_OFFSET 0x009c /* Priority Register B for Slave 3 */ +#define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */ +#define SAM_MATRIX_PRBS4_OFFSET 0x00a4 /* Priority Register B for Slave 4 */ +#define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */ +#define SAM_MATRIX_PRBS5_OFFSET 0x00ac /* Priority Register B for Slave 5 */ +#define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */ +#define SAM_MATRIX_PRBS6_OFFSET 0x00b4 /* Priority Register B for Slave 6 */ +#define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */ +#define SAM_MATRIX_PRBS7_OFFSET 0x00bc /* Priority Register B for Slave 7 */ +#define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */ +#define SAM_MATRIX_PRBS8_OFFSET 0x00c4 /* Priority Register B for Slave 8 */ +#define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */ +#define SAM_MATRIX_PRBS9_OFFSET 0x00cc /* Priority Register B for Slave 9 */ +#define SAM_MATRIX_PRAS10_OFFSET 0x00d0 /* Priority Register A for Slave 10 */ +#define SAM_MATRIX_PRBS10_OFFSET 0x00d4 /* Priority Register B for Slave 10 */ +#define SAM_MATRIX_PRAS11_OFFSET 0x00d8 /* Priority Register A for Slave 11 */ +#define SAM_MATRIX_PRBS11_OFFSET 0x00dc /* Priority Register B for Slave 11 */ +#define SAM_MATRIX_PRAS12_OFFSET 0x00e0 /* Priority Register A for Slave 12 */ +#define SAM_MATRIX_PRBS12_OFFSET 0x00e4 /* Priority Register B for Slave 12 */ +#define SAM_MATRIX_PRAS13_OFFSET 0x00e8 /* Priority Register A for Slave 13 */ +#define SAM_MATRIX_PRBS13_OFFSET 0x00ec /* Priority Register B for Slave 13 */ +#define SAM_MATRIX_PRAS14_OFFSET 0x00f0 /* Priority Register A for Slave 14 */ +#define SAM_MATRIX_PRBS14_OFFSET 0x00f4 /* Priority Register B for Slave 14 */ +#define SAM_MATRIX_PRAS15_OFFSET 0x00f8 /* Priority Register A for Slave 15 */ +#define SAM_MATRIX_PRBS15_OFFSET 0x00fc /* Priority Register B for Slave 15 */ +#define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */ + /* 0X104-0X1e0: Reserved */ +#define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */ +#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */ + /* 0x0110 - 0x01fc: Reserved */ + +/* MATRIX register adresses *************************************************************/ + +#define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n)) +#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET) +#define SAM_MATRIX_MCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG1_OFFSET) +#define SAM_MATRIX_MCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET) +#define SAM_MATRIX_MCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET) +#define SAM_MATRIX_MCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET) +#define SAM_MATRIX_MCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG5_OFFSET) +#define SAM_MATRIX_MCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG6_OFFSET) +#define SAM_MATRIX_MCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG7_OFFSET) +#define SAM_MATRIX_MCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG8_OFFSET) +#define SAM_MATRIX_MCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG9_OFFSET) +#define SAM_MATRIX_MCFG10 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG10_OFFSET) +#define SAM_MATRIX_MCFG11 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG11_OFFSET) +#define SAM_MATRIX_MCFG12 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG12_OFFSET) +#define SAM_MATRIX_MCFG13 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG13_OFFSET) +#define SAM_MATRIX_MCFG14 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG14_OFFSET) +#define SAM_MATRIX_MCFG15 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG15_OFFSET) + +#define SAM_MATRIX_SCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n)) +#define SAM_MATRIX_SCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET) +#define SAM_MATRIX_SCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG1_OFFSET) +#define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET) +#define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET) +#define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET) +#define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET) +#define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET) +#define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET) +#define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET) +#define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET) +#define SAM_MATRIX_SCFG10 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG10_OFFSET) +#define SAM_MATRIX_SCFG11 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG11_OFFSET) +#define SAM_MATRIX_SCFG12 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG12_OFFSET) +#define SAM_MATRIX_SCFG13 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG13_OFFSET) +#define SAM_MATRIX_SCFG14 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG14_OFFSET) +#define SAM_MATRIX_SCFG15 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG15_OFFSET) + +#define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n)) +#define SAM_MATRIX_PRBS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRBS_OFFSET(n)) +#define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET) +#define SAM_MATRIX_PRBS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS0_OFFSET) +#define SAM_MATRIX_PRAS1 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS1_OFFSET) +#define SAM_MATRIX_PRBS1 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS1_OFFSET) +#define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET) +#define SAM_MATRIX_PRBS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS2_OFFSET) +#define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET) +#define SAM_MATRIX_PRBS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS3_OFFSET) +#define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET) +#define SAM_MATRIX_PRBS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS4_OFFSET) +#define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET) +#define SAM_MATRIX_PRBS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS5_OFFSET) +#define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET) +#define SAM_MATRIX_PRBS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS6_OFFSET) +#define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET) +#define SAM_MATRIX_PRBS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS7_OFFSET) +#define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET) +#define SAM_MATRIX_PRBS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS8_OFFSET) +#define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET) +#define SAM_MATRIX_PRBS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS9_OFFSET) +#define SAM_MATRIX_PRAS10 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS10_OFFSET) +#define SAM_MATRIX_PRBS10 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS10_OFFSET) +#define SAM_MATRIX_PRAS11 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS11_OFFSET) +#define SAM_MATRIX_PRBS11 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS11_OFFSET) +#define SAM_MATRIX_PRAS12 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS12_OFFSET) +#define SAM_MATRIX_PRBS12 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS12_OFFSET) +#define SAM_MATRIX_PRAS13 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS13_OFFSET) +#define SAM_MATRIX_PRBS13 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS13_OFFSET) +#define SAM_MATRIX_PRAS14 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS14_OFFSET) +#define SAM_MATRIX_PRBS14 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS14_OFFSET) +#define SAM_MATRIX_PRAS15 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS15_OFFSET) +#define SAM_MATRIX_PRBS15 (SAM_MATRIX_BASE+SAM_MATRIX_PRBS15_OFFSET) + +#define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET) +#define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET) +#define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET) + +/* MATRIX register bit definitions ******************************************************/ +/* Master Configuration Registers */ + +#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT) +# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */ +# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */ +# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* 4-Beat Burst */ +# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* 8-Beat Burst */ +# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* 16-Beat Burst */ +# define MATRIX_MCFG_ULBT_32BEAT (5 << MATRIX_MCFG_ULBT_SHIFT) /* 32-Beat Burst */ +# define MATRIX_MCFG_ULBT_64BEAT (6 << MATRIX_MCFG_ULBT_SHIFT) /* 64-Beat Burst */ +# define MATRIX_MCFG_ULBT_128BEAT (7 << MATRIX_MCFG_ULBT_SHIFT) /* 128-Beat Burst */ + +/* Bus Matrix Slave Configuration Registers */ + +#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-8: Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_SLOTCYCLE_MASK (0x1ff << MATRIX_SCFG_SLOTCYCLE_SHIFT) +#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */ +#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT) +#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-21: Fixed Default Master */ +#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (15 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT) + +/* Bus Matrix Priority Registers A For Slaves */ + +#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2) +#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x)) +# define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */ +# define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT) +# define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */ +# define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT) +# define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */ +# define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT) +# define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */ +# define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT) +# define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17: Master 4 Priority */ +# define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT) +# define MATRIX_PRAS_M5PR_SHIFT (20) /* Bits 20-21: Master 5 Priority */ +# define MATRIX_PRAS_M5PR_MASK (3 << MATRIX_PRAS_M5PR_SHIFT) +# define MATRIX_PRAS_M6PR_SHIFT (24) /* Bits 24-25: Master 6 Priority */ +# define MATRIX_PRAS_M6PR_MASK (3 << MATRIX_PRAS_M6PR_SHIFT) +# define MATRIX_PRAS_M7PR_SHIFT (28) /* Bits 28-29: Master 7 Priority */ +# define MATRIX_PRAS_M7PR_MASK (3 << MATRIX_PRAS_M7PR_SHIFT) + +/* Bus Matrix Priority Registers B For Slaves */ + +#define MATRIX_PRBS_MPR_SHIFT(x) ((n)<<2) +#define MATRIX_PRBS_MPR_MASK(x) (3 << MATRIX_PRBS_MPR_SHIFT(x)) +# define MATRIX_PRBS_M8PR_SHIFT (0) /* Bits 0-1: Master 8 Priority */ +# define MATRIX_PRBS_M8PR_MASK (3 << MATRIX_PRBS_M8PR_SHIFT) +# define MATRIX_PRBS_M9PR_SHIFT (4) /* Bits 4-5: Master 9 Priority */ +# define MATRIX_PRBS_M9PR_MASK (3 << MATRIX_PRBS_M9PR_SHIFT) +# define MATRIX_PRBS_M10PR_SHIFT (8) /* Bits 8-9: Master 10 Priority */ +# define MATRIX_PRBS_M10PR_MASK (3 << MATRIX_PRBS_M10PR_SHIFT) +# define MATRIX_PRBS_M11PR_SHIFT (12) /* Bits 12-13: Master 11 Priority */ +# define MATRIX_PRBS_M11PR_MASK (3 << MATRIX_PRBS_M11PR_SHIFT) +# define MATRIX_PRBS_M12PR_SHIFT (16) /* Bits 16-17: Master 12 Priority */ +# define MATRIX_PRBS_M12PR_MASK (3 << MATRIX_PRBS_M12PR_SHIFT) +# define MATRIX_PRBS_M13PR_SHIFT (20) /* Bits 20-21: Master 13 Priority */ +# define MATRIX_PRBS_M13PR_MASK (3 << MATRIX_PRBS_M13PR_SHIFT) +# define MATRIX_PRBS_M14PR_SHIFT (24) /* Bits 24-25: Master 14 Priority */ +# define MATRIX_PRBS_M14PR_MASK (3 << MATRIX_PRBS_M14PR_SHIFT) +# define MATRIX_PRBS_M15PR_SHIFT (28) /* Bits 28-29: Master 15 Priority */ +# define MATRIX_PRBS_M15PR_MASK (3 << MATRIX_PRBS_M15PR_SHIFT) + +/* Master Remap Control Register */ + +#define MATRIX_MRCR_RCB(x) (1 << (x)) +# define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for Master 0 */ +# define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for Master 1 */ +# define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for Master 2 */ +# define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for Master 3 */ +# define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for Master 4 */ +# define MATRIX_MRCR_RCB5 (1 << 5) /* Bit 5: Remap Command Bit for Master 5 */ +# define MATRIX_MRCR_RCB6 (1 << 6) /* Bit 6: Remap Command Bit for Master 6 */ +# define MATRIX_MRCR_RCB7 (1 << 7) /* Bit 7: Remap Command Bit for Master 7 */ +# define MATRIX_MRCR_RCB8 (1 << 8) /* Bit 8: Remap Command Bit for Master 8 */ +# define MATRIX_MRCR_RCB9 (1 << 9) /* Bit 9: Remap Command Bit for Master 9 */ +# define MATRIX_MRCR_RCB10 (1 << 10) /* Bit 10: Remap Command Bit for Master 10 */ +# define MATRIX_MRCR_RCB11 (1 << 11) /* Bit 11: Remap Command Bit for Master 11 */ +# define MATRIX_MRCR_RCB12 (1 << 12) /* Bit 12: Remap Command Bit for Master 12 */ +# define MATRIX_MRCR_RCB13 (1 << 13) /* Bit 13: Remap Command Bit for Master 13 */ +# define MATRIX_MRCR_RCB14 (1 << 14) /* Bit 14: Remap Command Bit for Master 14 */ +# define MATRIX_MRCR_RCB15 (1 << 15) /* Bit 15: Remap Command Bit for Master 15 */ + +/* Write Protect Mode Register */ + +#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT) +# define MATRIX_WPMR_WPKEY (0x004d4154 << MATRIX_WPMR_WPKEY_SHIFT) + +/* Write Protect Status Register */ + +#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */ +#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MATRIX_H */ diff --git a/nuttx/arch/arm/src/sama5/chip/sam_pmc.h b/nuttx/arch/arm/src/sama5/chip/sam_pmc.h new file mode 100644 index 000000000..1d44d7b62 --- /dev/null +++ b/nuttx/arch/arm/src/sama5/chip/sam_pmc.h @@ -0,0 +1,399 @@ +/******************************************************************************************** + * arch/arm/src/sama5/chip/sam_pmc.h + * Power Management Controller (PMC) for the SAMA5 + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PMC_H +#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PMC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* PMC register offsets *********************************************************************/ + +#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */ +#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ +#define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ + /* 0x000c: Reserved */ +#define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */ +#define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */ +#define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */ +#define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ +#define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */ +#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */ +#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */ + /* 0x002c: Reserved */ +#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */ + /* 0x0034: Reserved */ +#define SAM_PMC_USB_OFFSET 0x0038 /* USB Clock Register */ +#define SAM_PMC_SMD_OFFSET 0x003c /* Soft Modem Clock Register */ +#define SAM_PMC_PCK0_OFFSET 0x0040 /* Programmable Clock 0 Register */ +#define SAM_PMC_PCK1_OFFSET 0x0044 /* Programmable Clock 1 Register */ +#define SAM_PMC_PCK2_OFFSET 0x0048 /* Programmable Clock 2 Register */ + /* 0x004c-0x005c: Reserved */ +#define SAM_PMC_IER_OFFSET 0x0060 /* Interrupt Enable Register */ +#define SAM_PMC_IDR_OFFSET 0x0064 /* Interrupt Disable Register */ +#define SAM_PMC_SR_OFFSET 0x0068 /* Status Register */ +#define SAM_PMC_IMR_OFFSET 0x006c /* Interrupt Mask Register */ + /* 0x0070-0x0074: Reserved */ +#define SAM_PMC_FOCR_OFFSET 0x0078 /* Fault Output Clear Register */ + /* 0x007c: Reserved */ +#define SAM_PMC_PLLICPR_OFFSET 0x0080 /* PLL Charge Pump Current Register */ + /* 0x0084-0x00e0: Reserved */ +#define SAM_PMC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */ +#define SAM_PMC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */ + /* 0x00ec-0x00fc: Reserved */ +#define SAM_PMC_PCER1_OFFSET 0x0100 /* Peripheral Clock Enable Register 1 */ +#define SAM_PMC_PCDR1_OFFSET 0x0104 /* Peripheral Clock Disable Register 1 */ +#define SAM_PMC_PCSR1_OFFSET 0x0108 /* Peripheral Clock Status Register 1 */ +#define SAM_PMC_PCR_OFFSET 0x010c /* Peripheral Control Register */ +#define SAM_PMC_OCR_OFFSET 0x0110 /* Oscillator Calibration Register */ + +/* PMC register adresses ********************************************************************/ + +#define SAM_PMC_SCER (SAM_PMC_VBASE+SAM_PMC_SCER_OFFSET) +#define SAM_PMC_SCDR (SAM_PMC_VBASE+SAM_PMC_SCDR_OFFSET) +#define SAM_PMC_SCSR (SAM_PMC_VBASE+SAM_PMC_SCSR_OFFSET) +#define SAM_PMC_PCER0 (SAM_PMC_VBASE+SAM_PMC_PCER0_OFFSET) +#define SAM_PMC_PCDR0 (SAM_PMC_VBASE+SAM_PMC_PCDR0_OFFSET) +#define SAM_PMC_PCSR0 (SAM_PMC_VBASE+SAM_PMC_PCSR0_OFFSET) +#define SAM_PMC_CKGR_UCKR (SAM_PMC_VBASE+SAM_PMC_CKGR_UCKR_OFFSET) +#define SAM_PMC_CKGR_MOR (SAM_PMC_VBASE+SAM_PMC_CKGR_MOR_OFFSET) +#define SAM_PMC_CKGR_MCFR (SAM_PMC_VBASE+SAM_PMC_CKGR_MCFR_OFFSET) +#define SAM_PMC_CKGR_PLLAR (SAM_PMC_VBASE+SAM_PMC_CKGR_PLLAR_OFFSET) +#define SAM_PMC_MCKR (SAM_PMC_VBASE+SAM_PMC_MCKR_OFFSET) +#define SAM_PMC_USB (SAM_PMC_VBASE+SAM_PMC_USB_OFFSET) +#define SAM_PMC_SMD (SAM_PMC_VBASE+SAM_PMC_SMD_OFFSET) +#define SAM_PMC_PCK0 (SAM_PMC_VBASE+SAM_PMC_PCK0_OFFSET) +#define SAM_PMC_PCK1 (SAM_PMC_VBASE+SAM_PMC_PCK1_OFFSET) +#define SAM_PMC_PCK2 (SAM_PMC_VBASE+SAM_PMC_PCK2_OFFSET) +#define SAM_PMC_IER (SAM_PMC_VBASE+SAM_PMC_IER_OFFSET) +#define SAM_PMC_IDR (SAM_PMC_VBASE+SAM_PMC_IDR_OFFSET) +#define SAM_PMC_SR (SAM_PMC_VBASE+SAM_PMC_SR_OFFSET) +#define SAM_PMC_IMR (SAM_PMC_VBASE+SAM_PMC_IMR_OFFSET) +#define SAM_PMC_FOCR (SAM_PMC_VBASE+SAM_PMC_FOCR_OFFSET) +#define SAM_PMC_PLLICPR (SAM_PMC_VBASE+SAM_PMC_PLLICPR_OFFSET) +#define SAM_PMC_WPMR (SAM_PMC_VBASE+SAM_PMC_WPMR_OFFSET) +#define SAM_PMC_WPSR (SAM_PMC_VBASE+SAM_PMC_WPSR_OFFSET) +#define SAM_PMC_PCER1 (SAM_PMC_VBASE+SAM_PMC_PCER1_OFFSET) +#define SAM_PMC_PCDR1 (SAM_PMC_VBASE+SAM_PMC_PCDR1_OFFSET) +#define SAM_PMC_PCSR1 (SAM_PMC_VBASE+SAM_PMC_PCSR1_OFFSET) +#define SAM_PMC_PCR (SAM_PMC_VBASE+SAM_PMC_PCR_OFFSET) +#define SAM_PMC_OCR (SAM_PMC_VBASE+SAM_PMC_OCR_OFFSET) + +/* PMC register bit definitions *************************************************************/ + +/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System + * Clock Status Register common bit-field definitions + */ + +#define PMC_PCK (1 << 2) /* Bit 2: Processor Clock */ +#define PMC_DDRCK (1 << 2) /* Bit 2: DDR Clock */ +#define PMC_LCDCK (1 << 3) /* Bit 3: LCD2x Clock */ +#define PMC_SMDCK (1 << 4) /* Bit 4: SMD Clock */ +#define PMC_UHP (1 << 6) /* Bit 6: USB Host OHCI Clocks */ +#define PMC_UDP (1 << 7) /* Bit 7: USB Device Clock */ +#define PMC_PCK0 (1 << 8) /* Bit 8: Programmable Clock 0 Output */ +#define PMC_PCK1 (1 << 9) /* Bit 9: Programmable Clock 1 Output */ +#define PMC_PCK2 (1 << 10) /* Bit 10: Programmable Clock 2 Output */ + +/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC + * Peripheral Clock Status Register common bit-field definitions. + */ + +#define PMC_PIDL(n) (1 << (n)) +# define PMC_PID2 (1 << 2) /* Bit 2: Peripheral Clock 2 Enable */ +# define PMC_PID3 (1 << 3) /* Bit 3: Peripheral Clock 3 Enable */ +# define PMC_PID4 (1 << 4) /* Bit 4: Peripheral Clock 4 Enable */ +# define PMC_PID5 (1 << 5) /* Bit 5: Peripheral Clock 5 Enable */ +# define PMC_PID6 (1 << 6) /* Bit 6: Peripheral Clock 6 Enable */ +# define PMC_PID7 (1 << 7) /* Bit 7: Peripheral Clock 7 Enable */ +# define PMC_PID8 (1 << 8) /* Bit 8: Peripheral Clock 8 Enable */ +# define PMC_PID9 (1 << 9) /* Bit 9: Peripheral Clock 9 Enable */ +# define PMC_PID10 (1 << 10) /* Bit 10: Peripheral Clock 10 Enable */ +# define PMC_PID11 (1 << 11) /* Bit 11: Peripheral Clock 11 Enable */ +# define PMC_PID12 (1 << 12) /* Bit 12: Peripheral Clock 12 Enable */ +# define PMC_PID13 (1 << 13) /* Bit 13: Peripheral Clock 13 Enable */ +# define PMC_PID14 (1 << 14) /* Bit 14: Peripheral Clock 14 Enable */ +# define PMC_PID15 (1 << 15) /* Bit 15: Peripheral Clock 15 Enable */ +# define PMC_PID16 (1 << 16) /* Bit 16: Peripheral Clock 16 Enable */ +# define PMC_PID17 (1 << 17) /* Bit 17: Peripheral Clock 17 Enable */ +# define PMC_PID18 (1 << 18) /* Bit 18: Peripheral Clock 18 Enable */ +# define PMC_PID19 (1 << 19) /* Bit 19: Peripheral Clock 19 Enable */ +# define PMC_PID20 (1 << 20) /* Bit 20: Peripheral Clock 20 Enable */ +# define PMC_PID21 (1 << 21) /* Bit 21: Peripheral Clock 21 Enable */ +# define PMC_PID22 (1 << 22) /* Bit 22: Peripheral Clock 22 Enable */ +# define PMC_PID23 (1 << 23) /* Bit 23: Peripheral Clock 23 Enable */ +# define PMC_PID24 (1 << 24) /* Bit 24: Peripheral Clock 24 Enable */ +# define PMC_PID25 (1 << 25) /* Bit 25: Peripheral Clock 25 Enable */ +# define PMC_PID26 (1 << 26) /* Bit 26: Peripheral Clock 26 Enable */ +# define PMC_PID27 (1 << 27) /* Bit 27: Peripheral Clock 27 Enable */ +# define PMC_PID28 (1 << 28) /* Bit 28: Peripheral Clock 28 Enable */ +# define PMC_PID29 (1 << 29) /* Bit 29: Peripheral Clock 29 Enable */ +# define PMC_PID30 (1 << 30) /* Bit 30: Peripheral Clock 30 Enable */ +# define PMC_PID31 (1 << 31) /* Bit 31: Peripheral Clock 31 Enable */ + +/* PMC UTMI Clock Configuration Register */ + +#define PMC_CKGR_UCKR_UPLLEN (1 << 16) /* Bit 16: UTMI PLL Enable */ +#define PMC_CKGR_UCKR_UPLLCOUNT_SHIFT (20) /* Bits 20-23: UTMI PLL Start-up Time */ +#define PMC_CKGR_UCKR_UPLLCOUNT_MASK (15 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) +#define PMC_CKGR_UCKR_BIASEN (1 << 24) /* Bit 24: UTMI BIAS Enable */ +#define PMC_CKGR_UCKR_BIASCOUNT_SHIFT (28) /* Bits 28-31: UTMI BIAS Start-up Time */ +#define PMC_CKGR_UCKR_BIASCOUNT_MASK (15 << PMC_CKGR_UCKR_BIASCOUNT_SHIFT) */ + +/* PMC Clock Generator Main Oscillator Register */ + +#define PMC_CKGR_MOR_MOSCXTEN (1 << 0) /* Bit 0: Main Crystal Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCXTBY (1 << 1) /* Bit 1: Main Crystal Oscillator Bypass */ +#define PMC_CKGR_MOR_MOSCRCEN (1 << 3) /* Bit 3: Main On-Chip RC Oscillator Enable */ +#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-16: Main Crystal Oscillator Start-up Time */ +#define PMC_CKGR_MOR_MOSCXTST_MASK (0x1ff << PMC_CKGR_MOR_MOSCXTST_SHIFT) +#define PMC_CKGR_MOR_KEY_SHIFT (16) /* Bits 16-23: Password */ +#define PMC_CKGR_MOR_KEY_MASK (0xff << PMC_CKGR_MOR_KEY_SHIFT) +# define PMC_CKGR_MOR_KEY (0x37 << PMC_CKGR_MOR_KEY_SHIFT) +#define PMC_CKGR_MOR_MOSCSEL (1 << 24) /* Bit 24: Main Oscillator Selection */ +#define PMC_CKGR_MOR_CFDEN (1 << 25) /* Bit 25: Clock Failure Detector Enable */ + +/* PMC Clock Generator Main Clock Frequency Register */ + +#define PMC_CKGR_MCFR_MAINF_SHIFT (0) /* Bits 0-15: Main Clock Frequency */ +#define PMC_CKGR_MCFR_MAINF_MASK (0xffff << PMC_CKGR_MCFR_MAINF_SHIFT) +#define PMC_CKGR_MCFR_MAINFRDY (1 << 16) /* Bit 16: Main Clock Ready */ + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define PMC_CKGR_MCFR_RCMEAS (1 << 20) /* Bit 20: RC Oscillator Frequency Measure (write-only) */ +#endif + +/* PMC Clock Generator PLLA Register */ + +#define PMC_CKGR_PLLAR_DIV_SHIFT (0) /* Bits 0-7: Divider */ +#define PMC_CKGR_PLLAR_DIV_MASK (0xff << PMC_CKGR_PLLAR_DIV_SHIFT) +# define PMC_CKGR_PLLAR_DIV_ZERO (0 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is 0 */ +# define PMC_CKGR_PLLAR_DIV_BYPASS (1 << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */ +# define PMC_CKGR_PLLAR_DIV(n) ((n) << PMC_CKGR_PLLAR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */ +#define PMC_CKGR_PLLAR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */ +#define PMC_CKGR_PLLAR_COUNT_MASK (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define PMC_CKGR_PLLAR_OUT_SHIFT (16) /* Bits 16-17: PLLA Clock Frequency Range */ +#define PMC_CKGR_PLLAR_OUT_MASK (3 << PMC_CKGR_PLLAR_OUT_SHIFT) +# define PMC_CKGR_PLLAR_OUT (0 << PMC_CKGR_PLLAR_OUT_SHIFT) /* To be programmed to 0 */ +#define PMC_CKGR_PLLAR_MUL_SHIFT (18) /* Bits 18-24: PLLA Multiplier */ +#define PMC_CKGR_PLLAR_MUL_MASK (0x7f << PMC_CKGR_PLLAR_MUL_SHIFT) +#define PMC_CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */ + +/* PMC Master Clock Register */ + +#define PMC_MCKR_CSS_SHIFT (0) /* Bits 0-1: Master Clock Source Selection */ +#define PMC_MCKR_CSS_MASK (3 << PMC_MCKR_CSS_SHIFT) +# define PMC_MCKR_CSS_SLOW (0 << PMC_MCKR_CSS_SHIFT) /* Slow Clock */ +# define PMC_MCKR_CSS_MAIN (1 << PMC_MCKR_CSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CSS_PLLA (2 << PMC_MCKR_CSS_SHIFT) /* PLLA Clock */ +# define PMC_MCKR_CSS_UPLL (3 << PMC_MCKR_CSS_SHIFT) /* UPLL Clock */ +#define PMC_MCKR_PRES_SHIFT (4) /* Bits 4-6: Processor Clock Prescaler */ +#define PMC_MCKR_PRES_MASK (7 << PMC_MCKR_PRES_SHIFT) +# define PMC_MCKR_PRES_DIV1 (0 << PMC_MCKR_PRES_SHIFT) /* Selected clock */ +# define PMC_MCKR_PRES_DIV2 (1 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_MCKR_PRES_DIV4 (2 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_MCKR_PRES_DIV8 (3 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_MCKR_PRES_DIV16 (4 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_MCKR_PRES_DIV32 (5 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_MCKR_PRES_DIV64 (6 << PMC_MCKR_PRES_SHIFT) /* Selected clock divided by 64 */ +#define PMC_MCKR_MDIV_SHIFT (8) /* Bits 8-9: Master Clock Division */ +#define PMC_MCKR_MDIV_MASK (3 << PMC_MCKR_MDIV_SHIFT) +# define PMC_MCKR_MDIV_PCKDIV1 (0 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 1 */ +# define PMC_MCKR_MDIV_PCKDIV2 (1 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 2 */ +# define PMC_MCKR_MDIV_PCKDIV4 (2 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 4 */ +# define PMC_MCKR_MDIV_MASPCK1DIV3K (3 << PMC_MCKR_MDIV_SHIFT) /* Prescaler Output Clock divided by 3 */ +#define PMC_MCKR_PLLADIV2 (1 << 12) /* Bit 12: PLLA Divider */ + +/* USB Clock Register PMC_USB */ + +#define PMC_USB_USBS (1 << 0) /* Bit 0: USB Input Clock Selection */ +# define PMC_USB_USBS_PLLA (0) +# define PMC_USB_USBS_UPLL PMC_USB_USBS +#define PMC_USB_USBDIV_SHIFT (8) /* Bits 8-11: Divider for USB Clock */ +#define PMC_USB_USBDIV_MASK (15 << PMC_USB_USBDIV_SHIFT) + +/* Soft Modem Clock Register */ + +#define PMC_SMD_SMDS (1 << 0) /* Bit 0: SMD Input Clock Selection */ +# define PMC_SMD_SMDS_PLLA (0) +# define PMC_SMD_SMDS_UPLL PMC_SMD_SMDS +#define PMC_SMD_SMDDIV_SHIFT (8) /* Bits 8-12: Divider for SMD Clock */ +#define PMC_SMD_SMDDIV_MASK (31 << PMC_SMD_SMDDIV_SHIFT) + +/* PMC Programmable Clock Register (0,1,2) */ + +#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */ +#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK) +# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */ +# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */ +# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */ +# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */ +# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_MASK) /* Master Clock */ +#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */ +#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT) +# define PMC_PCK_PRES_DIV1 (0 << PMC_PCK_PRES_SHIFT) /* Selected clock */ +# define PMC_PCK_PRES_DIV2 (1 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 2 */ +# define PMC_PCK_PRES_DIV4 (2 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 4 */ +# define PMC_PCK_PRES_DIV8 (3 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 8 */ +# define PMC_PCK_PRES_DIV16 (4 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 16 */ +# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */ +# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */ + +/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register, + * and PMC Interrupt Mask Register common bit-field definitions + */ + +#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */ +#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */ +#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */ +#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */ +#define PMC_INT_PCKRDY0 (1 << 8) /* Bit 8: Programmable Clock Ready 0 Interrupt */ +#define PMC_INT_PCKRDY1 (1 << 9) /* Bit 9: Programmable Clock Ready 1 Interrupt */ +#define PMC_INT_PCKRDY2 (1 << 10) /* Bit 10: Programmable Clock Ready 2 Interrupt */ +#define PMC_INT_MOSCSELS (1 << 16) /* Bit 16: Main Oscillator Selection Status Interrupt */ +#define PMC_INT_MOSCRCS (1 << 17) /* Bit 17: Main On-Chip RC Status Interrupt */ +#define PMC_INT_CFDEV (1 << 18) /* Bit 18: Clock Failure Detector Event Interrupt */ +#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */ +#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */ + +/* PMC Fault Output Clear Register */ + +#define PMC_FOCLR (1 << 0) /* Bit 0: Fault Output Clear */ + +/* PLL Charge Pump Current Register */ + +#define PMC_PLLICPR_ICP_PLLA_SHIFT (0) /* Bits 0-1: Charge Pump Current PLLA */ +#define PMC_PLLICPR_ICP_PLLA_MASK (3 << PMC_PLLICPR_ICP_PLLA_SHIFT) +#define PMC_PLLICPR_IPLL_PLLA_SHIFT (8) /* Bits 8-10: Engineering Configuration PLLA */ +#define PMC_PLLICPR_IPLL_PLLA_MASK (7 << PMC_PLLICPR_IPLL_PLLA_SHIFT) +#define PMC_PLLICPR_ICP_PLLU_SHIFT (16) /* Bits 16-17: Charge Pump Current PLL UTMI */ +#define PMC_PLLICPR_ICP_PLLU_MASK (3 << PMC_PLLICPR_ICP_PLLU_SHIFT) +#define PMC_PLLICPR_IVCO_PLLU_SHIFT (14) /* Bits 24-15: Voltage Control Output Current PLL UTMI */ +#define PMC_PLLICPR_IVCO_PLLU_MASK (3 << PMC_PLLICPR_IVCO_PLLU_SHIFT) + +/* PMC Write Protect Mode Register */ + +#define PMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ +#define PMC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ +#define PMC_WPMR_WPKEY_MASK (0x00ffffff << PMC_WPMR_WPKEY_SHIFT) +# define PMC_WPMR_WPKEY (0x00504d43 << PMC_WPMR_WPKEY_SHIFT) + +/* PMC Write Protect Status Register */ + +#define PMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */ +#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) + +/* Peripheral Clock Enable Register 1 */ +/* Peripheral Clock Disable Register 1 */ +/* Peripheral Clock Status Register 1 */ + +#define PMC_PIDH(n) (1 << ((n) - 32)) +# define PMC_PID32 (1 << 0) /* Bit 0: PID32 */ +# define PMC_PID33 (1 << 1) /* Bit 1: PID33 */ +# define PMC_PID34 (1 << 2) /* Bit 2: PID34 */ +# define PMC_PID35 (1 << 3) /* Bit 3: PID35 */ +# define PMC_PID36 (1 << 4) /* Bit 4: PID36 */ +# define PMC_PID37 (1 << 5) /* Bit 5: PID37 */ +# define PMC_PID38 (1 << 6) /* Bit 6: PID38 */ +# define PMC_PID39 (1 << 7) /* Bit 7: PID39 */ +# define PMC_PID40 (1 << 8) /* Bit 8: PID40 */ +# define PMC_PID41 (1 << 9) /* Bit 9: PID41 */ +# define PMC_PID42 (1 << 10) /* Bit 10: PID42 */ +# define PMC_PID43 (1 << 11) /* Bit 11: PID43 */ +# define PMC_PID44 (1 << 12) /* Bit 12: PID44 */ +# define PMC_PID45 (1 << 13) /* Bit 13: PID45 */ +# define PMC_PID46 (1 << 14) /* Bit 14: PID46 */ +# define PMC_PID47 (1 << 15) /* Bit 15: PID47 */ +# define PMC_PID48 (1 << 16) /* Bit 16: PID48 */ +# define PMC_PID49 (1 << 17) /* Bit 17: PID49 */ +# define PMC_PID50 (1 << 18) /* Bit 18: PID50 */ +# define PMC_PID51 (1 << 19) /* Bit 19: PID51 */ +# define PMC_PID52 (1 << 20) /* Bit 20: PID52 */ +# define PMC_PID53 (1 << 21) /* Bit 21: PID53 */ +# define PMC_PID54 (1 << 22) /* Bit 22: PID54 */ +# define PMC_PID55 (1 << 23) /* Bit 23: PID55 */ +# define PMC_PID56 (1 << 24) /* Bit 24: PID56 */ +# define PMC_PID57 (1 << 25) /* Bit 25: PID57 */ +# define PMC_PID58 (1 << 26) /* Bit 26: PID58 */ +# define PMC_PID59 (1 << 27) /* Bit 27: PID59 */ +# define PMC_PID60 (1 << 28) /* Bit 28: PID50 */ +# define PMC_PID61 (1 << 29) /* Bit 29: PID61 */ +# define PMC_PID62 (1 << 30) /* Bit 30: PID62 */ +# define PMC_PID63 (1 << 31) /* Bit 31: PID63 */ + +/* Peripheral Control Register */ + +#define PMC_PCR_PID_SHIFT (0) /* Bits 0-5: Peripheral ID */ +#define PMC_PCR_PID_MASK (63 < PMC_PCR_PID_SHIFT) +#define PMC_PCR_CMD (1 << 12) /* Bit 12: Command */ +#define PMC_PCR_DIV_SHIFT (16) /* Bits 16-17: Divisor Value */ +#define PMC_PCR_DIV_MASK (3 < PMC_PCR_DIV_SHIFT) +# define PMC_PCR_DIV1 (0 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */ +# define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */ +# define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */ +# define PMC_PCR_DIV8 (3 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/8 */ +#define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */ + +/* Oscillator Calibration Register */ + +#define PMC_OCR_CAL_SHIFT (0) /* Bits 0-6: 12 MHz RC Oscillator Calibration bits */ +#define PMC_OCR_CAL_MASK (0x7f << PMC_OCR_CAL_SHIFT) +#define PMC_OCR_SEL (1 << 7) /* Bit 7: Selection of RC Oscillator Calibration bits */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PMC_H */ diff --git a/nuttx/arch/arm/src/sama5/chip/sam_wdt.h b/nuttx/arch/arm/src/sama5/chip/sam_wdt.h new file mode 100644 index 000000000..c42bcb98f --- /dev/null +++ b/nuttx/arch/arm/src/sama5/chip/sam_wdt.h @@ -0,0 +1,103 @@ +/**************************************************************************************** + * arch/arm/src/sama5/chip/sam_wdt.h + * Watchdog Timer (WDT) definitions for the SAMA5 + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_WDT_H +#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_WDT_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "chip/sam_memorymap.h" + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* WDT register offsets ****************************************************************/ + +#define SAM_WDT_CR_OFFSET 0x00 /* Control Register */ +#define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */ +#define SAM_WDT_SR_OFFSET 0x08 /* Status Register */ + +/* WDT register adresses ***************************************************************/ + +#define SAM_WDT_CR (SAM_WDT_VBASE+SAM_WDT_CR_OFFSET) +#define SAM_WDT_MR (SAM_WDT_VBASE+SAM_WDT_MR_OFFSET) +#define SAM_WDT_SR (SAM_WDT_VBASE+SAM_WDT_SR_OFFSET) + +/* WDT register bit definitions ********************************************************/ +/* Watchdog Timer Control Register */ + +#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */ +#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */ +#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT) +# define WDT_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT) + +/* Watchdog Timer Mode Register */ + +#define WDT_MR_WDV_SHIFT (0) /* Bits 0-11: Watchdog Counter Value */ +#define WDT_MR_WDV_MASK (0xfff << WDT_MR_WDV_SHIFT) +#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor */ +#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */ +#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value */ +#define WDT_MR_WDD_MASK (0xfff << WDT_MR_WDD_SHIFT) +#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */ + +/* Watchdog Timer Status Register */ + +#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */ +#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */ + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_WDT_H */ diff --git a/nuttx/arch/arm/src/sama5/sam_clockconfig.c b/nuttx/arch/arm/src/sama5/sam_clockconfig.c new file mode 100644 index 000000000..64040dd95 --- /dev/null +++ b/nuttx/arch/arm/src/sama5/sam_clockconfig.c @@ -0,0 +1,284 @@ +/**************************************************************************** + * arch/arm/src/sama5/sam_clockconfig.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include "up_arch.h" +#include "up_internal.h" + +#include "sam_clockconfig.h" +#include "chip/sam_pmc.h" +#include "chip/sam_wdt.h" +#include "chip/sam_matrix.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* PMC register settings based on the board configuration values defined + * in board.h + */ + +#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \ + PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN) +#define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \ + BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV) +#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN) +#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS) +#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_wdtsetup + * + * Description: + * Disable the watchdog timer + * + ****************************************************************************/ + +static inline void sam_wdtsetup(void) +{ + putreg32(WDT_MR_WDDIS, SAM_WDT_MR); +} + +/**************************************************************************** + * Name: sam_pmcwait + * + * Description: + * Wait for the specide PMC status bit to become "1" + * + ****************************************************************************/ + +static void sam_pmcwait(uint32_t bit) +{ + volatile uint32_t delay; + + for (delay = 0; + (getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX; + delay++); +} + +/**************************************************************************** + * Name: sam_pmcsetup + * + * Description: + * Initialize clocking + * + ****************************************************************************/ + +static inline void sam_pmcsetup(void) +{ + uint32_t regval; + + /* Enable main oscillator (if it has not already been selected) */ + + if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0) + { + /* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to + * enable the main oscillator, the MOSCXTS bit in the Power Management + * Controller Status Register (PMC_SR) is cleared and the counter starts + * counting down on the slow clock divided by 8 from the MOSCXTCNT + * value. ... When the counter reaches 0, the MOSCXTS bit is set, + * indicating that the main clock is valid." + */ + + putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR); + sam_pmcwait(PMC_INT_MOSCXTS); + } + + /* "Switch to the main oscillator. The selection is made by writing the + * MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of + * the Main Clock source is glitch free, so there is no need to run out + * of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS + * bit of the power Management Controller Status Register (PMC_SR) allows + * knowing when the switch sequence is done." + * + * MOSCSELS: Main Oscillator Selection Status + * 0 = Selection is done + * 1 = Selection is in progress + */ + + putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR); + sam_pmcwait(PMC_INT_MOSCSELS); + + /* "Select the master clock. "The Master Clock selection is made by writing + * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). + * The prescaler supports the division by a power of 2 of the selected clock + * between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs + * the prescaler. Each time PMC_MCKR is written to define a new Master Clock, + * the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is + * established. + */ + + regval = getreg32(SAM_PMC_MCKR); + regval &= ~PMC_MCKR_CSS_MASK; + regval |= PMC_MCKR_CSS_MAIN; + putreg32(regval, SAM_PMC_MCKR); + sam_pmcwait(PMC_INT_MCKRDY); + + /* Setup PLLA and wait for LOCKA */ + + putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR); + sam_pmcwait(PMC_INT_LOCKA); + + /* Setup UTMI for USB and wait for LOCKU */ + +#ifdef CONFIG_USBDEV + regval = getreg32(SAM_PMC_CKGR_UCKR); + regval |= BOARD_CKGR_UCKR; + putreg32(regval, SAM_PMC_CKGR_UCKR); + sam_pmcwait(PMC_INT_LOCKU); +#endif + + /* Switch to the fast clock and wait for MCKRDY */ + + putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR); + sam_pmcwait(PMC_INT_MCKRDY); + + putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR); + sam_pmcwait(PMC_INT_MCKRDY); +} + +/**************************************************************************** + * Name: sam_enabledefaultmaster and sam_disabledefaultmaster + * + * Description: + * Enable/disable default master access + * + ****************************************************************************/ + +static inline void sam_enabledefaultmaster(void) +{ +#warning Missing Logic +#if 0 + uint32_t regval; + + /* Set default master: SRAM0 -> Cortex-A5 System */ + + regval = getreg32(SAM_MATRIX_SCFG0); + regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + putreg32(regval, SAM_MATRIX_SCFG0); + + /* Set default master: SRAM1 -> Cortex-A5 System */ + + regval = getreg32(SAM_MATRIX_SCFG1); + regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + putreg32(regval, SAM_MATRIX_SCFG1); + + /* Set default master: Internal flash0 -> Cortex-A5 Instruction/Data */ + + regval = getreg32(SAM_MATRIX_SCFG3); + regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED); + putreg32(regval, SAM_MATRIX_SCFG3); +#endif +} + +#if 0 /* Not used */ +static inline void sam_disabledefaultmaster(void) +{ + uint32_t regval; + + /* Clear default master: SRAM0 -> Cortex-A5 System */ + + regval = getreg32(SAM_MATRIX_SCFG0); + regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; + putreg32(regval, SAM_MATRIX_SCFG0); + + /* Clear default master: SRAM1 -> Cortex-A5 System */ + + regval = getreg32(SAM_MATRIX_SCFG1); + regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; + putreg32(regval, SAM_MATRIX_SCFG1); + + /* Clear default master: Internal flash0 -> Cortex-A5 Instruction/Data */ + + regval = getreg32(SAM_MATRIX_SCFG3); + regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK; + putreg32(regval, SAM_MATRIX_SCFG3); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_clockconfig + * + * Description: + * Called to initialize the SAM3/4. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. (After power-on reset, the SAM3/4 + * is initially running on a 12MHz internal RC clock). This function also + * performs other low-level chip initialization of the chip including master + * clock, IRQ & watchdog configuration. + * + ****************************************************************************/ + +void sam_clockconfig(void) +{ + /* Configure the watchdog timer */ + + sam_wdtsetup(); + + /* Initialize clocking */ + + sam_pmcsetup(); + + /* Optimize CPU setting for speed */ + + sam_enabledefaultmaster(); +} diff --git a/nuttx/configs/sama5d3x-ek/README.txt b/nuttx/configs/sama5d3x-ek/README.txt index 25049c468..d7260e3cb 100644 --- a/nuttx/configs/sama5d3x-ek/README.txt +++ b/nuttx/configs/sama5d3x-ek/README.txt @@ -50,10 +50,9 @@ GNU Toolchain Options The NuttX make system will support the several different toolchain options. - All testing has been conducted using the AtmelStudio GCC toolchain. To use - the CodeSourcery, devkitARM or other GNU toolchain, you simply need to add - add one of the following configuration options to your .config (or defconfig) - file: + All testing has been conducted using the CodeSourcery GCC toolchain. To use + a different toolchain, you simply need to add change to one of the following + configuration options to your .config (or defconfig) file: CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYL=y : CodeSourcery under Linux @@ -63,8 +62,9 @@ GNU Toolchain Options CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIL=y : Generic GCC ARM EABI toolchain for Linux CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW=y : Generic GCC ARM EABI toolchain for Windows - The AtmelStudio GCC toolchain is selected with CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW=y - and setting the PATH variable appropriately. + The CodeSourcery GCC toolchain is selected with + CONFIG_ARMV7A_TOOLCHAIN_GNU_EABIW=y and setting the PATH variable + appropriately. If you are not using AtmelStudio GCC toolchain, then you may also have to modify the PATH in the setenv.h file if your make cannot find the tools. diff --git a/nuttx/configs/sama5d3x-ek/include/board.h b/nuttx/configs/sama5d3x-ek/include/board.h index 8759dce55..4bc9de143 100644 --- a/nuttx/configs/sama5d3x-ek/include/board.h +++ b/nuttx/configs/sama5d3x-ek/include/board.h @@ -47,10 +47,90 @@ ************************************************************************************/ /* Clocking *************************************************************************/ +/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These + * definitions will configure clocking + * + * MAINOSC: Frequency = 12MHz (crysta) + * PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz + * Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 96MHz + * CPU clock: 96MHz + */ + +/* Main oscillator register settings. + * + * The start up time should be should be: + * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. + */ + +#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration. + * + * Divider = 1 + * Multipler = 16 + */ + +#define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS + +/* PMC master clock register settings. + * + * Source = PLLA + * Divider = 2 + */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2 + +/* USB UTMI PLL start-up time */ + +#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) -/* Resulting clock frquencies *******************************************************/ +/* Resulting frequencies */ -#define BOARD_MCK_FREQUENCY 0 /* FIXME */ +#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ +#define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */ +#define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */ +#define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */ + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV+1)). + * + * MCI_SPEED = MCK / (2*(CLKDIV+1)) + * CLKDIV = MCI / MCI_SPEED / 2 - 1 + * + * Where CLKDIV has a range of 0-255. + */ + +/* MCK = 96MHz, CLKDIV = 119, MCI_SPEED = 96MHz / 2 * (119+1) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (119 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 96MHz, CLKDIV = 3, MCI_SPEED = 96MHz / 2 * (3+1) = 12 MHz */ + +#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 96MHz, CLKDIV = 1, MCI_SPEED = 96MHz / 2 * (1+1) = 24 MHz */ + +#define HSMCI_SDXFR_CLKDIV (1 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/* FLASH wait states + * + * FWS Max frequency + * 1.62V 1.8V + * --- ----- ------ + * 0 24MHz 27MHz + * 1 40MHz 47MHz + * 2 72MHz 84MHz + * 3 84MHz 96MHz + */ + +#define BOARD_FWS 3 /* LED definitions ******************************************************************/ diff --git a/nuttx/configs/sama5d3x-ek/ostest/setenv.sh b/nuttx/configs/sama5d3x-ek/ostest/setenv.sh index 1378d4298..9b2028586 100755 --- a/nuttx/configs/sama5d3x-ek/ostest/setenv.sh +++ b/nuttx/configs/sama5d3x-ek/ostest/setenv.sh @@ -50,12 +50,13 @@ fi # This is the Cygwin path to the location where I installed the Atmel GCC # toolchain under Windows. You will also have to edit this if you install # this toolchain in any other location -export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" # This is the Cygwin path to the location where I installed the CodeSourcery # toolchain under windows. You will also have to edit this if you install # the CodeSourcery toolchain in any other location #export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" # These are the Cygwin paths to the locations where I installed the Atollic # toolchain under windows. You will also have to edit this if you install |