diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-22 16:08:21 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-11-22 16:08:21 +0000 |
commit | 84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a (patch) | |
tree | fd3d96de23b5b5c7021565041f59e7d8c7b69b8b | |
parent | 1c87f4d5e59da4337f5372c191a860916f593794 (diff) | |
download | px4-nuttx-84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a.tar.gz px4-nuttx-84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a.tar.bz2 px4-nuttx-84c5686eebe6ed9e044dfff4199ea4c0f0fc1e6a.zip |
Working toward clean STM3240xx build
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4119 42af7a65-404d-4744-a932-0658087f49c3
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_adc.h | 26 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_flash.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32_spi.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h | 1 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h | 172 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h | 47 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h | 129 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_gpio.h | 26 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_rcc.c | 439 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_vectors.S | 434 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c | 541 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c | 162 |
15 files changed, 1084 insertions, 905 deletions
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_adc.h b/nuttx/arch/arm/src/stm32/chip/stm32_adc.h index c8e9f8163..5893ae625 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_adc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_adc.h @@ -503,21 +503,21 @@ #ifdef CONFIG_STM32_STM32F40XX # define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ # define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT) -# define ADC_CCR_MULTI_NON (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ +# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ -# define ADC_CCR_MULTI_ MASK (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_ MASK (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ MASK (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ -# define ADC_CCR_MULTI_ MASK (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ +# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ -# define ADC_CCR_MULTI_ MASK (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_ MASK (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ MASK (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_ MASK (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ -# define ADC_CCR_MULTI_ MASK (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ +# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ /* Bits 5-7: Reserved, must be kept at reset value. */ # define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ # define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h index 6fa2f15b0..596a86017 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_flash.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_flash.h @@ -54,7 +54,7 @@ # define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32_STM32F40XX) # define STM32_FLASH_NPAGES 8 -# define CONFIG_STM32_STM32F40XX (128*1024) +# define STM32_FLASH_PAGESIZE (128*1024) #endif #define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_spi.h b/nuttx/arch/arm/src/stm32/chip/stm32_spi.h index 844a12c33..93796f9b5 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_spi.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_spi.h @@ -162,7 +162,7 @@ #define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ #ifdef CONFIG_STM32_STM32F40XX -# define SPI_SR_TIFRFE:E (1 << 8) /* Bit 8: TI frame format error */ +# define SPI_SR_TIFRFE (1 << 8) /* Bit 8: TI frame format error */ #endif /* I2S configuration register */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h index 70701838a..f04b15d23 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_dma.h @@ -348,4 +348,3 @@ #define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H */ - diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h new file mode 100644 index 000000000..0d6b965d2 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h @@ -0,0 +1,172 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f10xxx_vectors.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ + +/* This file is included by stm32_vectors.S. It provides the macro VECTOR that + * supplies ach STM32F10xxx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f10xxx_irq.h. + * stm32_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +#ifdef CONFIG_STM32_CONNECTIVITY_LINE + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper interrupt */ +VECTOR(stm32_rtc, STM32_IRQ_RTC) /* Vector 16+3: RTC global interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */ +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* Vector 16+11: DMA1 Channel 1 global interrupt */ +VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* Vector 16+12: DMA1 Channel 2 global interrupt */ +VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* Vector 16+13: DMA1 Channel 3 global interrupt */ +VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* Vector 16+14: DMA1 Channel 4 global interrupt */ +VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* Vector 16+15: DMA1 Channel 5 global interrupt */ +VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* Vector 16+16: DMA1 Channel 7 global interrupt */ +VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* Vector 16+18: ADC1 and ADC2 global interrupt */ +VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */ +VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */ +VECTOR(stm32_can1rx, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */ +VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt */ +VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt */ +VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts */ +VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */ +VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */ +VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */ +VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */ +VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */ +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalr, STM32_IRQ_RTCALR) /* Vector 16+41: RTC alarm through EXTI line interrupt */ +VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */ +VECTOR(stm32_spi3, STM32_IRQ_SPI3 ) /* Vector 16+51: SPI3 global interrupt */ +VECTOR(stm32_uart4 , STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */ +VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */ +VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt */ +VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */ +VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 global interrupt */ +VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* Vector 16+57: DMA2 Channel 2 global interrupt */ +VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 global interrupt */ +VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* Vector 16+59: DMA2 Channel 4 global interrupt */ +VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* Vector 16+60: DMA2 Channel 5 global interrupt */ +VECTOR(stm32_eth, STM32_IRQ_ETH) /* Vector 16+61: Ethernet global interrupt */ +VECTOR(stm32_ethwkup, STM32_IRQ_ETHWKUP) /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */ +VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */ +VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */ +VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */ +VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */ +VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */ + +#else + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper interrupt */ +VECTOR(stm32_rtc, STM32_IRQ_RTC) /* Vector 16+3: RTC global interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */ +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* Vector 16+11: DMA1 Channel 1 global interrupt */ +VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* Vector 16+12: DMA1 Channel 2 global interrupt */ +VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* Vector 16+13: DMA1 Channel 3 global interrupt */ +VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* Vector 16+14: DMA1 Channel 4 global interrupt */ +VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* Vector 16+15: DMA1 Channel 5 global interrupt */ +VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* Vector 16+16: DMA1 Channel 6 global interrupt */ +VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* Vector 16+17: DMA1 Channel 7 global interrupt */ +VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* Vector 16+18: ADC1 and ADC2 global interrupt */ +VECTOR(stm32_usbhpcantx, STM32_IRQ_USBHPCANTX) /* Vector 16+19: USB High Priority or CAN TX interrupts*/ +VECTOR(stm32_usblpcanrx0, STM32_IRQ_USBLPCANRX0) /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/ +VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */ +VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt */ +VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt */ +VECTOR(stm32_tim1rtgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts */ +VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */ +VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */ +VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */ +VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */ +VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */ +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalr, STM32_IRQ_RTCALR) /* Vector 16+41: RTC alarm through EXTI line interrupt */ +VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP) /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/ +VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt */ +VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrupt */ +VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts */ +VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */ +VECTOR(stm32_adc3, STM32_IRQ_ADC3) /* Vector 16+47: ADC3 global interrupt */ +VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */ +VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */ +VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */ +VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */ +VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */ +VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */ +VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt */ +VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */ +VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 global interrupt */ +VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* Vector 16+57: DMA2 Channel 2 global interrupt */ +VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 global interrupt */ +VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45) /* Vector 16+59: DMA2 Channel 4&5 global interrupt */ +#endif diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h index 3c0939b7f..bfd2857f2 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_dma.h @@ -82,12 +82,6 @@ #define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ #define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ -#define STM32_DMA_SCR_OFFSET(n) (STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA_SNDTR_OFFSET(n) (STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA_SPAR_OFFSET(n) (STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA_SM0AR_OFFSET(n) (STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA_SM1AR_OFFSET(n) (STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) - #define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ #define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ #define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ @@ -149,7 +143,7 @@ #define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) #define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) -#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET(n)) +#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) #define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) #define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) @@ -159,7 +153,7 @@ #define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) #define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) -#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET(n)) +#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) #define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) #define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) @@ -169,7 +163,7 @@ #define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) #define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) -#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET(n)) +#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) #define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) #define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) @@ -179,7 +173,7 @@ #define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) #define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) -#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET(n)) +#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) #define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) #define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) @@ -189,7 +183,7 @@ #define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) #define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) -#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET(n)) +#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) #define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) #define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) @@ -199,7 +193,7 @@ #define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) #define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) -#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET(n)) +#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) #define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) #define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) @@ -214,7 +208,7 @@ #define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) #define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) -#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET(n)) +#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) #define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) #define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) @@ -224,7 +218,7 @@ #define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) #define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) -#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET(n)) +#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) #define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) #define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) @@ -234,7 +228,7 @@ #define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) #define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) -#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET(n)) +#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) #define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) #define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) @@ -244,7 +238,7 @@ #define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) #define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) -#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET(n)) +#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) #define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) #define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) @@ -254,7 +248,7 @@ #define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) #define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) -#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET(n)) +#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) #define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) #define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) @@ -264,7 +258,7 @@ #define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) #define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) -#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET(n)) +#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) #define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) #define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) #define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) @@ -286,7 +280,7 @@ /* DMA interrupt status register */ #define DMA_LISR_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt status */ -#define DMA_LISR_STREAM1_MASK (DMA_STREAM_MASK << DMA_LISR_STREAM0_SHIFT) +#define DMA_LISR_STREAM0_MASK (DMA_STREAM_MASK << DMA_LISR_STREAM0_SHIFT) #define DMA_LISR_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt status */ #define DMA_LISR_STREAM1_MASK (DMA_STREAM_MASK << DMA_LISR_STREAM1_SHIFT) #define DMA_LISR_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt status */ @@ -306,7 +300,7 @@ /* DMA interrupt flag clear register */ #define DMA_LICR_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt flag clear */ -#define DMA_LICR_STREAM1_MASK (DMA_STREAM_MASK << DMA_LICR_STREAM0_SHIFT) +#define DMA_LICR_STREAM0_MASK (DMA_STREAM_MASK << DMA_LICR_STREAM0_SHIFT) #define DMA_LICR_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt flag clear */ #define DMA_LICR_STREAM1_MASK (DMA_STREAM_MASK << DMA_LICR_STREAM1_SHIFT) #define DMA_LICR_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt flag clear */ @@ -372,7 +366,7 @@ # define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ #define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */ #define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT) -# DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) +# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) #define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) @@ -418,7 +412,7 @@ #define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) #define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) #define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) -#define DMAMAP_I2S2_EXT_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN3) +#define DMAMAP_I2S2_EXT_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN3) #define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) #define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) #define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) @@ -466,8 +460,8 @@ #define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) #define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) #define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) -#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) -#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) #define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1) #define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1) @@ -496,12 +490,12 @@ #define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5) #define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5) -#define DMAMAP_TIM1_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) #define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6) #define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6) #define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6) #define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM1_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) #define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) #define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6) #define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) @@ -515,4 +509,3 @@ #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_DMA_H */ - diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h index ee0ed7daa..9242ad027 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h @@ -108,7 +108,7 @@ #define GPIO_DCMI_D6_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN6) #define GPIO_DCMI_D7_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9) #define GPIO_DCMI_D7_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTE|GPIO_PIN6) -#define GPIO_DCMI_D7_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN7) +#define GPIO_DCMI_D7_3 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN7) #define GPIO_DCMI_D8_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN10) #define GPIO_DCMI_D8_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN1) #define GPIO_DCMI_D9_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTC|GPIO_PIN12) diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h index 6567aebf3..86a4436d5 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h @@ -179,7 +179,7 @@ # define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO_SHIFT) /* 01: LSE oscillator selected */ # define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO_SHIFT) /* 10: HSE oscillator clock selected */ # define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO_SHIFT) /* 11: PLL clock selected */ -#define TCC_CFGR_I2SSRC: (1 << 23) /* Bit 23: I2S clock selection */ +#define TCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */ #define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */ #define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT) # define RCC_CFGR_MCO1PRE_NONE (0 << RCC_CFGR_MCO1PRE_SHIFT) /* 0xx: no division */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h index c2a35e1ec..eea94b92f 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_rtc.h @@ -267,7 +267,7 @@ /* RTC write protection register */ -#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection ke +#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */ /* RTC sub second register */ @@ -293,7 +293,7 @@ #define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT) #define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ #define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) -#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation +#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ /* RTC timestamp sub second register */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h new file mode 100644 index 000000000..2bc949fec --- /dev/null +++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_vectors.h @@ -0,0 +1,129 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32f40xxx_vectors.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ + +/* This file is included by stm32_vectors.S. It provides the macro VECTOR that + * supplies ach STM32F40xxx vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f40xxx_irq.h. + * stm32_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper and time stamp interrupts */ +VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* Vector 16+3: RTC global interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */ +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1s0, STM32_IRQ_DMA1S0) /* Vector 16+11: DMA1 Stream 0 global interrupt */ +VECTOR(stm32_dma1s1, STM32_IRQ_DMA1S1) /* Vector 16+12: DMA1 Stream 1 global interrupt */ +VECTOR(stm32_dma1s2, STM32_IRQ_DMA1S2) /* Vector 16+13: DMA1 Stream 2 global interrupt */ +VECTOR(stm32_dma1s3, STM32_IRQ_DMA1S3) /* Vector 16+14: DMA1 Stream 3 global interrupt */ +VECTOR(stm32_dma1s4, STM32_IRQ_DMA1S4) /* Vector 16+15: DMA1 Stream 4 global interrupt */ +VECTOR(stm32_dma1s5, STM32_IRQ_DMA1S5) /* Vector 16+16: DMA1 Stream 5 global interrupt */ +VECTOR(stm32_dma1s6, STM32_IRQ_DMA1S6) /* Vector 16+17: DMA1 Stream 6 global interrupt */ +VECTOR(stm32_adc, STM32_IRQ_ADC) /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */ +VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* Vector 16+19: CAN1 TX interrupts */ +VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* Vector 16+20: CAN1 RX0 interrupts */ +VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* Vector 16+21: CAN1 RX1 interrupt */ +VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* Vector 16+22: CAN1 SCE interrupt */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */ +VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */ +VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */ +VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */ +VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */ +VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */ +VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */ +VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */ +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* Vector 16+41: RTC alarm through EXTI line interrupt */ +VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP) /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */ +VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* Vector 16+44: TIM8 Update interrup/TIM13 global interrupt */ +VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */ +VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* Vector 16+46: TIM8 Capture Compare interrupt */ +VECTOR(stm32_dma1s7, STM32_IRQ_DMA1S7) /* Vector 16+47: DMA1 Stream 7 global interrupt */ +VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */ +VECTOR(stm32_sdio, STM32_IRQ_SDIO) /* Vector 16+49: SDIO global interrupt */ +VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */ +VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */ +VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: UART4 global interrupt */ +VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: UART5 global interrupt */ +VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */ +VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */ +VECTOR(stm32_dma2s0, STM32_IRQ_DMA2S0) /* Vector 16+56: DMA2 Stream 0 global interrupt */ +VECTOR(stm32_dma2s1, STM32_IRQ_DMA2S1) /* Vector 16+57: DMA2 Stream 1 global interrupt */ +VECTOR(stm32_dma2s2, STM32_IRQ_DMA2S2) /* Vector 16+58: DMA2 Stream 2 global interrupt */ +VECTOR(stm32_dma2s3, STM32_IRQ_DMA2S3) /* Vector 16+59: DMA2 Stream 3 global interrupt */ +VECTOR(stm32_dma2s4, STM32_IRQ_DMA2S4) /* Vector 16+60: DMA2 Stream 4 global interrupt */ +VECTOR(stm32_eth, STM32_IRQ_ETH) /* Vector 16+61: Ethernet global interrupt */ +VECTOR(stm32_ethwkup, STM32_IRQ_ETHWKUP) /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */ +VECTOR(stm32_can2tx, STM32_IRQ_CAN2TX) /* Vector 16+63: CAN2 TX interrupts */ +VECTOR(stm32_can2rx0, STM32_IRQ_CAN2RX0) /* Vector 16+64: CAN2 RX0 interrupts */ +VECTOR(stm32_can2rx1, STM32_IRQ_CAN2RX1) /* Vector 16+65: CAN2 RX1 interrupt */ +VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE interrupt */ +VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */ +VECTOR(stm32_dma2s5, STM32_IRQ_DMA2S5) /* Vector 16+68: DMA2 Stream 5 global interrupt */ +VECTOR(stm32_dma2s6, STM32_IRQ_DMA2S6) /* Vector 16+69: DMA2 Stream 6 global interrupt */ +VECTOR(stm32_dma2s7, STM32_IRQ_DMA2S7) /* Vector 16+70: DMA2 Stream 7 global interrupt */ +VECTOR(stm32_usart6, STM32_IRQ_USART6) /* Vector 16+71: USART6 global interrupt */ +VECTOR(stm32_i2c3ev, STM32_IRQ_I2C3EV) /* Vector 16+72: I2C3 event interrupt */ +VECTOR(stm32_i2c3er, STM32_IRQ_I2C3ER) /* Vector 16+73: I2C3 error interrupt */ +VECTOR(stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT) /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */ +VECTOR(stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN) /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */ +VECTOR(stm32_otghswkup, STM32_IRQ_OTGHSWKUP) /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */ +VECTOR(stm32_otghs, STM32_IRQ_OTGHS ) /* Vector 16+77: USB On The Go HS global interrupt */ +VECTOR(stm32_dcmi, STM32_IRQ_DCMI) /* Vector 16+78: DCMI global interrupt */ +VECTOR(stm32_cryp, STM32_IRQ_CRYP) /* Vector 16+79: CRYP crypto global interrupt */ +VECTOR(stm32_hash, STM32_IRQ_HASH) /* Vector 16+80: Hash and Rng global interrupt */ +VECTOR(stm32_fpu, STM32_IRQ_FPU) /* Vector 16+81: FPU global interrupt */ + diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.h b/nuttx/arch/arm/src/stm32/stm32_gpio.h index 05a58da79..a93038ef0 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.h +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.h @@ -43,6 +43,12 @@ ************************************************************************************/ #include <nuttx/config.h> + +#ifndef __ASSEMBLY__ +# include <stdint.h> +# include <stdbool.h> +#endif + #include <nuttx/irq.h> #include "chip.h" @@ -231,10 +237,10 @@ extern "C" { #define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */ #define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -#define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ -#define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ -#define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ -#define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */ +# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */ +# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */ /* Input/output pull-ups/downs (not used with analog): * @@ -286,12 +292,12 @@ extern "C" { * .... .... FF.. .... .... */ -#define GPIO_MODE_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ -#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) -# define GPIO_MODE_2MHz (0 << GPIO_MODE_SHIFT) /* 2 MHz Low speed output */ -# define GPIO_MODE_25MHz (1 << GPIO_MODE_SHIFT) /* 25 MHz Medium speed output */ -# define GPIO_MODE_20MHz (2 << GPIO_MODE_SHIFT) /* 50 MHz Fast speed output */ -# define GPIO_MODE_100MHz (3 << GPIO_MODE_SHIFT) /* 100 MHz High speed output */ +#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */ +#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT) +# define GPIO_SPEED_2MHz (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */ +# define GPIO_SPEED_25MHz (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */ +# define GPIO_SPEED_20MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */ +# define GPIO_SPEED_100MHz (3 << GPIO_SPEED_SHIFT) /* 100 MHz High speed output */ /* Output/Alt function type selection: * diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.c b/nuttx/arch/arm/src/stm32/stm32_rcc.c index 553ca39a7..e95d437d1 100644 --- a/nuttx/arch/arm/src/stm32/stm32_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32_rcc.c @@ -74,411 +74,14 @@ * Private Functions ****************************************************************************/ -/* Put all RCC registers in reset state */ +/* Include chip-specific clocking initialization logic */ -static inline void rcc_reset(void) -{ - uint32_t regval; - - putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */ - putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */ - putreg32(RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */ - putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */ - putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */ - - regval = getreg32(STM32_RCC_CR); /* Set the HSION bit */ - regval |= RCC_CR_HSION; - putreg32(regval, STM32_RCC_CR); - - regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ - regval &= ~(RCC_CFGR_SW_MASK|RCC_CFGR_HPRE_MASK|RCC_CFGR_PPRE1_MASK|RCC_CFGR_PPRE2_MASK|RCC_CFGR_ADCPRE_MASK|RCC_CFGR_MCO_MASK); - putreg32(regval, STM32_RCC_CFGR); - - regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */ - regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON); - putreg32(regval, STM32_RCC_CR); - - regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */ - regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32_RCC_CR); - - regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ - regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK|RCC_CFGR_USBPRE); - putreg32(regval, STM32_RCC_CFGR); - - putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ -} - -static inline void rcc_enableahb(void) -{ - uint32_t regval; - - /* Always enable FLITF clock and SRAM clock */ - - regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN; - -#if CONFIG_STM32_DMA1 - /* DMA 1 clock enable */ - - regval |= RCC_AHBENR_DMA1EN; -#endif - -#if CONFIG_STM32_DMA2 - /* DMA 2 clock enable */ - - regval |= RCC_AHBENR_DMA2EN; -#endif - -#if CONFIG_STM32_CRC - /* CRC clock enable */ - - regval |= RCC_AHBENR_CRCEN; -#endif - -#if CONFIG_STM32_FSMC - /* FSMC clock enable */ - - regval |= RCC_AHBENR_FSMCEN; -#endif - -#if CONFIG_STM32_SDIO - /* SDIO clock enable */ - - regval |= RCC_AHBENR_SDIOEN; -#endif - - putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ -} - -static inline void rcc_enableapb1(void) -{ - uint32_t regval; - -#if CONFIG_STM32_USB - /* USB clock divider. This bit must be valid before enabling the USB - * clock in the RCC_APB1ENR register. This bit can’t be reset if the USB - * clock is enabled. - */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_USBPRE; - regval |= STM32_CFGR_USBPRE; - putreg32(regval, STM32_RCC_CFGR); -#endif - - /* Set the appropriate bits in the APB1ENR register to enabled the - * selected APB1 peripherals. - */ - - regval = getreg32(STM32_RCC_APB1ENR); -#if CONFIG_STM32_TIM2 - /* Timer 2 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_TIM2EN; -#endif -#endif - -#if CONFIG_STM32_TIM3 - /* Timer 3 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_TIM3EN; -#endif -#endif - -#if CONFIG_STM32_TIM4 - /* Timer 4 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_TIM4EN; -#endif -#endif - -#if CONFIG_STM32_TIM5 - /* Timer 5 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_TIM5EN; -#endif -#endif - -#if CONFIG_STM32_TIM6 - /* Timer 6 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_TIM6EN; -#endif -#endif - -#if CONFIG_STM32_TIM7 - /* Timer 7 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_TIM7EN; -#endif -#endif - -#if CONFIG_STM32_WWDG - /* Window Watchdog clock enable */ - - regval |= RCC_APB1ENR_WWDGEN; -#endif - -#if CONFIG_STM32_SPI2 - /* SPI 2 clock enable */ - - regval |= RCC_APB1ENR_SPI2EN; -#endif - -#if CONFIG_STM32_SPI3 - /* SPI 3 clock enable */ - - regval |= RCC_APB1ENR_SPI3EN; -#endif - -#if CONFIG_STM32_USART2 - /* USART 2 clock enable */ - - regval |= RCC_APB1ENR_USART2EN; -#endif - -#if CONFIG_STM32_USART3 - /* USART 3 clock enable */ - - regval |= RCC_APB1ENR_USART3EN; -#endif - -#if CONFIG_STM32_UART4 - /* UART 4 clock enable */ - - regval |= RCC_APB1ENR_UART4EN; -#endif - -#if CONFIG_STM32_UART5 - /* UART 5 clock enable */ - - regval |= RCC_APB1ENR_UART5EN; -#endif - -#if CONFIG_STM32_I2C1 - /* I2C 1 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_I2C1EN; -#endif -#endif - -#if CONFIG_STM32_I2C2 - /* I2C 2 clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB1ENR_I2C2EN; -#endif -#endif - -#if CONFIG_STM32_USB - /* USB clock enable */ - - regval |= RCC_APB1ENR_USBEN; -#endif - -#if CONFIG_STM32_CAN - /* CAN clock enable */ - - regval |= RCC_APB1ENR_CANEN; -#endif - -#if CONFIG_STM32_BKP - /* Backup interface clock enable */ - - regval |= RCC_APB1ENR_BKPEN; -#endif - -#if CONFIG_STM32_PWR - /* Power interface clock enable */ - - regval |= RCC_APB1ENR_PWREN; -#endif - -#if CONFIG_STM32_DAC - /* DAC interface clock enable */ - - regval |= RCC_APB1ENR_DACEN; -#endif - putreg32(regval, STM32_RCC_APB1ENR); -} - -static inline void rcc_enableapb2(void) -{ - uint32_t regval; - - /* Set the appropriate bits in the APB2ENR register to enabled the - * selected APB2 peripherals. - */ - - /* Enable GPIOA, GPIOB, ... and AFIO clocks */ - - regval = getreg32(STM32_RCC_APB2ENR); - regval |= (RCC_APB2ENR_AFIOEN -#if STM32_NGPIO > 0 - |RCC_APB2ENR_IOPAEN -#endif -#if STM32_NGPIO > 16 - |RCC_APB2ENR_IOPBEN -#endif -#if STM32_NGPIO > 32 - |RCC_APB2ENR_IOPCEN -#endif -#if STM32_NGPIO > 48 - |RCC_APB2ENR_IOPDEN -#endif -#if STM32_NGPIO > 64 - |RCC_APB2ENR_IOPEEN -#endif -#if STM32_NGPIO > 80 - |RCC_APB2ENR_IOPFEN -#endif -#if STM32_NGPIO > 96 - |RCC_APB2ENR_IOPGEN -#endif - ); - -#if CONFIG_STM32_ADC1 - /* ADC 1 interface clock enable */ - - regval |= RCC_APB2ENR_ADC1EN; -#endif - -#if CONFIG_STM32_ADC2 - /* ADC 2 interface clock enable */ - - regval |= RCC_APB2ENR_ADC2EN; -#endif - -#if CONFIG_STM32_TIM1 - /* TIM1 Timer clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB2ENR_TIM1EN; -#endif -#endif - -#if CONFIG_STM32_SPI1 - /* SPI 1 clock enable */ - - regval |= RCC_APB2ENR_SPI1EN; -#endif - -#if CONFIG_STM32_TIM8 - /* TIM8 Timer clock enable */ -#ifdef CONFIG_STM32_FORCEPOWER - regval |= RCC_APB2ENR_TIM8EN; -#endif -#endif - -#if CONFIG_STM32_USART1 - /* USART1 clock enable */ - - regval |= RCC_APB2ENR_USART1EN; -#endif - -#if CONFIG_STM32_ADC3 - /*ADC3 interface clock enable */ - - regval |= RCC_APB2ENR_ADC3EN; -#endif - putreg32(regval, STM32_RCC_APB2ENR); -} - -/* Called to change to new clock based on settings in board.h - * - * NOTE: This logic would need to be extended if you need to select low- - * power clocking modes! - */ - -#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -static inline void stm32_stdclockconfig(void) -{ - uint32_t regval; - volatile int32_t timeout; - - /* Enable External High-Speed Clock (HSE) */ - - regval = getreg32(STM32_RCC_CR); - regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ - regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32_RCC_CR); - - /* Wait until the HSE is ready (or until a timeout elapsed) */ - - for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) - { - /* Check if the HSERDY flag is the set in the CR */ - - if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) - { - /* If so, then break-out with timeout > 0 */ - - break; - } - } - - /* Check for a timeout. If this timeout occurs, then we are hosed. We - * have no real back-up plan, although the following logic makes it look - * as though we do. - */ - - if (timeout > 0) - { - /* Enable FLASH prefetch buffer and 2 wait states */ - - regval = getreg32(STM32_FLASH_ACR); - regval &= ~FLASH_ACR_LATENCY_MASK; - regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE); - putreg32(regval, STM32_FLASH_ACR); - - /* Set the HCLK source/divider */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32_RCC_CFGR_HPRE; - putreg32(regval, STM32_RCC_CFGR); - - /* Set the PCLK2 divider */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32_RCC_CFGR_PPRE2; - putreg32(regval, STM32_RCC_CFGR); - - /* Set the PCLK1 divider */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32_RCC_CFGR_PPRE1; - putreg32(regval, STM32_RCC_CFGR); - - /* Set the PLL divider and multipler */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK); - regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL); - putreg32(regval, STM32_RCC_CFGR); - - /* Enable the PLL */ - - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_PLLON; - putreg32(regval, STM32_RCC_CR); - - /* Wait until the PLL is ready */ - - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); - - /* Select the system clock source (probably the PLL) */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_SW_MASK; - regval |= STM32_SYSCLK_SW; - putreg32(regval, STM32_RCC_CFGR); - - /* Wait until the selected source is used as the system clock source */ - - while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); - } -} +#if defined(CONFIG_STM32_STM32F10XX) +# include "chip/stm32f10xxx_rcc.c" +#elif defined(CONFIG_STM32_STM32F40XX) +# include "chip/stm32f40xxx_rcc.c" +#else +# error "Unsupported STM32 chip" #endif /**************************************************************************** @@ -507,31 +110,5 @@ void stm32_clockconfig(void) /* Enable peripheral clocking */ - rcc_enableahb(); - rcc_enableapb2(); - rcc_enableapb1(); -} - -/* - * \todo Check for LSE good timeout and return with -1, - * possible ISR optimization? or at least ISR should be cough in case of failure - */ - -void stm32_rcc_enablelse(void) -{ - /* Enable LSE */ - - modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); - - /* We could wait for ISR here ... */ - - while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste(); - - /* Select LSE as RTC Clock Source */ - - modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); - - /* Enable Clock */ - - modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); + rcc_enableperipherals(); } diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S index 0c4722425..714244686 100644 --- a/nuttx/arch/arm/src/stm32/stm32_vectors.S +++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S @@ -39,8 +39,11 @@ ************************************************************************************/ #include <nuttx/config.h> + #include <arch/irq.h> +#include "chip.h" + /************************************************************************************ * Preprocessor Definitions ************************************************************************************/ @@ -128,220 +131,15 @@ stm32_vectors: /* External Interrupts */ +#undef VECTOR +#define VECTOR(l,i) .word l + #if defined(CONFIG_STM32_STM32F10XX) -# ifdef CONFIG_STM32_CONNECTIVITY_LINE - .word stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */ - .word stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */ - .word stm32_tamper /* Vector 16+2: Tamper interrupt */ - .word stm32_rtc /* Vector 16+3: RTC global interrupt */ - .word stm32_flash /* Vector 16+4: Flash global interrupt */ - .word stm32_rcc /* Vector 16+5: RCC global interrupt */ - .word stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */ - .word stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */ - .word stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */ - .word stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */ - .word stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */ - .word stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */ - .word stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */ - .word stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */ - .word stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */ - .word stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */ - .word stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 7 global interrupt */ - .word stm32_adc12 /* Vector 16+18: ADC1 and ADC2 global interrupt */ - .word stm32_can1tx /* Vector 16+19: CAN1 TX interrupts */ - .word stm32_can1rx0 /* Vector 16+20: CAN1 RX0 interrupts */ - .word stm32_can1rx /* Vector 16+21: CAN1 RX1 interrupt */ - .word stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */ - .word stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */ - .word stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt */ - .word stm32_tim1up /* Vector 16+25: TIM1 Update interrupt */ - .word stm32_tim1trgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts */ - .word stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */ - .word stm32_tim2 /* Vector 16+28: TIM2 global interrupt */ - .word stm32_tim3 /* Vector 16+29: TIM3 global interrupt */ - .word stm32_tim4 /* Vector 16+30: TIM4 global interrupt */ - .word stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */ - .word stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */ - .word stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */ - .word stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */ - .word stm32_spi1 /* Vector 16+35: SPI1 global interrupt */ - .word stm32_spi2 /* Vector 16+36: SPI2 global interrupt */ - .word stm32_usart1 /* Vector 16+37: USART1 global interrupt */ - .word stm32_usart2 /* Vector 16+38: USART2 global interrupt */ - .word stm32_usart3 /* Vector 16+39: USART3 global interrupt */ - .word stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */ - .word stm32_rtcalr /* Vector 16+41: RTC alarm through EXTI line interrupt */ - .word stm32_otgfswkup /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */ - .word stm32_reserved /* Vector 16+43: Reserved */ - .word stm32_reserved /* Vector 16+44: Reserved */ - .word stm32_reserved /* Vector 16+45: Reserved */ - .word stm32_reserved /* Vector 16+46: Reserved */ - .word stm32_reserved /* Vector 16+47: Reserved */ - .word stm32_reserved /* Vector 16+48: Reserved */ - .word stm32_reserved /* Vector 16+49: Reserved */ - .word stm32_tim5 /* Vector 16+50: TIM5 global interrupt */ - .word stm32_spi3 /* Vector 16+51: SPI3 global interrupt */ - .word stm32_uart4 /* Vector 16+52: UART4 global interrupt */ - .word stm32_uart5 /* Vector 16+53: UART5 global interrupt */ - .word stm32_tim6 /* Vector 16+54: TIM6 global interrupt */ - .word stm32_tim7 /* Vector 16+55: TIM7 global interrupt */ - .word stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */ - .word stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */ - .word stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */ - .word stm32_dma2ch4 /* Vector 16+59: DMA2 Channel 4 global interrupt */ - .word stm32_dma2ch5 /* Vector 16+60: DMA2 Channel 5 global interrupt */ - .word stm32_eth /* Vector 16+61: Ethernet global interrupt */ - .word stm32_ethwkup /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */ - .word stm32_can2tx /* Vector 16+63: CAN2 TX interrupts */ - .word stm32_can2rx0 /* Vector 16+64: CAN2 RX0 interrupts */ - .word stm32_can2rx1 /* Vector 16+65: CAN2 RX1 interrupt */ - .word stm32_can2sce /* Vector 16+66: CAN2 SCE interrupt */ - .word stm32_otgfs /* Vector 16+67: USB On The Go FS global interrupt */ -# else - .word stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */ - .word stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */ - .word stm32_tamper /* Vector 16+2: Tamper interrupt */ - .word stm32_rtc /* Vector 16+3: RTC global interrupt */ - .word stm32_flash /* Vector 16+4: Flash global interrupt */ - .word stm32_rcc /* Vector 16+5: RCC global interrupt */ - .word stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */ - .word stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */ - .word stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */ - .word stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */ - .word stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */ - .word stm32_dma1ch1 /* Vector 16+11: DMA1 Channel 1 global interrupt */ - .word stm32_dma1ch2 /* Vector 16+12: DMA1 Channel 2 global interrupt */ - .word stm32_dma1ch3 /* Vector 16+13: DMA1 Channel 3 global interrupt */ - .word stm32_dma1ch4 /* Vector 16+14: DMA1 Channel 4 global interrupt */ - .word stm32_dma1ch5 /* Vector 16+15: DMA1 Channel 5 global interrupt */ - .word stm32_dma1ch6 /* Vector 16+16: DMA1 Channel 6 global interrupt */ - .word stm32_dma1ch7 /* Vector 16+17: DMA1 Channel 7 global interrupt */ - .word stm32_adc12 /* Vector 16+18: ADC1 and ADC2 global interrupt */ - .word stm32_usbhpcantx /* Vector 16+19: USB High Priority or CAN TX interrupts*/ - .word stm32_usblpcanrx0 /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/ - .word stm32_can1rx1 /* Vector 16+21: CAN1 RX1 interrupt */ - .word stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */ - .word stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */ - .word stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt */ - .word stm32_tim1up /* Vector 16+25: TIM1 Update interrupt */ - .word stm32_tim1rtgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts */ - .word stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */ - .word stm32_tim2 /* Vector 16+28: TIM2 global interrupt */ - .word stm32_tim3 /* Vector 16+29: TIM3 global interrupt */ - .word stm32_tim4 /* Vector 16+30: TIM4 global interrupt */ - .word stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */ - .word stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */ - .word stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */ - .word stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */ - .word stm32_spi1 /* Vector 16+35: SPI1 global interrupt */ - .word stm32_spi2 /* Vector 16+36: SPI2 global interrupt */ - .word stm32_usart1 /* Vector 16+37: USART1 global interrupt */ - .word stm32_usart2 /* Vector 16+38: USART2 global interrupt */ - .word stm32_usart3 /* Vector 16+39: USART3 global interrupt */ - .word stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */ - .word stm32_rtcalr /* Vector 16+41: RTC alarm through EXTI line interrupt */ - .word stm32_usbwkup /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/ - .word stm32_tim8brk /* Vector 16+43: TIM8 Break interrupt */ - .word stm32_tim8up /* Vector 16+44: TIM8 Update interrupt */ - .word stm32_tim8trgcom /* Vector 16+45: TIM8 Trigger and Commutation interrupts */ - .word stm32_tim8cc /* Vector 16+46: TIM8 Capture Compare interrupt */ - .word stm32_adc3 /* Vector 16+47: ADC3 global interrupt */ - .word stm32_fsmc /* Vector 16+48: FSMC global interrupt */ - .word stm32_sdio /* Vector 16+49: SDIO global interrupt */ - .word stm32_tim5 /* Vector 16+50: TIM5 global interrupt */ - .word stm32_spi3 /* Vector 16+51: SPI3 global interrupt */ - .word stm32_uart4 /* Vector 16+52: UART4 global interrupt */ - .word stm32_uart5 /* Vector 16+53: UART5 global interrupt */ - .word stm32_tim6 /* Vector 16+54: TIM6 global interrupt */ - .word stm32_tim7 /* Vector 16+55: TIM7 global interrupt */ - .word stm32_dma2ch1 /* Vector 16+56: DMA2 Channel 1 global interrupt */ - .word stm32_dma2ch2 /* Vector 16+57: DMA2 Channel 2 global interrupt */ - .word stm32_dma2ch3 /* Vector 16+58: DMA2 Channel 3 global interrupt */ - .word stm32_dma2ch45 /* Vector 16+59: DMA2 Channel 4&5 global interrupt */ -# endif +# include "chip/chip/stm32f10xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) - .word stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */ - .word stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */ - .word stm32_tamper /* Vector 16+2: Tamper and time stamp interrupts */ - .word stm32_rtc_wkup /* Vector 16+3: RTC global interrupt */ - .word stm32_flash /* Vector 16+4: Flash global interrupt */ - .word stm32_rcc /* Vector 16+5: RCC global interrupt */ - .word stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */ - .word stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */ - .word stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */ - .word stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */ - .word stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */ - .word stm32_dma1s0 /* Vector 16+11: DMA1 Stream 0 global interrupt */ - .word stm32_dma1s1 /* Vector 16+12: DMA1 Stream 1 global interrupt */ - .word stm32_dma1s2 /* Vector 16+13: DMA1 Stream 2 global interrupt */ - .word stm32_dma1s3 /* Vector 16+14: DMA1 Stream 3 global interrupt */ - .word stm32_dma1s4 /* Vector 16+15: DMA1 Stream 4 global interrupt */ - .word stm32_dma1s5 /* Vector 16+16: DMA1 Stream 5 global interrupt */ - .word stm32_dma1s6 /* Vector 16+17: DMA1 Stream 6 global interrupt */ - .word stm32_adc /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */ - .word stm32_can1tx /* Vector 16+19: CAN1 TX interrupts */ - .word stm32_can1rx0 /* Vector 16+20: CAN1 RX0 interrupts */ - .word stm32_can1rx1 /* Vector 16+21: CAN1 RX1 interrupt */ - .word stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */ - .word stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */ - .word stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */ - .word stm32_tim1up /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */ - .word stm32_tim1trgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */ - .word stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */ - .word stm32_tim2 /* Vector 16+28: TIM2 global interrupt */ - .word stm32_tim3 /* Vector 16+29: TIM3 global interrupt */ - .word stm32_tim4 /* Vector 16+30: TIM4 global interrupt */ - .word stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */ - .word stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */ - .word stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */ - .word stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */ - .word stm32_spi1 /* Vector 16+35: SPI1 global interrupt */ - .word stm32_spi2 /* Vector 16+36: SPI2 global interrupt */ - .word stm32_usart1 /* Vector 16+37: USART1 global interrupt */ - .word stm32_usart2 /* Vector 16+38: USART2 global interrupt */ - .word stm32_usart3 /* Vector 16+39: USART3 global interrupt */ - .word stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */ - .word stm32_rtcalrm /* Vector 16+41: RTC alarm through EXTI line interrupt */ - .word stm32_otgfswkup /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */ - .word stm32_tim8brk /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */ - .word stm32_tim8up /* Vector 16+44: TIM8 Update interrup/TIM13 global interrupt */ - .word stm32_tim8trgcom /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */ - .word stm32_tim8cc /* Vector 16+46: TIM8 Capture Compare interrupt */ - .word stm32_dma1s7 /* Vector 16+47: DMA1 Stream 7 global interrupt */ - .word stm32_fsmc /* Vector 16+48: FSMC global interrupt */ - .word stm32_sdio /* Vector 16+49: SDIO global interrupt */ - .word stm32_tim5 /* Vector 16+50: TIM5 global interrupt */ - .word stm32_spi3 /* Vector 16+51: SPI3 global interrupt */ - .word stm32_uart4 /* Vector 16+52: UART4 global interrupt */ - .word stm32_uart5 /* Vector 16+53: UART5 global interrupt */ - .word stm32_tim6 /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */ - .word stm32_tim7 /* Vector 16+55: TIM7 global interrupt */ - .word stm32_dma2s0 /* Vector 16+56: DMA2 Stream 0 global interrupt */ - .word stm32_dma2s1 /* Vector 16+57: DMA2 Stream 1 global interrupt */ - .word stm32_dma2s2 /* Vector 16+58: DMA2 Stream 2 global interrupt */ - .word stm32_dma2s3 /* Vector 16+59: DMA2 Stream 3 global interrupt */ - .word stm32_dma2s4 /* Vector 16+60: DMA2 Stream 4 global interrupt */ - .word stm32_eth /* Vector 16+61: Ethernet global interrupt */ - .word stm32_ethwkup /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */ - .word stm32_can2tx /* Vector 16+63: CAN2 TX interrupts */ - .word stm32_can2rx0 /* Vector 16+64: CAN2 RX0 interrupts */ - .word stm32_can2rx1 /* Vector 16+65: CAN2 RX1 interrupt */ - .word stm32_can2sce /* Vector 16+66: CAN2 SCE interrupt */ - .word stm32_otgfs /* Vector 16+67: USB On The Go FS global interrupt */ - .word stm32_dma2s5 /* Vector 16+68: DMA2 Stream 5 global interrupt */ - .word stm32_dma2s6 /* Vector 16+69: DMA2 Stream 6 global interrupt */ - .word stm32_dma2s7 /* Vector 16+70: DMA2 Stream 7 global interrupt */ - .word stm32_usart6 /* Vector 16+71: USART6 global interrupt */ - .word stm32_i2c3ev /* Vector 16+72: I2C3 event interrupt */ - .word stm32_i2c3er /* Vector 16+73: I2C3 error interrupt */ - .word stm32_otghsep1out /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */ - .word stm32_otghsep1in /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */ - .word stm32_otghswkup /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */ - .word stm32_otghs /* Vector 16+77: USB On The Go HS global interrupt */ - .word stm32_dcmi /* Vector 16+78: DCMI global interrupt */ - .word stm32_cryp /* Vector 16+79: CRYP crypto global interrupt */ - .word stm32_hash /* Vector 16+80: Hash and Rng global interrupt */ - .word STM32_FPU /* Vector 16+81: FPU global interrupt */ +# include "chip/chip/stm32f40xxx_vectors.h" +#else +# error "No vectors for STM32 chip" #endif .size stm32_vectors, .-stm32_vectors @@ -364,213 +162,15 @@ handlers: HANDLER stm32_pendsv, STM32_IRQ_PENDSV /* Vector 14: Penable system service request */ HANDLER stm32_systick, STM32_IRQ_SYSTICK /* Vector 15: System tick */ +#undef VECTOR +#define VECTOR(l,i) HANDLER l, i + #if defined(CONFIG_STM32_STM32F10XX) -# ifdef CONFIG_STM32_CONNECTIVITY_LINE - HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */ - HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */ - HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */ - HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC global interrupt */ - HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */ - HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */ - HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */ - HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */ - HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */ - HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */ - HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */ - HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */ - HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */ - HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */ - HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */ - HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */ - HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 7 global interrupt */ - HANDLER stm32_adc12, STM32_IRQ_ADC12 /* Vector 16+18: ADC1 and ADC2 global interrupt */ - HANDLER stm32_can1tx, STM32_IRQ_CAN1TX /* Vector 16+19: CAN1 TX interrupts */ - HANDLER stm32_can1rx0, STM32_IRQ_CAN1RX0 /* Vector 16+20: CAN1 RX0 interrupts */ - HANDLER stm32_can1rx, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */ - HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */ - HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */ - HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt */ - HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt */ - HANDLER stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts */ - HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */ - HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */ - HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */ - HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */ - HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */ - HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */ - HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */ - HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */ - HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */ - HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */ - HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */ - HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */ - HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */ - HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */ - HANDLER stm32_rtcalr, STM32_IRQ_RTCALR /* Vector 16+41: RTC alarm through EXTI line interrupt */ - HANDLER stm32_otgfswkup, STM32_IRQ_OTGFSWKUP /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */ - HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */ - HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */ - HANDLER stm32_uart4 , STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */ - HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */ - HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */ - HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */ - HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */ - HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */ - HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */ - HANDLER stm32_dma2ch4, STM32_IRQ_DMA2CH4 /* Vector 16+59: DMA2 Channel 4 global interrupt */ - HANDLER stm32_dma2ch5, STM32_IRQ_DMA2CH5 /* Vector 16+60: DMA2 Channel 5 global interrupt */ - HANDLER stm32_eth, STM32_IRQ_ETH /* Vector 16+61: Ethernet global interrupt */ - HANDLER stm32_ethwkup, STM32_IRQ_ETHWKUP /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */ - HANDLER stm32_can2tx, STM32_IRQ_CAN2TX /* Vector 16+63: CAN2 TX interrupts */ - HANDLER stm32_can2rx0, STM32_IRQ_CAN2RX0 /* Vector 16+64: CAN2 RX0 interrupts */ - HANDLER stm32_can2rx1, STM32_IRQ_CAN2RX1 /* Vector 16+65: CAN2 RX1 interrupt */ - HANDLER stm32_can2sce, STM32_IRQ_CAN2SCE /* Vector 16+66: CAN2 SCE interrupt */ - HANDLER stm32_otgfs, STM32_IRQ_OTGFS /* Vector 16+67: USB On The Go FS global interrupt */ -# else - HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */ - HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */ - HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper interrupt */ - HANDLER stm32_rtc, STM32_IRQ_RTC /* Vector 16+3: RTC global interrupt */ - HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */ - HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */ - HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */ - HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */ - HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */ - HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */ - HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */ - HANDLER stm32_dma1ch1, STM32_IRQ_DMA1CH1 /* Vector 16+11: DMA1 Channel 1 global interrupt */ - HANDLER stm32_dma1ch2, STM32_IRQ_DMA1CH2 /* Vector 16+12: DMA1 Channel 2 global interrupt */ - HANDLER stm32_dma1ch3, STM32_IRQ_DMA1CH3 /* Vector 16+13: DMA1 Channel 3 global interrupt */ - HANDLER stm32_dma1ch4, STM32_IRQ_DMA1CH4 /* Vector 16+14: DMA1 Channel 4 global interrupt */ - HANDLER stm32_dma1ch5, STM32_IRQ_DMA1CH5 /* Vector 16+15: DMA1 Channel 5 global interrupt */ - HANDLER stm32_dma1ch6, STM32_IRQ_DMA1CH6 /* Vector 16+16: DMA1 Channel 6 global interrupt */ - HANDLER stm32_dma1ch7, STM32_IRQ_DMA1CH7 /* Vector 16+17: DMA1 Channel 7 global interrupt */ - HANDLER stm32_adc12, STM32_IRQ_ADC12 /* Vector 16+18: ADC1 and ADC2 global interrupt */ - HANDLER stm32_usbhpcantx, STM32_IRQ_USBHPCANTX /* Vector 16+19: USB High Priority or CAN TX interrupts*/ - HANDLER stm32_usblpcanrx0, STM32_IRQ_USBLPCANRX0 /* Vector 16+20: USB Low Priority or CAN RX0 interrupts*/ - HANDLER stm32_can1rx1, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */ - HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */ - HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */ - HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt */ - HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt */ - HANDLER stm32_tim1rtgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts */ - HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */ - HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */ - HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */ - HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */ - HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */ - HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */ - HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */ - HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */ - HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */ - HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */ - HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */ - HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */ - HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */ - HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */ - HANDLER stm32_rtcalr, STM32_IRQ_RTCALR /* Vector 16+41: RTC alarm through EXTI line interrupt */ - HANDLER stm32_usbwkup, STM32_IRQ_USBWKUP /* Vector 16+42: USB wakeup from suspend through EXTI line interrupt*/ - HANDLER stm32_tim8brk, STM32_IRQ_TIM8BRK /* Vector 16+43: TIM8 Break interrupt */ - HANDLER stm32_tim8up, STM32_IRQ_TIM8UP /* Vector 16+44: TIM8 Update interrupt */ - HANDLER stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM /* Vector 16+45: TIM8 Trigger and Commutation interrupts */ - HANDLER stm32_tim8cc, STM32_IRQ_TIM8CC /* Vector 16+46: TIM8 Capture Compare interrupt */ - HANDLER stm32_adc3, STM32_IRQ_ADC3 /* Vector 16+47: ADC3 global interrupt */ - HANDLER stm32_fsmc, STM32_IRQ_FSMC /* Vector 16+48: FSMC global interrupt */ - HANDLER stm32_sdio, STM32_IRQ_SDIO /* Vector 16+49: SDIO global interrupt */ - HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */ - HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */ - HANDLER stm32_uart4, STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */ - HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */ - HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt */ - HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */ - HANDLER stm32_dma2ch1, STM32_IRQ_DMA2CH1 /* Vector 16+56: DMA2 Channel 1 global interrupt */ - HANDLER stm32_dma2ch2, STM32_IRQ_DMA2CH2 /* Vector 16+57: DMA2 Channel 2 global interrupt */ - HANDLER stm32_dma2ch3, STM32_IRQ_DMA2CH3 /* Vector 16+58: DMA2 Channel 3 global interrupt */ - HANDLER stm32_dma2ch45, STM32_IRQ_DMA2CH45 /* Vector 16+59: DMA2 Channel 4&5 global interrupt */ -# endif +# include "chip/chip/stm32f10xxx_vectors.h" #elif defined(CONFIG_STM32_STM32F40XX) - HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */ - HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */ - HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper and time stamp interrupts */ - HANDLER stm32_rtc_wkup, STM32_IRQ_RTC_WKUP /* Vector 16+3: RTC global interrupt */ - HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */ - HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */ - HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */ - HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */ - HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */ - HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */ - HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */ - HANDLER stm32_dma1s0, STM32_IRQ_DMA1S0 /* Vector 16+11: DMA1 Stream 0 global interrupt */ - HANDLER stm32_dma1s1, STM32_IRQ_DMA1S1 /* Vector 16+12: DMA1 Stream 1 global interrupt */ - HANDLER stm32_dma1s2, STM32_IRQ_DMA1S2 /* Vector 16+13: DMA1 Stream 2 global interrupt */ - HANDLER stm32_dma1s3, STM32_IRQ_DMA1S3 /* Vector 16+14: DMA1 Stream 3 global interrupt */ - HANDLER stm32_dma1s4, STM32_IRQ_DMA1S4 /* Vector 16+15: DMA1 Stream 4 global interrupt */ - HANDLER stm32_dma1s5, STM32_IRQ_DMA1S5 /* Vector 16+16: DMA1 Stream 5 global interrupt */ - HANDLER stm32_dma1s6, STM32_IRQ_DMA1S6 /* Vector 16+17: DMA1 Stream 6 global interrupt */ - HANDLER stm32_adc, STM32_IRQ_ADC /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */ - HANDLER stm32_can1tx, STM32_IRQ_CAN1TX /* Vector 16+19: CAN1 TX interrupts */ - HANDLER stm32_can1rx0, STM32_IRQ_CAN1RX0 /* Vector 16+20: CAN1 RX0 interrupts */ - HANDLER stm32_can1rx1, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */ - HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */ - HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */ - HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */ - HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */ - HANDLER stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */ - HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */ - HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */ - HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */ - HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */ - HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */ - HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */ - HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */ - HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */ - HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */ - HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */ - HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */ - HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */ - HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */ - HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */ - HANDLER stm32_rtcalrm, STM32_IRQ_RTCALRM /* Vector 16+41: RTC alarm through EXTI line interrupt */ - HANDLER stm32_otgfswkup, STM32_IRQ_OTGFSWKUP /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */ - HANDLER stm32_tim8brk, STM32_IRQ_TIM8BRK /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */ - HANDLER stm32_tim8up, STM32_IRQ_TIM8UP /* Vector 16+44: TIM8 Update interrup/TIM13 global interrupt */ - HANDLER stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */ - HANDLER stm32_tim8cc, STM32_IRQ_TIM8CC /* Vector 16+46: TIM8 Capture Compare interrupt */ - HANDLER stm32_dma1s7, STM32_IRQ_DMA1S7 /* Vector 16+47: DMA1 Stream 7 global interrupt */ - HANDLER stm32_fsmc, STM32_IRQ_FSMC /* Vector 16+48: FSMC global interrupt */ - HANDLER stm32_sdio, STM32_IRQ_SDIO /* Vector 16+49: SDIO global interrupt */ - HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */ - HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */ - HANDLER stm32_uart4, STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */ - HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */ - HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */ - HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */ - HANDLER stm32_dma2s0, STM32_IRQ_DMA2S0 /* Vector 16+56: DMA2 Stream 0 global interrupt */ - HANDLER stm32_dma2s1, STM32_IRQ_DMA2S1 /* Vector 16+57: DMA2 Stream 1 global interrupt */ - HANDLER stm32_dma2s2, STM32_IRQ_DMA2S2 /* Vector 16+58: DMA2 Stream 2 global interrupt */ - HANDLER stm32_dma2s3, STM32_IRQ_DMA2S3 /* Vector 16+59: DMA2 Stream 3 global interrupt */ - HANDLER stm32_dma2s4, STM32_IRQ_DMA2S4 /* Vector 16+60: DMA2 Stream 4 global interrupt */ - HANDLER stm32_eth, STM32_IRQ_ETH /* Vector 16+61: Ethernet global interrupt */ - HANDLER stm32_ethwkup, STM32_IRQ_ETHWKUP /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */ - HANDLER stm32_can2tx, STM32_IRQ_CAN2TX /* Vector 16+63: CAN2 TX interrupts */ - HANDLER stm32_can2rx0, STM32_IRQ_CAN2RX0 /* Vector 16+64: CAN2 RX0 interrupts */ - HANDLER stm32_can2rx1, STM32_IRQ_CAN2RX1 /* Vector 16+65: CAN2 RX1 interrupt */ - HANDLER stm32_can2sce, STM32_IRQ_CAN2SCE /* Vector 16+66: CAN2 SCE interrupt */ - HANDLER stm32_otgfs, STM32_IRQ_OTGFS /* Vector 16+67: USB On The Go FS global interrupt */ - HANDLER stm32_dma2s5, STM32_IRQ_DMA2S5 /* Vector 16+68: DMA2 Stream 5 global interrupt */ - HANDLER stm32_dma2s6, STM32_IRQ_DMA2S6 /* Vector 16+69: DMA2 Stream 6 global interrupt */ - HANDLER stm32_dma2s7, STM32_IRQ_DMA2S7 /* Vector 16+70: DMA2 Stream 7 global interrupt */ - HANDLER stm32_usart6, STM32_IRQ_USART6 /* Vector 16+71: USART6 global interrupt */ - HANDLER stm32_i2c3ev, STM32_IRQ_I2C3EV /* Vector 16+72: I2C3 event interrupt */ - HANDLER stm32_i2c3er, STM32_IRQ_I2C3ER /* Vector 16+73: I2C3 error interrupt */ - HANDLER stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */ - HANDLER stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */ - HANDLER stm32_otghswkup, STM32_IRQ_OTGHSWKUP /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */ - HANDLER stm32_otghs, STM32_IRQ_OTGHS /* Vector 16+77: USB On The Go HS global interrupt */ - HANDLER stm32_dcmi, STM32_IRQ_DCMI /* Vector 16+78: DCMI global interrupt */ - HANDLER stm32_cryp, STM32_IRQ_CRYP /* Vector 16+79: CRYP crypto global interrupt */ - HANDLER stm32_hash, STM32_IRQ_HASH /* Vector 16+80: Hash and Rng global interrupt */ - HANDLER stm32_fpu, STM32_IRQ_FPU /* Vector 16+81: FPU global interrupt */ +# include "chip/chip/stm32f40xxx_vectors.h" +#else +# error "No handlers for STM32 chip" #endif /* Common IRQ handling logic. On entry here, the return stack is on either diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c new file mode 100644 index 000000000..f970b9668 --- /dev/null +++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c @@ -0,0 +1,541 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32f10xxx_rcc.c + * + * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Put all RCC registers in reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */ + putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */ + putreg32(RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */ + putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */ + putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */ + + regval = getreg32(STM32_RCC_CR); /* Set the HSION bit */ + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ + regval &= ~(RCC_CFGR_SW_MASK|RCC_CFGR_HPRE_MASK|RCC_CFGR_PPRE1_MASK|RCC_CFGR_PPRE2_MASK|RCC_CFGR_ADCPRE_MASK|RCC_CFGR_MCO_MASK); + putreg32(regval, STM32_RCC_CFGR); + + regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */ + regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON); + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */ + regval &= ~RCC_CR_HSEBYP; + putreg32(regval, STM32_RCC_CR); + + regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ + regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK|RCC_CFGR_USBPRE); + putreg32(regval, STM32_RCC_CFGR); + + putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ +} + +/**************************************************************************** + * Name: rcc_enableahb + * + * Description: + * Enable selected AHB peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb(void) +{ + uint32_t regval; + + /* Always enable FLITF clock and SRAM clock */ + + regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN; + +#if CONFIG_STM32_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHBENR_DMA1EN; +#endif + +#if CONFIG_STM32_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHBENR_DMA2EN; +#endif + +#if CONFIG_STM32_CRC + /* CRC clock enable */ + + regval |= RCC_AHBENR_CRCEN; +#endif + +#if CONFIG_STM32_FSMC + /* FSMC clock enable */ + + regval |= RCC_AHBENR_FSMCEN; +#endif + +#if CONFIG_STM32_SDIO + /* SDIO clock enable */ + + regval |= RCC_AHBENR_SDIOEN; +#endif + + putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + +#if CONFIG_STM32_USB + /* USB clock divider. This bit must be valid before enabling the USB + * clock in the RCC_APB1ENR register. This bit can’t be reset if the USB + * clock is enabled. + */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_USBPRE; + regval |= STM32_CFGR_USBPRE; + putreg32(regval, STM32_RCC_CFGR); +#endif + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); +#if CONFIG_STM32_TIM2 + /* Timer 2 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM2EN; +#endif +#endif + +#if CONFIG_STM32_TIM3 + /* Timer 3 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM3EN; +#endif +#endif + +#if CONFIG_STM32_TIM4 + /* Timer 4 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM4EN; +#endif +#endif + +#if CONFIG_STM32_TIM5 + /* Timer 5 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM5EN; +#endif +#endif + +#if CONFIG_STM32_TIM6 + /* Timer 6 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM6EN; +#endif +#endif + +#if CONFIG_STM32_TIM7 + /* Timer 7 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_TIM7EN; +#endif +#endif + +#if CONFIG_STM32_WWDG + /* Window Watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#if CONFIG_STM32_SPI2 + /* SPI 2 clock enable */ + + regval |= RCC_APB1ENR_SPI2EN; +#endif + +#if CONFIG_STM32_SPI3 + /* SPI 3 clock enable */ + + regval |= RCC_APB1ENR_SPI3EN; +#endif + +#if CONFIG_STM32_USART2 + /* USART 2 clock enable */ + + regval |= RCC_APB1ENR_USART2EN; +#endif + +#if CONFIG_STM32_USART3 + /* USART 3 clock enable */ + + regval |= RCC_APB1ENR_USART3EN; +#endif + +#if CONFIG_STM32_UART4 + /* UART 4 clock enable */ + + regval |= RCC_APB1ENR_UART4EN; +#endif + +#if CONFIG_STM32_UART5 + /* UART 5 clock enable */ + + regval |= RCC_APB1ENR_UART5EN; +#endif + +#if CONFIG_STM32_I2C1 + /* I2C 1 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_I2C1EN; +#endif +#endif + +#if CONFIG_STM32_I2C2 + /* I2C 2 clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB1ENR_I2C2EN; +#endif +#endif + +#if CONFIG_STM32_USB + /* USB clock enable */ + + regval |= RCC_APB1ENR_USBEN; +#endif + +#if CONFIG_STM32_CAN + /* CAN clock enable */ + + regval |= RCC_APB1ENR_CANEN; +#endif + +#if CONFIG_STM32_BKP + /* Backup interface clock enable */ + + regval |= RCC_APB1ENR_BKPEN; +#endif + +#if CONFIG_STM32_PWR + /* Power interface clock enable */ + + regval |= RCC_APB1ENR_PWREN; +#endif + +#if CONFIG_STM32_DAC + /* DAC interface clock enable */ + + regval |= RCC_APB1ENR_DACEN; +#endif + putreg32(regval, STM32_RCC_APB1ENR); +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + /* Enable GPIOA, GPIOB, ... and AFIO clocks */ + + regval = getreg32(STM32_RCC_APB2ENR); + regval |= (RCC_APB2ENR_AFIOEN +#if STM32_NGPIO > 0 + |RCC_APB2ENR_IOPAEN +#endif +#if STM32_NGPIO > 16 + |RCC_APB2ENR_IOPBEN +#endif +#if STM32_NGPIO > 32 + |RCC_APB2ENR_IOPCEN +#endif +#if STM32_NGPIO > 48 + |RCC_APB2ENR_IOPDEN +#endif +#if STM32_NGPIO > 64 + |RCC_APB2ENR_IOPEEN +#endif +#if STM32_NGPIO > 80 + |RCC_APB2ENR_IOPFEN +#endif +#if STM32_NGPIO > 96 + |RCC_APB2ENR_IOPGEN +#endif + ); + +#if CONFIG_STM32_ADC1 + /* ADC 1 interface clock enable */ + + regval |= RCC_APB2ENR_ADC1EN; +#endif + +#if CONFIG_STM32_ADC2 + /* ADC 2 interface clock enable */ + + regval |= RCC_APB2ENR_ADC2EN; +#endif + +#if CONFIG_STM32_TIM1 + /* TIM1 Timer clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM1EN; +#endif +#endif + +#if CONFIG_STM32_SPI1 + /* SPI 1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#if CONFIG_STM32_TIM8 + /* TIM8 Timer clock enable */ +#ifdef CONFIG_STM32_FORCEPOWER + regval |= RCC_APB2ENR_TIM8EN; +#endif +#endif + +#if CONFIG_STM32_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#if CONFIG_STM32_ADC3 + /*ADC3 interface clock enable */ + + regval |= RCC_APB2ENR_ADC3EN; +#endif + putreg32(regval, STM32_RCC_APB2ENR); +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static inline void stm32_stdclockconfig(void) +{ + uint32_t regval; + volatile int32_t timeout; + + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + + /* Check for a timeout. If this timeout occurs, then we are hosed. We + * have no real back-up plan, although the following logic makes it look + * as though we do. + */ + + if (timeout > 0) + { + /* Enable FLASH prefetch buffer and 2 wait states */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); + + /* Set the HCLK source/divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE2_MASK; + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PLL divider and multipler */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK); + regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL); + putreg32(regval, STM32_RCC_CFGR); + + /* Enable the PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLL is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); + + /* Select the system clock source (probably the PLL) */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= STM32_SYSCLK_SW; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the selected source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); + } +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb(); + rcc_enableapb2(); + rcc_enableapb1(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rcc_enablelse + * + * Todo: + * Check for LSE good timeout and return with -1, + * possible ISR optimization? or at least ISR should be cough in case of failure + * + ****************************************************************************/ + +void stm32_rcc_enablelse(void) +{ + /* Enable LSE */ + + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON); + + /* We could wait for ISR here ... */ + + while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste(); + + /* Select LSE as RTC Clock Source */ + + modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); + + /* Enable Clock */ + + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); +} diff --git a/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c new file mode 100644 index 000000000..004a0dfac --- /dev/null +++ b/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32f40xxx_rcc.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Put all RCC registers in reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: rcc_enableahb1 + * + * Description: + * Enable selected AHB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb1(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: rcc_enableahb2 + * + * Description: + * Enable selected AHB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb2(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: rcc_enableahb3 + * + * Description: + * Enable selected AHB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb3(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static inline void stm32_stdclockconfig(void) +{ +#warning "Missing logic" +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb1(); + rcc_enableahb2(); + rcc_enableahb3(); + rcc_enableapb1(); + rcc_enableapb2(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ |