diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-16 00:32:11 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-12-16 00:32:11 +0000 |
commit | df5aca04bdf127475b90bf6fdc246f402f039649 (patch) | |
tree | fa8d7ebc153e98273b925eb661c86da5c96e9519 | |
parent | fdaf3f62925632d5c98d019511acd22934653b0c (diff) | |
download | px4-nuttx-df5aca04bdf127475b90bf6fdc246f402f039649.tar.gz px4-nuttx-df5aca04bdf127475b90bf6fdc246f402f039649.tar.bz2 px4-nuttx-df5aca04bdf127475b90bf6fdc246f402f039649.zip |
Updated STM32 ADC driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4189 42af7a65-404d-4744-a932-0658087f49c3
-rw-r--r-- | apps/examples/README.txt | 6 | ||||
-rwxr-xr-x | apps/examples/adc/adc.h | 57 | ||||
-rw-r--r-- | apps/examples/adc/adc_main.c | 23 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_adc.c | 192 | ||||
-rw-r--r-- | nuttx/arch/arm/src/stm32/stm32_adc.h | 2 | ||||
-rw-r--r-- | nuttx/configs/stm3210e-eval/src/up_adc.c | 249 | ||||
-rw-r--r-- | nuttx/drivers/analog/adc.c | 341 |
7 files changed, 500 insertions, 370 deletions
diff --git a/apps/examples/README.txt b/apps/examples/README.txt index 63b0a0223..61166c438 100644 --- a/apps/examples/README.txt +++ b/apps/examples/README.txt @@ -44,8 +44,10 @@ examples/adc and this value is ignored. Otherwise, this number of samples is collected and the program terminates. Default: Samples are collected indefinitely. - - CONFIG_EXAMPLES_ADC_SAMPLESIZE - The number of bytes to read in one sample. - Default: 8 + - CONFIG_EXAMPLES_ADC_GROUPSIZE - The number of samples to read at once. + Default: 4 + - CONFIG_EXAMPLES_ADC_SAMPLEWIDTH - The width (in bits) of the on ADC sample. + Default: 16 examples/buttons ^^^^^^^^^^^^^^^^ diff --git a/apps/examples/adc/adc.h b/apps/examples/adc/adc.h index a8f225532..e6d9dd7bd 100755 --- a/apps/examples/adc/adc.h +++ b/apps/examples/adc/adc.h @@ -54,8 +54,10 @@ * and this value is ignored. Otherwise, this number of samples is * collected and the program terminates. Default: Samples are collected * indefinitely. - * CONFIG_EXAMPLES_ADC_SAMPLESIZE - The number of bytes to read in one sample. - * Default: 8 + * CONFIG_EXAMPLES_ADC_GROUPSIZE - The number of samples to read at once. + * Default: 4 + * CONFIG_EXAMPLES_ADC_SAMPLEWIDTH - The width (in bits) of the on ADC sample. + * Default: 16 */ #ifndef CONFIG_ADC @@ -66,10 +68,43 @@ # define CONFIG_EXAMPLES_ADC_DEVPATH "/dev/adc0" #endif -#ifndef CONFIG_EXAMPLES_ADC_SAMPLESIZE -# define CONFIG_EXAMPLES_ADC_SAMPLESIZE 8 +#ifndef CONFIG_EXAMPLES_ADC_GROUPSIZE +# define CONFIG_EXAMPLES_ADC_GROUPSIZE 4 #endif +#ifndef CONFIG_EXAMPLES_ADC_SAMPLEWIDTH +# define CONFIG_EXAMPLES_ADC_SAMPLEWIDTH 16 +#endif + +/* Sample characteristics ***************************************************/ + +#undef ADC_SAMPLE_BYTEWIDTH +#if CONFIG_EXAMPLES_ADC_SAMPLEWIDTH <= 8 +# undef CONFIG_EXAMPLES_ADC_SAMPLEWIDTH +# define CONFIG_EXAMPLES_ADC_SAMPLEWIDTH 8 +# define ADC_SAMPLE_BYTEWIDTH 1 +# define SAMPLE_FMT "%02x" +#elif CONFIG_EXAMPLES_ADC_SAMPLEWIDTH <= 16 +# undef CONFIG_EXAMPLES_ADC_SAMPLEWIDTH +# define CONFIG_EXAMPLES_ADC_SAMPLEWIDTH 16 +# define ADC_SAMPLE_BYTEWIDTH 2 +# define SAMPLE_FMT "%04x" +#elif CONFIG_EXAMPLES_ADC_SAMPLEWIDTH <= 24 +# undef CONFIG_EXAMPLES_ADC_SAMPLEWIDTH +# define CONFIG_EXAMPLES_ADC_SAMPLEWIDTH 24 +# define ADC_SAMPLE_BYTEWIDTH 3 +# define SAMPLE_FMT "%06x" +#elif CONFIG_EXAMPLES_ADC_SAMPLEWIDTH <= 32 +# undef CONFIG_EXAMPLES_ADC_SAMPLEWIDTH +# define CONFIG_EXAMPLES_ADC_SAMPLEWIDTH 32 +# define ADC_SAMPLE_BYTEWIDTH 4 +# define SAMPLE_FMT "%08x" +#else +# error "Unsupported sample width" +#endif + +#undef ADC_SAMPLE_SIZE (CONFIG_EXAMPLES_ADC_GROUPSIZE * ADC_SAMPLE_BYTEWIDTH) + /* Debug ********************************************************************/ #ifdef CONFIG_CPP_HAVE_VARARGS @@ -94,6 +129,18 @@ * Public Types ****************************************************************************/ +#if CONFIG_EXAMPLES_ADC_SAMPLEWIDTH == 8 +typedef uint8_t adc_sample_t; +#elif CONFIG_EXAMPLES_ADC_SAMPLEWIDTH == 16 +typedef uint16_t adc_sample_t; +#elif CONFIG_EXAMPLES_ADC_SAMPLEWIDTH == 24 +typedef uint32_t adc_sample_t; +#elif CONFIG_EXAMPLES_ADC_SAMPLEWIDTH == 32 +typedef uint32_t adc_sample_t; +#else +# error "Unsupported sample width" +#endif + /**************************************************************************** * Public Variables ****************************************************************************/ @@ -111,6 +158,6 @@ * ****************************************************************************/ -void adc_devinit(void); +int adc_devinit(void); #endif /* __APPS_EXAMPLES_ADC_ADC_H */ diff --git a/apps/examples/adc/adc_main.c b/apps/examples/adc/adc_main.c index 3a1a1be44..e85ee7653 100644 --- a/apps/examples/adc/adc_main.c +++ b/apps/examples/adc/adc_main.c @@ -94,8 +94,9 @@ int MAIN_NAME(int argc, char *argv[]) { - uintt_t sample[CONFIG_EXAMPLES_ADC_SAMPLESIZE]; + uint8_t sample[ADC_SAMPLE_SIZE]; ssize_t nbytes; + FAR adc_sample_t *ptr; #if defined(CONFIG_NSH_BUILTIN_APPS) || defined(CONFIG_EXAMPLES_ADC_NSAMPLES) long nsamples; #endif @@ -131,6 +132,7 @@ int MAIN_NAME(int argc, char *argv[]) errval = 1; goto errout; } + message(MAIN_STRING "Hardware initialized. Opening the ADC device\n"); /* Open the ADC device for reading */ @@ -147,6 +149,8 @@ int MAIN_NAME(int argc, char *argv[]) * ADC samples. */ + message(MAIN_STRING "Entering the main loop\n"); + #if defined(CONFIG_NSH_BUILTIN_APPS) for (; nsamples > 0; nsamples--) #elif defined(CONFIG_EXAMPLES_ADC_NSAMPLES) @@ -161,10 +165,10 @@ int MAIN_NAME(int argc, char *argv[]) msgflush(); - /* Read one sample */ + /* Read one sample of size ADC_SAMPLE_SIZE */ - nbytes = read(fd, sample,CONFIG_EXAMPLES_ADC_SAMPLESIZE )); - ivdbg("Bytes read: %d\n", nbytes); + nbytes = read(fd, sample, ADC_SAMPLE_SIZE); + message("Bytes read: %d\n", nbytes); /* Handle unexpected return values */ @@ -181,10 +185,10 @@ int MAIN_NAME(int argc, char *argv[]) message(MAIN_STRING "Interrupted read...\n"); } - else if (nbytes != CONFIG_EXAMPLES_ADC_SAMPLESIZE) + else if (nbytes != ADC_SAMPLE_SIZE) { message(MAIN_STRING "Unexpected read size=%d, expected=%d, Ignoring\n", - nbytes, CONFIG_EXAMPLES_ADC_SAMPLESIZE); + nbytes, ADC_SAMPLE_SIZE); } /* Print the sample data on successful return */ @@ -192,16 +196,17 @@ int MAIN_NAME(int argc, char *argv[]) else { message("Sample :\n"); - for (i = 0; i < CONFIG_EXAMPLES_ADC_SAMPLESIZE; i++) + ptr = (FAR adc_sample_t*)sample; + for (i = 0; i < CONFIG_EXAMPLES_ADC_GROUPSIZE; i++) { - message("%d: %02x\n", i, sample[i]); + message("%d: " SAMPLE_FMT "\n", i, ptr[i]); } } } errout_with_dev: close(fd); -errout_with_dev: + errout: message("Terminating!\n"); msgflush(); diff --git a/nuttx/arch/arm/src/stm32/stm32_adc.c b/nuttx/arch/arm/src/stm32/stm32_adc.c index 88f117b6e..5903158db 100644 --- a/nuttx/arch/arm/src/stm32/stm32_adc.c +++ b/nuttx/arch/arm/src/stm32/stm32_adc.c @@ -44,6 +44,7 @@ #include <sys/types.h> #include <stdint.h> #include <stdbool.h> +#include <string.h> #include <semaphore.h> #include <errno.h> #include <assert.h> @@ -115,8 +116,6 @@ struct stm32_dev_s uint32_t base; /* Base address of registers unique to this ADC block */ uint8_t chanlist[ADC_MAX_SAMPLES]; - int32_t buf[8]; - uint8_t count[8]; }; /**************************************************************************** @@ -127,11 +126,11 @@ struct stm32_dev_s static uint32_t adc_getreg(struct stm32_dev_s *priv, int offset); static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value); -static void adc_rccreset(int regaddr, bool reset); +static void adc_rccreset(struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -static int adc_interrupt(FAR struct stm32_dev_s *priv); +static int adc_interrupt(FAR struct adc_dev_s *dev); #if defined(CONFIG_STM32_STM32F10XX) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) static int adc12_interrupt(int irq, void *context); #endif @@ -178,7 +177,7 @@ static struct stm32_dev_s g_adcpriv1 = .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, #endif - .intf = 1; + .intf = 1, .base = STM32_ADC1_BASE, }; @@ -362,11 +361,14 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) * Returned Value: * *******************************************************************************/ + static void adc_enable(FAR struct adc_dev_s *dev, bool enable) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; uint32_t regval; + avdbg("enable: %d\n", enable); + regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); if (enable) { @@ -394,16 +396,13 @@ static void adc_enable(FAR struct adc_dev_s *dev, bool enable) static void adc_reset(FAR struct adc_dev_s *dev) { - adbg("Initializing the ADC to the reset values \n"); - FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; irqstate_t flags; uint32_t regval; - uint32_t L = priv->nchannels; - uint32_t ch; int offset; int i; - + + avdbg("intf: %d\n", priv->intf); flags = irqsave(); /* Enable ADC reset state */ @@ -435,22 +434,22 @@ static void adc_reset(FAR struct adc_dev_s *dev) putreg32(regval,STM32_ADC_CCR_OFFSET); #endif - /* Initialize the same sample time for each ADC 1.5 cycles + /* Initialize the same sample time for each ADC 55.5 cycles * * During sample cycles channel selection bits must remain unchanged. * - * 000: 1.5 cycles - * 001: 7.5 cycles - * 010: 13.5 cycles - * 011: 28.5 cycles - * 100: 41.5 cycles - * 101: 55.5 cycles - * 110: 71.5 cycles - * 111: 239.5 cycles + * 000: 1.5 cycles + * 001: 7.5 cycles + * 010: 13.5 cycles + * 011: 28.5 cycles + * 100: 41.5 cycles + * 101: 55.5 cycles + * 110: 71.5 cycles + * 111: 239.5 cycles */ - adc_putreg(priv,STM32_ADC_SMPR1_OFFSET,0x00000000); - adc_putreg(priv,STM32_ADC_SMPR2_OFFSET,0x00000000); + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, 0x00b6db6d); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, 0x00b6db6d); /* ADC CR1 Configuration */ @@ -467,8 +466,25 @@ static void adc_reset(FAR struct adc_dev_s *dev) /* Initialize the ADC_CR1_SCAN member DISABLE */ regval &= ~ADC_CR1_SCAN; + + /* Initialize the Analog watchdog enable */ + + regval |= ADC_CR1_AWDEN; + + /* AWDIE: Analog watchdog interrupt enable */ + + regval |= ADC_CR1_AWDIE; + + /* EOCIE: Interrupt enable for EOC */ + + regval |= ADC_CR1_EOCIE; + adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval); +#warning "Only one channel is able to be guarded for the watchdog" +#warning "The channel is configured in the ADC_CR1_AWDCH [4:0]" +#warning "We have to decide if we need this watchdog " + /* ADC1 CR2 Configuration */ /* Set the ADON bit to wake up the ADC from power down mode */ @@ -476,62 +492,55 @@ static void adc_reset(FAR struct adc_dev_s *dev) regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); regval |= ADC_CR2_ADON; - /* Clear CONT, ALIGN and EXTTRIG bits */ + /* Clear CONT, ALIGN (Right = 0) and EXTTRIG bits */ - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); regval &= ~ADC_CR2_CONT; regval &= ~ADC_CR2_ALIGN; regval &= ~ADC_CR2_EXTSEL_MASK; - adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); - - /* Set CONT, ALIGN and EXTTRIG bits */ - /* Initialize the ALIGN: Data alignment Right */ - - regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); - regval &= ~ADC_CR2_ALIGN; - - /* Initialize the External event select "Timer CC1 event" */ - - regval &= ~ADC_CR2_EXTSEL_MASK; - - /* Initialize the ADC_ContinuousConvMode "Single conversion mode" */ + + /* SWSTART: Start conversion of regular channels */ - regval &= ~ADC_CR2_CONT; +#warning "Don't you want to finish setting up the registers before starting the conversion?" + regval |= ADC_CR2_SWSTART; adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); + + /* Configuration of the channel conversions */ - /* ADC1 SQR Configuration */ - - L = L << 20; - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET); - regval &= ~ADC_SQR1_L_MASK; /* Clear L Mask */ - regval |= L; /* SetL, # of conversions */ - adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval); - - /* Configuration of the channels conversions */ - - regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ~ADC_SQR3_RESERVED; + regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; for (i = 0, offset = 0; i < priv->nchannels && i < 6; i++, offset += 5) { regval |= (uint32_t)priv->chanlist[i] << offset; } adc_putreg(priv, STM32_ADC_SQR3_OFFSET, regval); - - regval = adc_getreg(priv, STM32_ADC_SQR2_OFFSET) & ~ADC_SQR2_RESERVED; + + regval = adc_getreg(priv, STM32_ADC_SQR2_OFFSET) & ADC_SQR2_RESERVED; for (i = 6, offset = 0; i < priv->nchannels && i < 12; i++, offset += 5) { regval |= (uint32_t)priv->chanlist[i] << offset; } adc_putreg(priv, STM32_ADC_SQR2_OFFSET, regval); - regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ~(ADC_SQR1_RESERVED|ADC_SQR1_L_MASK); + regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; for (i = 12, offset = 0; i < priv->nchannels && i < 16; i++, offset += 5) { regval |= (uint32_t)priv->chanlist[i] << offset; } - adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval); + + /* Set the number of conversions */ DEBUGASSERT(priv->nchannels <= 16); + + regval |= ((uint32_t)priv->nchannels << ADC_SQR1_L_SHIFT); + adc_putreg(priv, STM32_ADC_SQR1_OFFSET, regval); irqrestore(flags); + + avdbg("CR1: 0x%08x CR2: 0x%08x\n", + adc_getreg(priv, STM32_ADC_CR1_OFFSET), + adc_getreg(priv, STM32_ADC_CR2_OFFSET)) + avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", + adc_getreg(priv, STM32_ADC_SQR1_OFFSET), + adc_getreg(priv, STM32_ADC_SQR2_OFFSET), + adc_getreg(priv, STM32_ADC_SQR3_OFFSET)) } /**************************************************************************** @@ -553,18 +562,14 @@ static int adc_setup(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int ret; - int i; + + avdbg("intf: %d\n", priv->intf); + /* Attach the ADC interrupt */ ret = irq_attach(priv->irq, priv->isr); if (ret == OK) { - for (i = 0; i < 8; i++) - { - priv->buf[i] = 0; - priv->count[i] = 0; - } - /* Enable the ADC interrupt */ up_enable_irq(priv->irq); @@ -590,6 +595,8 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + avdbg("intf: %d\n", priv->intf); + /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -615,6 +622,8 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; uint32_t regval; + avdbg("intf: %d enable: %d\n", priv->intf, enable); + regval = adc_getreg(priv, STM32_ADC_CR1_OFFSET); if (enable) { @@ -624,7 +633,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) } else { - /* Enable all ADC interrupts */ + /* Disable all ADC interrupts */ regval &= ~ADC_CR1_ALLINTS; } @@ -645,6 +654,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) { + avdbg("intf: %d\n", priv->intf); return -ENOTTY; } @@ -660,13 +670,16 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -static int adc_interrupt(FAR struct stm32_dev_s *priv) +static int adc_interrupt(FAR struct adc_dev_s *dev) { + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; uint32_t adcsr; int32_t value; uint8_t ch; int i; + avdbg("intf: %d\n", priv->intf); + /* Identifies the interruption AWD or EOC */ adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET); @@ -679,16 +692,27 @@ static int adc_interrupt(FAR struct stm32_dev_s *priv) if ((adcsr & ADC_SR_EOC) != 0) { - value = adc_getreg(priv, STM32_ADC_DR_OFFSET); - value &= ADC_DR_DATA_MASK; -#error "i is not assigned a value" - ch = priv->chanlist[i]; /* Channel converted */ - - /* Handle the ADC interrupt */ + /* Call adc_receive for each channel that completed */ + +# warning "Does the DR register need to be read numerous times? Once for each channel?" +# warning "I don't know how this is supposed to work, but I will add some guesses here -- please fix" - adc_receive(priv, ch, value); - priv->buf[ch] = 0; - priv->count[ch] = 0; + for (i = 0; i < priv->nchannels; i++) + { + /* Read the converted value */ + + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); + value &= ADC_DR_DATA_MASK; + + /* Give the ADC data to the ADC dirver. adc_receive accepts 3 parameters: + * + * 1) The first is the ADC device instance for this ADC block. + * 2) The second is the channel number for the data, and + * 3) The third is the converted data for the channel. + */ + + adc_receive(dev, i, value); + } } return OK; @@ -712,6 +736,8 @@ static int adc12_interrupt(int irq, void *context) uint32_t regval; uint32_t pending; + avdbg("irq: %d\n"); + /* Check for pending ADC1 interrupts */ #ifdef CONFIG_STM32_ADC1 @@ -719,7 +745,7 @@ static int adc12_interrupt(int irq, void *context) pending = regval & ADC_SR_ALLINTS; if (pending != 0) { - adc_interrupt(&g_adcpriv1); + adc_interrupt(&g_adcdev1); regval &= ~pending; putreg32(regval, STM32_ADC1_SR); } @@ -732,7 +758,7 @@ static int adc12_interrupt(int irq, void *context) pending = regval & ADC_SR_ALLINTS; if (pending != 0) { - adc_interrupt(&g_adcpriv2); + adc_interrupt(&g_adcdev2); regval &= ~pending; putreg32(regval, STM32_ADC2_SR); } @@ -759,13 +785,15 @@ static int adc3_interrupt(int irq, void *context) uint32_t regval; uint32_t pending; + avdbg("irq: %d\n"); + /* Check for pending ADC3 interrupts */ regval = getreg32(STM32_ADC3_SR); pending = regval & ADC_SR_ALLINTS; if (pending != 0) { - adc_interrupt(&g_adcpriv3); + adc_interrupt(&g_adcdev3); regval &= ~pending; putreg32(regval, STM32_ADC3_SR); } @@ -792,6 +820,8 @@ static int adc123_interrupt(int irq, void *context) uint32_t regval; uint32_t pending; + avdbg("irq: %d\n"); + /* Check for pending ADC1 interrupts */ #ifdef CONFIG_STM32_ADC1 @@ -799,7 +829,7 @@ static int adc123_interrupt(int irq, void *context) pending = regval & ADC_SR_ALLINTS; if (pending != 0) { - adc_interrupt(&g_adcpriv1); + adc_interrupt(&g_adcdev1); regval &= ~pending; putreg32(regval, STM32_ADC1_SR); } @@ -812,7 +842,7 @@ static int adc123_interrupt(int irq, void *context) pending = regval & ADC_SR_ALLINTS; if (pending != 0) { - adc_interrupt(&g_adcpriv2); + adc_interrupt(&g_adcdev2); regval &= ~pending; putreg32(regval, STM32_ADC2_SR); } @@ -825,7 +855,7 @@ static int adc123_interrupt(int irq, void *context) pending = regval & ADC_SR_ALLINTS; if (pending != 0) { - adc_interrupt(&g_adcpriv3); + adc_interrupt(&g_adcdev3); regval &= ~pending; putreg32(regval, STM32_ADC3_SR); } @@ -868,15 +898,17 @@ static int adc123_interrupt(int irq, void *context) * ****************************************************************************/ -struct adc_dev_s *stm32_adcinitialize(int intf, uint8_t *chanlist, int nchannels) +struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nchannels) { FAR struct adc_dev_s *dev; FAR struct stm32_dev_s *priv; + avdbg("intf: %d nchannels: %d\n", intf, nchannels); + #ifdef CONFIG_STM32_ADC1 if (intf == 1) { - adbg("ADC1 Selected \n"); + adbg("ADC1 Selected\n"); dev = &g_adcdev1; } else @@ -884,7 +916,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, uint8_t *chanlist, int nchannels #ifdef CONFIG_STM32_ADC2 if (intf == 2) { - adbg("ADC2 Selected \n"); + adbg("ADC2 Selected\n"); dev = &g_adcdev2; } else @@ -892,7 +924,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, uint8_t *chanlist, int nchannels #ifdef CONFIG_STM32_ADC3 if (intf == 3) { - adbg("ADC3 Selected \n"); + adbg("ADC3 Selected\n"); dev = &g_adcdev3; } else diff --git a/nuttx/arch/arm/src/stm32/stm32_adc.h b/nuttx/arch/arm/src/stm32/stm32_adc.h index 508813bd1..eb5926f28 100644 --- a/nuttx/arch/arm/src/stm32/stm32_adc.h +++ b/nuttx/arch/arm/src/stm32/stm32_adc.h @@ -76,7 +76,7 @@ extern "C" { ****************************************************************************/ struct adc_dev_s; -EXTERN struct adc_dev_s *stm32_adcinitialize(int intf, uint8_t *chanlist, +EXTERN struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN diff --git a/nuttx/configs/stm3210e-eval/src/up_adc.c b/nuttx/configs/stm3210e-eval/src/up_adc.c index c2a0d2cfe..92e21a8e5 100644 --- a/nuttx/configs/stm3210e-eval/src/up_adc.c +++ b/nuttx/configs/stm3210e-eval/src/up_adc.c @@ -1,111 +1,140 @@ -/************************************************************************************
- * configs/stm3210e-eval/src/up_adc.c
- * arch/arm/src/board/up_adc.c
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <debug.h>
-
-#include <nuttx/analog/adc.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
-#include "up_arch.h"
-#include "stm3210e-internal.h"
-
-#ifdef CONFIG_ADC
-
-/************************************************************************************
- * Definitions
- ************************************************************************************/
-
-/* Configuration ************************************************************/
-/* Up to 3 ADC interfaces are supported */
-
-#if STM32_NADC < 3
-# undef CONFIG_STM32_ADC3
-#endif
-
-#if STM32_NADC < 2
-# undef CONFIG_STM32_ADC2
-#endif
-
-#if STM32_NADC < 1
-# undef CONFIG_STM32_ADC1
-#endif
-
-#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3)
-
-/************************************************************************************
- * Private Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_boardinitialize
- *
- * Description:
- * All STM32 architectures must provide the following entry point. This entry point
- * is called early in the intitialization -- after all memory has been configured
- * and mapped but before any devices have been initialized.
- *
- ************************************************************************************/
-
-void adc_devinit(void)
-{
- struct adc_dev_s *adc;
- int ret;
-
- /* Call stm32_adcinitialize() to get an instance of the ADC interface */
-#warning "Missing Logic"
-
- /* Register the ADC driver at "/dev/adc0" */
-
- ret = adc_register("/dev/adc0", adc);
- if (ret < 0)
- {
- adbg("adc_register failed: %d\n", ret);
- }
-}
-
-#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */
+/************************************************************************************ + * configs/stm3210e-eval/src/up_adc.c + * arch/arm/src/board/up_adc.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include <nuttx/analog/adc.h> +#include <arch/board/board.h> + +#include "chip.h" +#include "up_arch.h" +#include "stm3210e-internal.h" + +#ifdef CONFIG_ADC + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* Configuration ************************************************************/ +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) + +/* The number of ADC channels in the conversion list */ + +#define ADC_NCHANNELS 2 + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist[ADC_NCHANNELS] = {14, 10}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC_NCHANNELS] = {GPIO_ADC1_IN14 , GPIO_ADC1_IN10}; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +int adc_devinit(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + avdbg("Entry\n"); + + /* Configure the pins as analog inputs for the selected channels */^M + + for(i = 0; i < ADC_NCHANNELS; i++) + { + stm32_configgpio(chanlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */^M + + adc = stm32_adcinitialize(1, g_chanlist, ADC_NCHANNELS); + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + adbg("adc_register failed: %d\n", ret); + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */
\ No newline at end of file diff --git a/nuttx/drivers/analog/adc.c b/nuttx/drivers/analog/adc.c index bf3d7bdf6..ab374f973 100644 --- a/nuttx/drivers/analog/adc.c +++ b/nuttx/drivers/analog/adc.c @@ -77,14 +77,14 @@ static int adc_ioctl(FAR struct file *filep,int cmd,unsigned long arg); static const struct file_operations adc_fops = { - adc_open, /* open */ - adc_close, /* close */ - adc_read, /* read */ - adc_write, /* write */ - 0, /* seek */ - adc_ioctl /* ioctl */ + adc_open, /* open */ + adc_close, /* close */ + adc_read, /* read */ + adc_write, /* write */ + 0, /* seek */ + adc_ioctl /* ioctl */ #ifndef CONFIG_DISABLE_POLL - , 0 /* poll */ + , 0 /* poll */ #endif }; @@ -101,62 +101,62 @@ static const struct file_operations adc_fops = static int adc_open(FAR struct file *filep) { - FAR struct inode *inode = filep->f_inode; - FAR struct adc_dev_s *dev = inode->i_private; - uint8_t tmp; - int ret = OK; + FAR struct inode *inode = filep->f_inode; + FAR struct adc_dev_s *dev = inode->i_private; + uint8_t tmp; + int ret = OK; - /* If the port is the middle of closing, wait until the close is finished */ + /* If the port is the middle of closing, wait until the close is finished */ - if (sem_wait(&dev->ad_closesem) != OK) + if (sem_wait(&dev->ad_closesem) != OK) { - ret = -errno; + ret = -errno; } - else + else { - /* Increment the count of references to the device. If this the first - * time that the driver has been opened for this device, then initialize - * the device. - */ + /* Increment the count of references to the device. If this the first + * time that the driver has been opened for this device, then initialize + * the device. + */ - tmp = dev->ad_ocount + 1; - if (tmp == 0) + tmp = dev->ad_ocount + 1; + if (tmp == 0) { - /* More than 255 opens; uint8_t overflows to zero */ + /* More than 255 opens; uint8_t overflows to zero */ - ret = -EMFILE; + ret = -EMFILE; } - else + else { - /* Check if this is the first time that the driver has been opened. */ + /* Check if this is the first time that the driver has been opened. */ - if (tmp == 1) + if (tmp == 1) { - /* Yes.. perform one time hardware initialization. */ + /* Yes.. perform one time hardware initialization. */ - irqstate_t flags = irqsave(); - ret = dev->ad_ops->ao_setup(dev); - if (ret == OK) + irqstate_t flags = irqsave(); + ret = dev->ad_ops->ao_setup(dev); + if (ret == OK) { - /* Mark the FIFOs empty */ + /* Mark the FIFOs empty */ - dev->ad_recv.af_head = 0; - dev->ad_recv.af_tail = 0; + dev->ad_recv.af_head = 0; + dev->ad_recv.af_tail = 0; - /* Finally, Enable the CAN RX interrupt */ + /* Finally, Enable the CAN RX interrupt */ - dev->ad_ops->ao_rxint(dev, true); + dev->ad_ops->ao_rxint(dev, true); - /* Save the new open count on success */ + /* Save the new open count on success */ - dev->ad_ocount = tmp; + dev->ad_ocount = tmp; } - irqrestore(flags); + irqrestore(flags); } } - sem_post(&dev->ad_closesem); + sem_post(&dev->ad_closesem); } - return ret; + return ret; } /************************************************************************************ @@ -170,43 +170,42 @@ static int adc_open(FAR struct file *filep) static int adc_close(FAR struct file *filep) { - FAR struct inode *inode = filep->f_inode; - FAR struct adc_dev_s *dev = inode->i_private; - irqstate_t flags; - int ret = OK; + FAR struct inode *inode = filep->f_inode; + FAR struct adc_dev_s *dev = inode->i_private; + irqstate_t flags; + int ret = OK; - if (sem_wait(&dev->ad_closesem) != OK) + if (sem_wait(&dev->ad_closesem) != OK) { - ret = -errno; + ret = -errno; } - else + else { - /* Decrement the references to the driver. If the reference count will - * decrement to 0, then uninitialize the driver. - */ + /* Decrement the references to the driver. If the reference count will + * decrement to 0, then uninitialize the driver. + */ - if (dev->ad_ocount > 1) + if (dev->ad_ocount > 1) { - dev->ad_ocount--; - sem_post(&dev->ad_closesem); + dev->ad_ocount--; + sem_post(&dev->ad_closesem); } - else + else { - /* There are no more references to the port */ + /* There are no more references to the port */ - dev->ad_ocount = 0; + dev->ad_ocount = 0; + /* Free the IRQ and disable the ADC device */ - /* Free the IRQ and disable the ADC device */ + flags = irqsave(); /* Disable interrupts */ + dev->ad_ops->ao_shutdown(dev); /* Disable the ADC */ + irqrestore(flags); - flags = irqsave(); /* Disable interrupts */ - dev->ad_ops->ao_shutdown(dev); /* Disable the ADC */ - irqrestore(flags); - - sem_post(&dev->ad_closesem); + sem_post(&dev->ad_closesem); } } - return ret; + return ret; } /**************************************************************************** @@ -215,115 +214,129 @@ static int adc_close(FAR struct file *filep) static ssize_t adc_read(FAR struct file *filep, FAR char *buffer, size_t buflen) { - FAR struct inode *inode = filep->f_inode; - FAR struct adc_dev_s *dev = inode->i_private; - size_t nread; - irqstate_t flags; - int ret = 0; - int msglen; - - if (buflen % 5 ==0 ) - msglen=5; - else if (buflen % 4 ==0 ) - msglen=4; - else if (buflen % 3 ==0 ) - msglen=3; - else if (buflen % 2 ==0 ) - msglen=2; - else if (buflen == 1) - msglen=1; - else - msglen=5; - - if (buflen >= msglen) + FAR struct inode *inode = filep->f_inode; + FAR struct adc_dev_s *dev = inode->i_private; + size_t nread; + irqstate_t flags; + int ret = 0; + int msglen; + + avdbg("buflen: %d\n", (int)buflen); + + if (buflen % 5 == 0) + msglen = 5; + else if (buflen % 4 == 0) + msglen = 4; + else if (buflen % 3 == 0) + msglen = 3; + else if (buflen % 2 == 0) + msglen = 2; + else if (buflen == 1) + msglen = 1; + else + msglen = 5; + + if (buflen >= msglen) { - /* Interrupts must be disabled while accessing the ad_recv FIFO */ + /* Interrupts must be disabled while accessing the ad_recv FIFO */ - flags = irqsave(); - while (dev->ad_recv.af_head == dev->ad_recv.af_tail) + flags = irqsave(); + while (dev->ad_recv.af_head == dev->ad_recv.af_tail) { - /* The receive FIFO is empty -- was non-blocking mode selected? */ + /* The receive FIFO is empty -- was non-blocking mode selected? */ - if (filep->f_oflags & O_NONBLOCK) + if (filep->f_oflags & O_NONBLOCK) { - ret = -EAGAIN; - goto return_with_irqdisabled; + ret = -EAGAIN; + goto return_with_irqdisabled; } - /* Wait for a message to be received */ + /* Wait for a message to be received */ - dev->ad_nrxwaiters++; - ret = sem_wait(&dev->ad_recv.af_sem); - dev->ad_nrxwaiters--; - if (ret < 0) + dev->ad_nrxwaiters++; + ret = sem_wait(&dev->ad_recv.af_sem); + dev->ad_nrxwaiters--; + if (ret < 0) { - ret = -errno; - goto return_with_irqdisabled; + ret = -errno; + goto return_with_irqdisabled; } } - /* The ad_recv FIFO is not empty. Copy all buffered data that will fit - * in the user buffer. - */ + /* The ad_recv FIFO is not empty. Copy all buffered data that will fit + * in the user buffer. + */ - nread = 0; - do + nread = 0; + do { - FAR struct adc_msg_s *msg = &dev->ad_recv.af_buffer[dev->ad_recv.af_head]; + FAR struct adc_msg_s *msg = &dev->ad_recv.af_buffer[dev->ad_recv.af_head]; - /* Will the next message in the FIFO fit into the user buffer? */ + /* Will the next message in the FIFO fit into the user buffer? */ - if (ret + msglen > buflen) + if (ret + msglen > buflen) { - break; + break; } - /* Copy the message to the user buffer */ + /* Copy the message to the user buffer */ - if (msglen==1) + if (msglen == 1) { - buffer[nread]=msg->am_data>>24; //Only one channel,read highest 8bits + /* Only one channel,read highest 8-bits */ + + buffer[nread] = msg->am_data >> 24; } - else if (msglen==2) + else if (msglen == 2) { - *(int16_t *)&buffer[nread]=msg->am_data>>16; //Only one channel,read highest 16bits + /* Only one channel, read highest 16-bits */ + + *(int16_t *)&buffer[nread] = msg->am_data >> 16; } - else if (msglen==3) + else if (msglen == 3) { - buffer[nread]=msg->am_channel; - *(int16_t *)&buffer[nread+1]=msg->am_data>>16; //read channel highest 16bits + /* Read channel highest 16-bits */ + + buffer[nread] = msg->am_channel; + *(int16_t *)&buffer[nread + 1] = msg->am_data >> 16; } - else if (msglen==4) + else if (msglen == 4) { - *(int32_t *)&buffer[nread]=msg->am_data; //read channel highest 24bits - buffer[nread]=msg->am_channel; + /* read channel highest 24-bits */ + + *(int32_t *)&buffer[nread] = msg->am_data; + buffer[nread] = msg->am_channel; } - else + else { - *(int32_t *)&buffer[nread+1]=msg->am_data; //read all - buffer[nread]=msg->am_channel; + /* Read all */ + + *(int32_t *)&buffer[nread + 1] = msg->am_data; + buffer[nread] = msg->am_channel; } - nread += msglen; + nread += msglen; - /* Increment the head of the circular message buffer */ + /* Increment the head of the circular message buffer */ - if (++dev->ad_recv.af_head >= CONFIG_ADC_FIFOSIZE) + if (++dev->ad_recv.af_head >= CONFIG_ADC_FIFOSIZE) { - dev->ad_recv.af_head = 0; + dev->ad_recv.af_head = 0; } } - while (dev->ad_recv.af_head != dev->ad_recv.af_tail); + while (dev->ad_recv.af_head != dev->ad_recv.af_tail); - /* All on the messages have bee transferred. Return the number of bytes - * that were read. - */ + /* All on the messages have bee transferred. Return the number of bytes + * that were read. + */ - ret = nread; + ret = nread; return_with_irqdisabled: - irqrestore(flags); + irqrestore(flags); } - return ret; + + avdbg("Returning: %d\n", ret); + return ret; } /************************************************************************************ @@ -332,7 +345,7 @@ return_with_irqdisabled: static ssize_t adc_write(FAR struct file *filep, FAR const char *buffer, size_t buflen) { - return 0; + return 0; } /************************************************************************************ @@ -341,12 +354,12 @@ static ssize_t adc_write(FAR struct file *filep, FAR const char *buffer, size_t static int adc_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { - FAR struct inode *inode = filep->f_inode; - FAR struct adc_dev_s *dev = inode->i_private; - int ret = OK; + FAR struct inode *inode = filep->f_inode; + FAR struct adc_dev_s *dev = inode->i_private; + int ret = OK; - ret = dev->ad_ops->ao_ioctl(dev, cmd, arg); - return ret; + ret = dev->ad_ops->ao_ioctl(dev, cmd, arg); + return ret; } /**************************************************************************** @@ -355,51 +368,53 @@ static int adc_ioctl(FAR struct file *filep, int cmd, unsigned long arg) int adc_receive(FAR struct adc_dev_s *dev, uint8_t ch, int32_t data) { - FAR struct adc_fifo_s *fifo = &dev->ad_recv; - int nexttail; - int err = -ENOMEM; + FAR struct adc_fifo_s *fifo = &dev->ad_recv; + int nexttail; + int err = -ENOMEM; - /* Check if adding this new message would over-run the drivers ability to enqueue - * read data. - */ + /* Check if adding this new message would over-run the drivers ability to enqueue + * read data. + */ - nexttail = fifo->af_tail + 1; - if (nexttail >= CONFIG_ADC_FIFOSIZE) + nexttail = fifo->af_tail + 1; + if (nexttail >= CONFIG_ADC_FIFOSIZE) { - nexttail = 0; + nexttail = 0; } - /* Refuse the new data if the FIFO is full */ + /* Refuse the new data if the FIFO is full */ - if (nexttail != fifo->af_head) + if (nexttail != fifo->af_head) { - /* Add the new, decoded CAN message at the tail of the FIFO */ + /* Add the new, decoded CAN message at the tail of the FIFO */ - fifo->af_buffer[fifo->af_tail].am_channel = ch; - fifo->af_buffer[fifo->af_tail].am_data=data; + fifo->af_buffer[fifo->af_tail].am_channel = ch; + fifo->af_buffer[fifo->af_tail].am_data = data; - /* Increment the tail of the circular buffer */ + /* Increment the tail of the circular buffer */ - fifo->af_tail = nexttail; + fifo->af_tail = nexttail; - if(dev->ad_nrxwaiters>0) - sem_post(&fifo->af_sem); - err = OK; + if (dev->ad_nrxwaiters > 0) + { + sem_post(&fifo->af_sem); + } + err = OK; } return err; } int adc_register(FAR const char *path, FAR struct adc_dev_s *dev) { - /* Initialize the ADC device structure */ + /* Initialize the ADC device structure */ - dev->ad_ocount = 0; + dev->ad_ocount = 0; - sem_init(&dev->ad_recv.af_sem, 0, 0); - sem_init(&dev->ad_closesem, 0, 1); + sem_init(&dev->ad_recv.af_sem, 0, 0); + sem_init(&dev->ad_closesem, 0, 1); - dev->ad_ops->ao_reset(dev); + dev->ad_ops->ao_reset(dev); - return register_driver(path, &adc_fops, 0444, dev); + return register_driver(path, &adc_fops, 0444, dev); } |