diff options
author | Gregory Nutt <gnutt@nuttx.org> | 2013-06-11 14:32:07 -0600 |
---|---|---|
committer | Gregory Nutt <gnutt@nuttx.org> | 2013-06-11 14:32:07 -0600 |
commit | 190ecc0e601b476d93280bbb5550e9588dff3011 (patch) | |
tree | 684539731baa8d520fa967b20161be05b97c29a7 | |
parent | 1930ae380035e4ed8d546c08ad20369906df78e8 (diff) | |
download | px4-nuttx-190ecc0e601b476d93280bbb5550e9588dff3011.tar.gz px4-nuttx-190ecc0e601b476d93280bbb5550e9588dff3011.tar.bz2 px4-nuttx-190ecc0e601b476d93280bbb5550e9588dff3011.zip |
SAM4S: Add pin multiplexing definitions
-rw-r--r-- | nuttx/ChangeLog | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/include/sam34/sam3u_irq.h | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h | 24 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h | 314 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_periphclks.h | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_lowputc.c | 47 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_serial.c | 622 |
8 files changed, 580 insertions, 439 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 7b0fdf5fa..51f09b4e9 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -4947,4 +4947,6 @@ There is not much there on initial checkin (2013-6-10). * arch/arm/src/sam34: SAM3S support: GPIO, chip characteristics, peripheral Kconfig (2013-6-11). + * arch/arm/src/sam34/chip/sam4s_pinmap.h: Add SAM4S pin configuration + definitinos (2013-6-11). diff --git a/nuttx/arch/arm/include/sam34/sam3u_irq.h b/nuttx/arch/arm/include/sam34/sam3u_irq.h index 58f2afd94..9f7c4d771 100644 --- a/nuttx/arch/arm/include/sam34/sam3u_irq.h +++ b/nuttx/arch/arm/include/sam34/sam3u_irq.h @@ -58,7 +58,7 @@ #define SAM_PID_PMC (5) /* Power Management Controller */ #define SAM_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */ #define SAM_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */ -#define SAM_PID_UART (8) /* Universal Asynchronous Receiver Transmitter */ +#define SAM_PID_UART0 (8) /* Universal Asynchronous Receiver Transmitter */ #define SAM_PID_SMC (9) /* Static Memory Controller */ #define SAM_PID_PIOA (10) /* Parallel I/O Controller A */ #define SAM_PID_PIOB (11) /* Parallel I/O Controller B */ @@ -92,7 +92,7 @@ #define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */ #define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */ #define SAM_IRQ_EEFC1 (SAM_IRQ_EXTINT+SAM_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */ -#define SAM_IRQ_UART (SAM_IRQ_EXTINT+SAM_PID_UART) /* Universal Asynchronous Receiver Transmitter */ +#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter */ #define SAM_IRQ_SMC (SAM_IRQ_EXTINT+SAM_PID_SMC) /* Static Memory Controller */ #define SAM_IRQ_PIOA (SAM_IRQ_EXTINT+SAM_PID_PIOA) /* Parallel I/O Controller A */ #define SAM_IRQ_PIOB (SAM_IRQ_EXTINT+SAM_PID_PIOB) /* Parallel I/O Controller B */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h index fbcffbfd0..e508a3b4c 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pinmap.h @@ -122,12 +122,12 @@ #define GPIO_MCI_DA (GPIO_PERIPHA|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN4) #define GPIO_MCI_DAT0IN (GPIO_INPUT|GPIO_CFG_PULLUP|GPIO_PORT_PIOA|GPIO_PIN5) -#define GPIO_PWMC_PWMH0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0) -#define GPIO_PWMC_PWML0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7) -#define GPIO_PWMC_PWMH1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1) -#define GPIO_PWMC_PWML1 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8) -#define GPIO_PWMC_PWMH2 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2) -#define GPIO_PWMC_PWML2 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) +#define GPIO_PWM0_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN0) +#define GPIO_PWM0_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN7) +#define GPIO_PWM1_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN1) +#define GPIO_PWM1_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN8) +#define GPIO_PWM2_H (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN2) +#define GPIO_PWM2_L (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) #define GPIO_SPI0_MISO (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN13) #define GPIO_SPI0_MOSI (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN14) @@ -149,13 +149,13 @@ #define GPIO_PCK0 (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21) -#define GPIO_TWI_TWD0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) -#define GPIO_TWI_TWCK0 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10) -#define GPIO_TWI_TWD1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) -#define GPIO_TWI_TWCK1 (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) +#define GPIO_TWI0_D (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN9) +#define GPIO_TWI0_CK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN10) +#define GPIO_TW1I_D (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN24) +#define GPIO_TWI1_CK (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN25) -#define GPIO_UART_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12) -#define GPIO_UART_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11) +#define GPIO_UART0_TXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN12) +#define GPIO_UART0_RXD (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN11) #define GPIO_USART0_CTS (GPIO_PERIPHA|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN8) #define GPIO_USART0_DCD (GPIO_PERIPHB|GPIO_CFG_DEFAULT|GPIO_PORT_PIOB|GPIO_PIN11) diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h index fd4c1a39e..2af4ac734 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_vectors.h @@ -62,7 +62,7 @@ VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */ VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */ VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */ - VECTOR(sam_uart, SAM_IRQ_UART) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */ + VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */ VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+9: Static Memory Controller */ VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+10: Parallel I/O Controller A */ VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+11: Parallel I/O Controller B */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h new file mode 100644 index 000000000..589ffd270 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h @@ -0,0 +1,314 @@ +/************************************************************************************ + * arch/arm/src/sam34/chip/sam4s_pinmap.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "sam_gpio.h" + +/************************************************************************************ + * Definitions + ************************************************************************************/ + +/* GPIO pin definitions *************************************************************/ +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. + * Drivers, however, will use the pin selection without the numeric suffix. + * Additional definitions are required in the board.h file. For example, if we + * wanted the programmable clock output PCK0 on PA6, then the following definition + * should appear in the board.h header file for that board: + * + * #define GPIO_PCK0 GPIO_PCK0_1 + * + * The driver will then automatically configre PA6 as the PCK0 pin. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in this file. + */ + +/* 12-bit Analog-to-Digital Conververt (ADC) */ + +#define GPIO_ADC0_AD0 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_ADC0_AD1 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_ADC0_AD2 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_ADC0_AD3 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_ADC0_AD4 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_ADC0_AD5 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_ADC0_AD6 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_ADC0_AD7 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN3) +#define GPIO_ADC0_AD8 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_ADC0_AD9 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_ADC0_AD10 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_ADC0_AD11 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_ADC0_AD12 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_ADC0_AD13 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_ADC0_AD14 (GPIO_INPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_ADC0_ADTRG (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN8) + +/* Digital-to-Analog Convert (DAC) */ + +#define GPIO_DAC0 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_DAC1 (GPIO_OUTPUT | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_DAC_DATRG (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN2) + +/* High-Speed Multimedia Card Interface (HSMCI) */ + +#define GPIO_MCI_CK (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_MCI_DA (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_MCI_DAT0 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_MCI_DAT1 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_MCI_DAT2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_MCI_DAT3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN27) + +/* Programmable Clock Output */ + +#define GPIO_PCK0_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN6) +#define GPIO_PCK0_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_PCK1_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_PCK1_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_PCK2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_PCK2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_PCK2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN3) + +/* Pulse Width Modulation (PWM) */ + +#define GPIO_PWM0_FI (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_PWM0_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_PWM0_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN0) +#define GPIO_PWM0_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_PWM0_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_PWM0_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_PWM0_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_PWM0_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_PWM0_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_PWM0_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_PWM1_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_PWM1_H_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN1) +#define GPIO_PWM1_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_PWM1_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_PWM1_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_PWM1_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_PWM1_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN12) +#define GPIO_PWM1_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_PWM1_L_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_PWM2_H_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_PWM2_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_PWM2_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_PWM2_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN4) +#define GPIO_PWM2_H_5 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_PWM2_L_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_PWM2_L_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN13) +#define GPIO_PWM2_L_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_PWM2_L_4 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_PWM3_H_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN14) +#define GPIO_PWM3_H_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_PWM3_H_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_PWM3_H_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_PWM3_H_5 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_PWM3_L_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_PWM3_L_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_PWM3_L_3 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN15) + +/* Static Memory Controller (SMC) */ + +#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN8) + +/* Serial Peripheral Interface (SPI) */ + +#define GPIO_SPI0_MISO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN12) +#define GPIO_SPI0_MOSI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN13) +#define GPIO_SPI0_NPCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN11) +#define GPIO_SPI0_NPCS1_1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN31) +#define GPIO_SPI0_NPCS1_2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN14) +#define GPIO_SPI0_NPCS1_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_SPI0_NPCS1_4 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SPI0_NPCS2_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_SPI0_NPCS2_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN30) +#define GPIO_SPI0_NPCS2_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_SPI0_NPCS3_1 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SPI0_NPCS3_2 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN3) +#define GPIO_SPI0_NPCS3_3 (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_SPI0_SPCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN14) + +/* Synchronous Serial Controller (SSC) */ + +#define GPIO_SSC_RD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SSC_RF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SSC_RK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SSC_TD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN17) +#define GPIO_SSC_TF (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_SSC_TK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN16) + +/* Timer/Counters (TC) */ + +#define GPIO_TC0_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_TC0_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_TC0_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_TC1_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_TC1_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN15) +#define GPIO_TC1_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN16) +#define GPIO_TC2_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN29) +#define GPIO_TC2_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_TC2_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_TC3_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_TC3_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_TC3_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_TC4_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_TC4_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_TC4_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_TC5_TCLK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_TC5_TIOA (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_TC5_TIOB (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOC | GPIO_PIN30) + +/* Two Wire Interface (TWI) */ + +#define GPIO_TWI0_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN4) +#define GPIO_TWI0_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN3) +#define GPIO_TWI1_CK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN5) +#define GPIO_TWI1_D (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN4) + +/* Universal Asynchronous Receiver Transceiver (UART) */ + +#define GPIO_UART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN9) +#define GPIO_UART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN10) +#define GPIO_UART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN2) +#define GPIO_UART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOB | GPIO_PIN3) + +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ + +#define GPIO_USART0_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN8) +#define GPIO_USART0_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN7) +#define GPIO_USART0_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN5) +#define GPIO_USART0_SCK (GPIO_PERIPHB | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN2) +#define GPIO_USART0_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN6) + +#define GPIO_USART1_CTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_USART1_DCD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN26) +#define GPIO_USART1_DSR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN28) +#define GPIO_USART1_DTR (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN27) +#define GPIO_USART1_RI (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN29) + +#define GPIO_USART1_RTS (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_USART1_RXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN21) +#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | PIO_PORT_PIOA | GPIO_PIN22) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/sam34/sam3u_periphclks.h b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h index 0facf690a..0b0466f8c 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_periphclks.h +++ b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h @@ -61,7 +61,7 @@ #define sam_pmc_enableclk() sam_enableperipheral(SAM_PID_PMC) #define sam_eefc0_enableclk() sam_enableperipheral(SAM_PID_EEFC0) #define sam_eefc1_enableclk() sam_enableperipheral(SAM_PID_EEFC1) -#define sam_uart_enableclk() sam_enableperipheral(SAM_PID_UART) +#define sam_uart0_enableclk() sam_enableperipheral(SAM_PID_UART0) #define sam_smc_enableclk() sam_enableperipheral(SAM_PID_SMC) #define sam_pioa_enableclk() sam_enableperipheral(SAM_PID_PIOA) #define sam_piob_enableclk() sam_enableperipheral(SAM_PID_PIOB) @@ -91,7 +91,7 @@ #define sam_pmc_disableclk() sam_disableperipheral(SAM_PID_PMC) #define sam_eefc0_disableclk() sam_disableperipheral(SAM_PID_EEFC0) #define sam_eefc1_disableclk() sam_disableperipheral(SAM_PID_EEFC1) -#define sam_uart_disableclk() sam_disableperipheral(SAM_PID_UART) +#define sam_uart0_disableclk() sam_disableperipheral(SAM_PID_UART0) #define sam_smc_disableclk() sam_disableperipheral(SAM_PID_SMC) #define sam_pioa_disableclk() sam_disableperipheral(SAM_PID_PIOA) #define sam_piob_disableclk() sam_disableperipheral(SAM_PID_PIOB) diff --git a/nuttx/arch/arm/src/sam34/sam_lowputc.c b/nuttx/arch/arm/src/sam34/sam_lowputc.c index 8add13587..0ed02235a 100644 --- a/nuttx/arch/arm/src/sam34/sam_lowputc.c +++ b/nuttx/arch/arm/src/sam34/sam_lowputc.c @@ -56,6 +56,9 @@ #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_usart.h" # include "sam4l_periphclks.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4S) +# include "chip/sam3u_uart.h" +# include "sam4s_periphclks.h" #else # error Unknown UART #endif @@ -85,40 +88,54 @@ # undef CONFIG_SAM34_USART3 #endif -/* Is there a serial console? It could be on the UART, or USARTn */ +/* Is there a serial console? It could be on UART0-1 or USART0-3 */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3) -# undef CONFIG_USART_SERIAL_CONSOLE +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #else -# undef CONFIG_USART_SERIAL_CONSOLE +# warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -151,6 +168,12 @@ # define SAM_CONSOLE_BITS CONFIG_UART0_BITS # define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY # define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define SAM_CONSOLE_BASE SAM_UART1_BASE +# define SAM_CONSOLE_BAUD CONFIG_UART1_BAUD +# define SAM_CONSOLE_BITS CONFIG_UART1_BITS +# define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY +# define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP #elif defined(CONFIG_USART0_SERIAL_CONSOLE) # define SAM_CONSOLE_BASE SAM_USART0_BASE # define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD @@ -189,7 +212,8 @@ # define MR_CHRL_VALUE UART_MR_CHRL_7BITS /* 7 bits */ #elif SAM_CONSOLE_BITS == 8 # define MR_CHRL_VALUE UART_MR_CHRL_8BITS /* 8 bits */ -#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART_SERIAL_CONSOLE) +#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART0_SERIAL_CONSOLE) && \ + !defined(CONFIG_UART1_SERIAL_CONSOLE) # define MR_CHRL_VALUE UART_MR_MODE9 #else # error "Invlaid number of bits" @@ -270,7 +294,10 @@ void sam_lowsetup(void) /* Enable clocking for all selected UART/USARTs */ #ifdef CONFIG_SAM34_UART0 - sam_uart_enableclk(); + sam_uart0_enableclk(); +#endif +#ifdef CONFIG_SAM34_UART1 + sam_uart1_enableclk(); #endif #ifdef CONFIG_SAM34_USART0 sam_usart0_enableclk(); @@ -288,8 +315,8 @@ void sam_lowsetup(void) /* Configure UART pins for all selected UART/USARTs */ #ifdef CONFIG_SAM34_UART0 - (void)sam_configgpio(GPIO_UART_RXD); - (void)sam_configgpio(GPIO_UART_TXD); + (void)sam_configgpio(GPIO_UART0_RXD); + (void)sam_configgpio(GPIO_UART0_TXD); #endif #ifdef CONFIG_SAM34_USART0 diff --git a/nuttx/arch/arm/src/sam34/sam_serial.c b/nuttx/arch/arm/src/sam34/sam_serial.c index 5133ec25f..dcc81ab0f 100644 --- a/nuttx/arch/arm/src/sam34/sam_serial.c +++ b/nuttx/arch/arm/src/sam34/sam_serial.c @@ -93,9 +93,9 @@ /* Is there a USART/USART enabled? */ -#if !defined(CONFIG_SAM34_UART0) && !defined(CONFIG_SAM34_USART0) && \ - !defined(CONFIG_SAM34_USART1) && !defined(CONFIG_SAM34_USART2) && \ - !defined(CONFIG_SAM34_USART3) +#if !defined(CONFIG_SAM34_UART0) && !defined(CONFIG_SAM34_UART1) && \ + !defined(CONFIG_SAM34_USART0) && !defined(CONFIG_SAM34_USART1) && \ + !defined(CONFIG_SAM34_USART2) && !defined(CONFIG_SAM34_USART3) # error "No USARTs enabled" #endif @@ -104,9 +104,17 @@ # define HAVE_USART #endif -/* Is there a serial console? */ +/* Is there a serial console? It could be on UART0-1 or USART0-3 */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -114,24 +122,28 @@ # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART0) # undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART1) # undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART2) # undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # define HAVE_CONSOLE 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM34_USART3) # undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -139,6 +151,7 @@ #else # warning "No valid CONFIG_USARTn_SERIAL_CONSOLE Setting" # undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -152,405 +165,148 @@ #ifdef USE_SERIALDRIVER -/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? */ +/* Which UART/USART with be tty0/console and which tty1? tty2? tty3? tty4? tty5? */ + +/* First pick the console and ttys0. This could be any of UART0-1, USART0-3 */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uartport /* UART=console */ -# define TTYS0_DEV g_uartport /* UART=ttyS0 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* UART=ttyS0;USART0=ttyS1 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* UART=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART1=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART0=ttyS1;USART1=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART0=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* UART=ttyS0;USART1=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* UART=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* UART=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* UART=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* UART=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* UART=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 #elif defined(CONFIG_USART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart0port /* USART0=console */ -# define TTYS0_DEV g_usart0port /* USART0=ttyS0 */ -# ifdef CONFIG_SAM34_UART0 -# define TTYS1_DEV g_uartport /* USART0=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART0=ttyS0;UART=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART1=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;UART=ttyS1;USART1=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART0=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART0=ttyS0;USART1=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART0=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART0=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART0=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART0=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART0=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART0=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart0port /* USART0 is console */ +# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 #elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart1port /* USART1=console */ -# define TTYS0_DEV g_usart1port /* USART1=ttyS0 */ -# ifdef CONFIG_SAM34_UART0 -# define TTYS1_DEV g_uartport /* USART1=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART1=ttyS0;UART=ttyS1;USART0=ttyS2;USART2=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART0=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;UART=ttyS1;USART2=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART1=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART1=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART1=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART1=ttyS0;USART2=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART1=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART1=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART1=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART1=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart1port /* USART1 is console */ +# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 #elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart2port /* USART2=console */ -# define TTYS0_DEV g_usart2port /* USART2=ttyS0 */ -# ifdef CONFIG_SAM34_UART0 -# define TTYS1_DEV g_uartport /* USART2=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS3_DEV g_usart1port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS4_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;USART3=ttyS4 */ -# else -# undef TTYS4_DEV /* USART2=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART0=ttyS;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;UART=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART2=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS3_DEV g_usart3port /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;USART3=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART2=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART0=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART2=ttyS0;USART1=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART3 -# define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART2=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART3 -# define TTYS1_DEV g_usart3port /* USART2=ttyS0;USART3=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART2=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif +# define CONSOLE_DEV g_usart2port /* USART2 is console */ +# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 #elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define CONSOLE_DEV g_usart3port /* USART3=console */ -# define TTYS0_DEV g_usart3port /* USART3=ttyS0 */ -# ifdef CONFIG_SAM34_UART0 -# define TTYS1_DEV g_uartport /* USART3=ttyS0;UART=ttyS1 */ -# ifdef CONFIG_SAM34_USART0 -# define TTYS2_DEV g_usart0port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS3_DEV g_usart1port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS4_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;USART2=ttyS4 */ -# else -# undef TTYS4_DEV /* USART3=ttyS0;UART=ttyS1;USART0=ttyS2;USART1=ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART0=ttyS;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;UART=ttyS1;USART0=ttyS;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;UART=ttyS1;USART1=ttys2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART3=ttyS0;UART=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;UART=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# undef TTYS4_DEV /* No ttyS4 */ -# endif -# endif -# else -# ifdef CONFIG_SAM34_USART0 -# define TTYS1_DEV g_usart0port /* USART3=ttyS0;USART0=ttyS1;No ttyS4 */ -# ifdef CONFIG_SAM34_USART1 -# define TTYS2_DEV g_usart1port /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS3_DEV g_usart2port /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;USART2=ttyS3;No ttyS4 */ -# else -# undef TTYS3_DEV /* USART3=ttyS0;USART0=ttyS1;USART1=ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_usart2port /* USART3=ttyS0;USART0=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;USART0=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# else -# ifdef CONFIG_SAM34_USART1 -# define TTYS1_DEV g_usart1port /* USART3=ttyS0;USART1=ttyS1;No ttyS3;No ttyS4 */ -# ifdef CONFIG_SAM34_USART2 -# define TTYS2_DEV g_EEEEport /* USART3=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS2_DEV /* USART3=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# else -# ifdef CONFIG_SAM34_USART2 -# define TTYS1_DEV g_usart2port /* USART3=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# else -# undef TTYS1_DEV /* USART3=ttyS0;No ttyS1;No ttyS2;No ttyS3;No ttyS4 */ -# endif -# undef TTYS2_DEV /* No ttyS2 */ -# endif -# undef TTYS3_DEV /* No ttyS3 */ -# endif -# undef TTYS4_DEV /* No ttyS4 */ +# define CONSOLE_DEV g_usart3port /* USART3 is console */ +# define TTYS5_DEV g_usart3port /* USART3 is ttyS0 */ +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_SAM34_UART0) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_SAM34_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART0) +# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ +# define USART0_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART1) +# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */ +# define USART1_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART2) +# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */ +# define USART2_ASSIGNED 1 +# elif defined(CONFIG_SAM34_USART3) +# define TTYS0_DEV g_usart3port /* USART3 is ttyS0 */ +# define USART3_ASSIGNED 1 # endif #endif +/* Pick ttys1. This could be any of UART0-1, USART0-3 excluding the console UART. */ + +#if defined(CONFIG_SAM34_UART0) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS1_DEV g_usart3port /* USART3 is ttyS1 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART1 or USART0-3. It can't be UART0 + * because that was either assigned as ttyS0 or ttys1. One of these + * could also be the console. + */ + +#if defined(CONFIG_SAM34_UART1) && !defined(UART1_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS2_DEV g_usart3port /* USART3 is ttyS2 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys3. This could be one of USART0-3. It can't be UART0-1 because + * those have already been assigned to ttsyS0, 1, or 2. One of + * USART0-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART0) && !defined(USART0_ASSIGNED) +# define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */ +# define USART0_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS3_DEV g_usart3port /* USART3 is ttyS3 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys4. This could be one of USART1-3. It can't be UART0-1 or USART0 + * because those have already been assigned to ttsyS0, 1, 2 or 3. One of + * USART1-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART1) && !defined(USART1_ASSIGNED) +# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */ +# define USART1_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS4_DEV g_usart3port /* USART3 is ttyS4 */ +# define USART3_ASSIGNED 1 +#endif + +/* Pick ttys5. This could be one of USART2-3. It can't be UART0-1 or + * USART0-1 because those have already been assigned to ttsyS0, 1, 2, + * 3 or 4. One of USART2-3 could also be the console. + */ + +#if defined(CONFIG_SAM34_USART2) && !defined(USART2_ASSIGNED) +# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */ +# define USART2_ASSIGNED 1 +#elif defined(CONFIG_SAM34_USART3) && !defined(USART3_ASSIGNED) +# define TTYS5_DEV g_usart3port /* USART3 is ttyS5 */ +# define USART3_ASSIGNED 1 +#endif + /* Select MCU-specific settings * * For the SAM3U, the USARTs are driven by the main clock. @@ -625,8 +381,12 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ #ifdef CONFIG_SAM34_UART0 -static char g_uartrxbuffer[CONFIG_UART0_RXBUFSIZE]; -static char g_uarttxbuffer[CONFIG_UART0_TXBUFSIZE]; +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_SAM34_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; #endif #ifdef CONFIG_SAM34_USART0 static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; @@ -645,33 +405,63 @@ static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; #endif -/* This describes the state of the UART port. */ +/* This describes the state of the UART0 port. */ #ifdef CONFIG_SAM34_UART0 -static struct up_dev_s g_uartpriv = +static struct up_dev_s g_uart0priv = { .usartbase = SAM_UART0_BASE, .baud = CONFIG_UART0_BAUD, - .irq = SAM_IRQ_UART, + .irq = SAM_IRQ_UART0, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, .stopbits2 = CONFIG_UART0_2STOP, }; -static uart_dev_t g_uartport = +static uart_dev_t g_uart0port = { .recv = { .size = CONFIG_UART0_RXBUFSIZE, - .buffer = g_uartrxbuffer, + .buffer = g_uart0rxbuffer, }, .xmit = { .size = CONFIG_UART0_TXBUFSIZE, - .buffer = g_uarttxbuffer, + .buffer = g_uart0txbuffer, }, .ops = &g_uart_ops, - .priv = &g_uartpriv, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the UART1 port. */ + +#ifdef CONFIG_SAM34_UART1 +static struct up_dev_s g_uart1priv = +{ + .usartbase = SAM_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irq = SAM_IRQ_UART1, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, }; #endif @@ -913,13 +703,14 @@ static int up_setup(struct uart_dev_s *dev) regval |= UART_MR_CHRL_7BITS; /* 7 bits */ } #ifdef HAVE_USART -#ifdef CONFIG_SAM34_UART0 - /* UART does not support 9bit mode */ - - else if (priv->bits == 9 && priv->usartbase != SAM_UART_BASE) -#else - else if (priv->bits == 9) /* Only USARTS */ + else if (priv->bits == 9 +#if defined(CONFIG_SAM34_UART0) + && priv->usartbase != SAM_UART0_BASE +#endif +#if defined(CONFIG_SAM34_UART1) + && priv->usartbase != SAM_UART1_BASE #endif + ) { regval |= UART_MR_MODE9; /* 9 bits */ } @@ -1068,9 +859,16 @@ static int up_interrupt(int irq, void *context) bool handled; #ifdef CONFIG_SAM34_UART0 - if (g_uartpriv.irq == irq) + if (g_uart0priv.irq == irq) + { + dev = &g_uart0port; + } + else +#endif +#ifdef CONFIG_SAM34_UART1 + if (g_uart1priv.irq == irq) { - dev = &g_uartport; + dev = &g_uart1port; } else #endif @@ -1119,7 +917,7 @@ static int up_interrupt(int irq, void *context) /* Get the UART/USART status (we are only interested in the unmasked interrupts). */ priv->sr = up_serialin(priv, SAM_UART_SR_OFFSET); /* Save for error reporting */ - pending = priv->sr & priv->imr; /* Mask out disabled interrupt sources */ + pending = priv->sr & priv->imr; /* Mask out disabled interrupt sources */ /* Handle an incoming, receive byte. RXRDY: At least one complete character * has been received and US_RHR has not yet been read. |