SAMV71-XULT: Tried the SDRAM test again. Found one bug, but it still fails

3 files changed, 33 insertions, 39 deletions

diff --git a/nuttx/configs/samv71-xult/README.txt b/nuttx/configs/samv71-xult/README.txt
index ef6edbbb3..757e0f6f0 100644
--- a/nuttx/configs/samv71-xult/README.txt
+++ b/nuttx/configs/samv71-xult/README.txt
@@ -1307,26 +1307,9 @@ Configuration sub-directories
 
        The RAM test can be executed as follows:
 
-         nsh> ramtest -w 70000000 209152
-
-       STATUS: As of this writing, SDRAM does not pass the RAM test.  This is the sympton:
-
-        nsh> mw 70000000
-          70000000 = 0x00000000
-        nsh> mw 70000000=55555555
-          70000000 = 0x00000000 -> 0x55555555
-        nsh> mw 70000000
-          70000000 = 0x55555555
-
-        nsh> mw 70100000
-          70100000 = 0x00000000
-        nsh> mw 70100000=aaaaaaaa
-          70100000 = 0x00000000 -> 0xaaaaaaaa
-        nsh> mw 70100000
-          70100000 = 0xaaaaaaaa
-
-        nsh> mw 70000000
-          70000000 = 0x00000000 <<< Lost RAM content
+         nsh> ramtest -w 70000000 2097152
+
+       STATUS: As of this writing, SDRAM does not pass the RAM test.
 
     5. The button test at apps/examples/buttons is included in the
        configuration.  This configuration illustrates (1) use of the buttons
diff --git a/nuttx/configs/samv71-xult/nsh/defconfig b/nuttx/configs/samv71-xult/nsh/defconfig
index 59f00daae..e0589580e 100644
--- a/nuttx/configs/samv71-xult/nsh/defconfig
+++ b/nuttx/configs/samv71-xult/nsh/defconfig
@@ -123,6 +123,7 @@ CONFIG_ARMV7M_HAVE_ICACHE=y
 CONFIG_ARMV7M_HAVE_DCACHE=y
 CONFIG_ARMV7M_ICACHE=y
 CONFIG_ARMV7M_DCACHE=y
+# CONFIG_ARMV7M_DCACHE_WRITETHROUGH is not set
 CONFIG_ARMV7M_HAVE_ITCM=y
 CONFIG_ARMV7M_HAVE_DTCM=y
 # CONFIG_ARMV7M_ITCM is not set
@@ -326,6 +327,12 @@ CONFIG_NSH_MMCSDSLOTNO=0
 #
 # Board-Specific Options
 #
+# CONFIG_SAMV71XULT_MXTXPLND is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_TSCTEST is not set
+# CONFIG_BOARDCTL_ADCTEST is not set
+# CONFIG_BOARDCTL_GRAPHICS is not set
+# CONFIG_BOARDCTL_IOCTL is not set
 
 #
 # RTOS Features
@@ -462,9 +469,14 @@ CONFIG_SPI_EXCHANGE=y
 # CONFIG_SPI_CALLBACK is not set
 # CONFIG_SPI_BITBANG is not set
 # CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
 # CONFIG_TIMER is not set
 # CONFIG_RTC is not set
 # CONFIG_WATCHDOG is not set
+# CONFIG_TIMERS_CS2100CP is not set
 # CONFIG_ANALOG is not set
 # CONFIG_AUDIO_DEVICES is not set
 # CONFIG_VIDEO_DEVICES is not set
@@ -806,12 +818,7 @@ CONFIG_EXAMPLES_NSH=y
 # CONFIG_NETUTILS_FTPC is not set
 # CONFIG_NETUTILS_JSON is not set
 # CONFIG_NETUTILS_SMTP is not set
-CONFIG_NETUTILS_TFTPC=y
 # CONFIG_NETUTILS_THTTPD is not set
-CONFIG_NETUTILS_NETLIB=y
-CONFIG_NETUTILS_WEBCLIENT=y
-CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)"
-CONFIG_WEBCLIENT_TIMEOUT=10
 # CONFIG_NETUTILS_PPPD is not set
 
 #
@@ -905,7 +912,6 @@ CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_CONSOLE=y
 # CONFIG_NSH_ALTCONDEV is not set
 CONFIG_NSH_ARCHINIT=y
-CONFIG_LIB_BOARDCTL=y
 
 #
 # NxWidgets/NxWM
diff --git a/nuttx/configs/samv71-xult/src/sam_sdram.c b/nuttx/configs/samv71-xult/src/sam_sdram.c
index f2b3336b0..2c9799d07 100644
--- a/nuttx/configs/samv71-xult/src/sam_sdram.c
+++ b/nuttx/configs/samv71-xult/src/sam_sdram.c
@@ -67,31 +67,34 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#define SDRAM_BA0 (1 << 20)
+#define SDRAM_BA1 (1 << 21)
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Public Functions
- ************************************************************************************/
+ ****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Name: sam_sdram_config
  *
  * Description:
- *   Configures the on-board SDRAM.  SAMV71 Xplained Ultra features one external
- *   IS42S16100E-7BLI, 512Kx16x2, 10ns, SDRAM. SDRAM0 is connected to chip select
- *   NCS1.
+ *   Configures the on-board SDRAM.  SAMV71 Xplained Ultra features one
+ *   external IS42S16100E-7BLI, 512Kx16x2, 10ns, SDRAM. SDRAM0 is connected
+ *   to chip select NCS1.
  *
  *  Input Parameters:
  *     None
  *
  *  Assumptions:
- *    The DDR memory regions is configured as strongly ordered memory.  When we
- *    complete initialization of SDRAM and it is ready for use, we will make DRAM
- *    into normal memory.
+ *    The DDR memory regions is configured as strongly ordered memory.  When
+ *    we complete initialization of SDRAM and it is ready for use, we will
+ *    make DRAM into normal, cached memory.
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 void sam_sdram_config(void)
 {
@@ -150,17 +153,19 @@ void sam_sdram_config(void)
   sam_configgpio(GPIO_SMC_A7);        /* PC25 A7        -> A5 */
   sam_configgpio(GPIO_SMC_A8);        /* PC26 A8        -> A6 */
   sam_configgpio(GPIO_SMC_A9);        /* PC27 A9        -> A7 */
+  sam_configgpio(GPIO_SMC_A10);       /* PC28 A10       -> A8 */
+  sam_configgpio(GPIO_SMC_A11);       /* PC29 A11       -> A9 */
   sam_configgpio(GPIO_SDRAMC_A10_2);  /* PD13 SDA10     -> A10 */
   sam_configgpio(GPIO_SDRAMC_BA0);    /* PA20 BA0       -> A11 */
 
-  sam_configgpio(GPIO_SDRAMC_CAS);    /* PD17 CAS       -> nCAS */
   sam_configgpio(GPIO_SDRAMC_CKE);    /* PD14 SDCKE     -> CKE */
   sam_configgpio(GPIO_SDRAMC_CK);     /* PD23 SDCK      -> CLK */
   sam_configgpio(GPIO_SDRAMC_CS_1);   /* PC15 SDCS      -> nCS */
-  sam_configgpio(GPIO_SMC_NBS0);      /* PC18 A0/NBS0   -> LDQM */
   sam_configgpio(GPIO_SDRAMC_RAS);    /* PD16 RAS       -> nRAS */
-  sam_configgpio(GPIO_SMC_NBS1);      /* PD15 NWR1/NBS1 -> UDQM */
+  sam_configgpio(GPIO_SDRAMC_CAS);    /* PD17 CAS       -> nCAS */
   sam_configgpio(GPIO_SDRAMC_WE);     /* PD29 SDWE      -> nWE */
+  sam_configgpio(GPIO_SMC_NBS0);      /* PC18 A0/NBS0   -> LDQM */
+  sam_configgpio(GPIO_SMC_NBS1);      /* PD15 NWR1/NBS1 -> UDQM */
 
   /* Enable the SDRAMC peripheral */