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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-07-21 12:52:38 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-07-21 12:52:38 -0600 |
| commit | 0d4b1a260f420c65588795c0f2bb0f6c3f21c3ba (patch) | |
| tree | 679ab6e3815f343d2ef4e481124c9e970204eb7c /nuttx/arch/arm/src/armv7-a/arm_head.S | |
| parent | 57fffd22bdc9ba4d356795734f9020ecc08d6d10 (diff) | |
| download | px4-nuttx-0d4b1a260f420c65588795c0f2bb0f6c3f21c3ba.tar.gz px4-nuttx-0d4b1a260f420c65588795c0f2bb0f6c3f21c3ba.tar.bz2 px4-nuttx-0d4b1a260f420c65588795c0f2bb0f6c3f21c3ba.zip | |
A few more Cortex-A5 and SAMA5 files
Diffstat (limited to 'nuttx/arch/arm/src/armv7-a/arm_head.S')
| -rw-r--r-- | nuttx/arch/arm/src/armv7-a/arm_head.S | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/nuttx/arch/arm/src/armv7-a/arm_head.S b/nuttx/arch/arm/src/armv7-a/arm_head.S index fdd139b36..acb87b248 100644 --- a/nuttx/arch/arm/src/armv7-a/arm_head.S +++ b/nuttx/arch/arm/src/armv7-a/arm_head.S @@ -343,17 +343,20 @@ __start: /* Invalidate caches and TLBs. * - * NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not - * support a CP15 operation to invalidate the entire data cache. ... - * In normal usage the only time the entire data cache has to be - * invalidated is on reset." + * NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not + * support a CP15 operation to invalidate the entire data cache. ... + * In normal usage the only time the entire data cache has to be + * invalidated is on reset." * - * REVISIT: This could be an issue if NuttX is every started in a - * context where the DCache could be dirty. + * The instruction cache is virtually indexed and physically tagged but + * the data cache is physically indexed and physically tagged. So it + * should not be an issue if the system comes up with a dirty Dcache; + * the ICache, however, must be invalidated. */ mov r0, #0 mcr CP15_ICIALLUIS(r0) /* Invalidate entire instruction cache Inner Shareable */ + mcr CP15_TLBIALLIS(r0) /* Invalidate entire Unified TLB Inner Shareable */ /* Load the page table address. * @@ -392,10 +395,15 @@ __start: ldr lr, .LCvstart /* Abs. virtual address */ - /* Configure the domain access register (see mmu.h) */ + /* Configure the domain access register (see mmu.h). + * + * Domains 0: Accesses are not checked + * Domains 1: Accesses are not checked + * Domains 2: Accesses checked against permissions in the TLB + */ - mov r0, #0x1f /* Domains 0, 1 = client */ - mcr CP15_DACR(r0) /* Load domain access register */ + mov r0, #(DACR_MANAGER(0) | DACR_MANAGER(1) | DACR_CLIENT(2)) + mcr CP15_DACR(r0) /* Set domain access register */ /* Configure the system control register (see sctrl.h) */ @@ -668,7 +676,7 @@ __start: /* Finally branch to the OS entry point */ - mov lr, #0 + mov lr, #0 b os_start /* Text-section constants: |