Common ARM support

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@187 42af7a65-404d-4744-a932-0658087f49c3

16 files changed, 3169 insertions, 0 deletions

diff --git a/nuttx/arch/arm/src/dm320/Make.defs b/nuttx/arch/arm/src/dm320/Make.defs
new file mode 100644
index 000000000..8868ee275
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/Make.defs
@@ -0,0 +1,50 @@
+############################################################################
+# dm320/Make.defs
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= up_head.S
+
+CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S
+CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
+		  up_dataabort.c up_delay.c up_exit.c up_idle.c \
+		  up_initialize.c up_initialstate.c up_interruptcontext.c \
+		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
+		  up_reprioritizertr.c up_schedulesigaction.c \
+		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
+		  up_undefinedinsn.c up_usestack.c
+
+CHIP_ASRCS	= dm320_lowputc.S dm320_restart.S dm320_vectors.S
+CHIP_CSRCS	= dm320_allocateheap.c dm320_boot.c dm320_doirq.c dm320_irq.c \
+		  dm320_serial.c dm320_timerisr.c
+
diff --git a/nuttx/arch/arm/src/dm320/chip.h b/nuttx/arch/arm/src/dm320/chip.h
new file mode 100644
index 000000000..51a67e2fd
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/chip.h
@@ -0,0 +1,57 @@
+/************************************************************************************
+ * dm320/chip.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_CHIP_H
+#define __DM320_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include "dm320_memorymap.h"
+#include "dm320_uart.h"
+#include "dm320_timer.h"
+#include "dm320_intc.h"
+#include "dm320_gio.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#endif  /* __DM320_CHIP_H */
diff --git a/nuttx/arch/arm/src/dm320/dm320_allocateheap.c b/nuttx/arch/arm/src/dm320/dm320_allocateheap.c
new file mode 100644
index 000000000..f97a55c7d
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_allocateheap.c
@@ -0,0 +1,79 @@
+/************************************************************
+ * dm320/dm320_allocateheap.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "up_arch.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Private Definitions
+ ************************************************************/
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   The heap may be statically allocated by
+ *   defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE.  If these
+ *   are not defined, then this function will be called to
+ *   dynamically set aside the heap region.
+ *
+ ************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  up_ledon(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)g_heapbase;
+  *heap_size  = (DM320_SDRAM_VADDR + CONFIG_DRAM_SIZE) - g_heapbase;
+}
diff --git a/nuttx/arch/arm/src/dm320/dm320_boot.c b/nuttx/arch/arm/src/dm320/dm320_boot.c
new file mode 100644
index 000000000..46a39dfd2
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_boot.c
@@ -0,0 +1,227 @@
+/************************************************************************************
+ * dm320/dm320_boot.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+struct section_mapping_s
+{
+  uint32 physbase;   /* Physical address of the region to be mapped */
+  uint32 virtbase;   /* Virtual address of the region to be mapped */
+  uint32 mmuflags;   /* MMU settings for the region (e.g., cache-able) */
+  uint32 nsections;  /* Number of mappings in the region */
+};
+
+/************************************************************************************
+ * Public Variables
+ ************************************************************************************/
+
+extern uint32 _vector_start; /* Beginning of vector block */
+extern uint32 _vector_end;   /* End+1 of vector block */
+
+/************************************************************************************
+ * Private Variables
+ ************************************************************************************/
+
+static const struct section_mapping_s section_mapping[] =
+{
+  { DM320_PERIPHERALS_PSECTION, DM320_PERIPHERALS_VSECTION, 
+    DM320_PERIPHERALS_MMUFLAGS, DM320_PERIPHERALS_NSECTIONS},
+  { DM320_FLASH_PSECTION,       DM320_FLASH_VSECTION, 
+    DM320_FLASH_MMUFLAGS,       DM320_FLASH_NSECTIONS},
+  { DM320_CFI_PSECTION,         DM320_CFI_VSECTION, 
+    DM320_CFI_MMUFLAGS,         DM320_CFI_NSECTIONS},
+  { DM320_SSFDC_PSECTION,       DM320_SSFDC_VSECTION, 
+    DM320_SSFDC_MMUFLAGS,       DM320_SSFDC_NSECTIONS},
+  { DM320_CE1_PSECTION,         DM320_CE1_VSECTION, 
+    DM320_CE1_MMUFLAGS,         DM320_CE1_NSECTIONS},
+  { DM320_CE2_PSECTION,         DM320_CE2_VSECTION, 
+    DM320_CE2_MMUFLAGS,         DM320_CE2_NSECTIONS},
+  { DM320_VLYNQ_PSECTION,       DM320_VLYNQ_VSECTION, 
+    DM320_VLYNQ_MMUFLAGS,       DM320_VLYNQ_NSECTIONS},
+  { DM320_USBOTG_PSECTION,      DM320_USBOTG_VSECTION, 
+    DM320_USBOTG_MMUFLAGS,      DM320_USBOTG_NSECTIONS}
+};
+#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: up_setlevel1entry
+ ************************************************************************************/
+
+static inline void up_setlevel1entry(uint32 paddr, uint32 vaddr, uint32 mmuflags)
+{
+  uint32 *pgtable = (uint32*)PGTABLE_BASE_VADDR;
+  uint32  index   = vaddr >> 20;
+
+  /* Save the page table entry */
+
+  pgtable[index]  = (paddr | mmuflags);
+}
+
+/************************************************************************************
+ * Name: up_setlevel2coarseentry
+ ************************************************************************************/
+
+static inline void up_setlevel2coarseentry(uint32 ctabvaddr, uint32 paddr,
+                                           uint32 vaddr, uint32 mmuflags)
+{
+  uint32 *ctable  = (uint32*)ctabvaddr;
+  uint32  index;
+
+  /* The coarse table divides a 1Mb address space up into 256 entries, each
+   * corresponding to 4Kb of address space.  The coarse page table index is
+   * related to the offset from the beginning of 1Mb region.
+   */
+
+  index = (vaddr & 0x000ff000) >> 12;
+
+  /* Save the coarse table entry */
+
+  ctable[index] = (paddr | mmuflags);
+}
+
+/************************************************************************************
+ * Name: up_setupmappings
+ ************************************************************************************/
+
+static void up_setupmappings(void)
+{
+  int i, j;
+
+  for (i = 0; i < NMAPPINGS; i++)
+    {
+      uint32 sect_paddr = section_mapping[i].physbase;
+      uint32 sect_vaddr = section_mapping[i].virtbase;
+      uint32 mmuflags   = section_mapping[i].mmuflags;
+
+      for (j = 0; j < section_mapping[i].nsections; j++)
+        {
+          up_setlevel1entry(sect_paddr, sect_vaddr, mmuflags);
+          sect_paddr += SECTION_SIZE;
+          sect_vaddr += SECTION_SIZE;
+        }
+    }
+}
+
+/************************************************************************************
+ * Name: up_vectormapping
+ ************************************************************************************/
+
+static void up_vectormapping(void)
+{
+  uint32 vector_paddr = DM320_IRAM_PADDR;
+  uint32 vector_vaddr = DM320_VECTOR_VADDR;
+  uint32 end_paddr    = vector_paddr + DM320_IRAM_SIZE;
+
+  /* We want to keep our interrupt vectors and interrupt-related logic in zero-wait
+   * state internal RAM (IRAM).  The DM320 has 16Kb of IRAM positioned at physical
+   * address 0x0000:0000; we need to map this to 0xffff:0000.
+   */
+
+  while (vector_paddr < end_paddr)
+    {
+      up_setlevel2coarseentry(PGTABLE_COARSE_BASE_VADDR,
+                                  vector_paddr,
+                                  vector_vaddr,
+                                  MMU_L2_VECTORFLAGS);
+      vector_paddr += 4096;
+      vector_vaddr += 4096;
+    }
+
+  /* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
+
+  up_setlevel1entry(PGTABLE_COARSE_BASE_PADDR,
+                        DM320_VECTOR_VCOARSE,
+                        MMU_L1_VECTORFLAGS);
+}
+
+/************************************************************************************
+ * Name: up_copyvectorblock
+ ************************************************************************************/
+
+static void up_copyvectorblock(void)
+{
+  uint32 *src  = (uint32*)&_vector_start;
+  uint32 *end  = (uint32*)&_vector_end;
+  uint32 *dest = (uint32*)VECTOR_BASE;
+
+  while (src < end)
+    {
+      *dest++ = *src++;
+    }
+}
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+void up_boot(void)
+{
+  /* __start provided the basic MMU mappings for SDRAM.  Now provide mappings for all
+   * IO regions (Including the vector region).
+   */
+
+  up_setupmappings();
+
+  /* Provide a special mapping for the IRAM interrupt vector positioned in high
+   * memory.
+   */
+
+  up_vectormapping();
+
+  /* Setup up vector block.  _vector_start and _vector_end are exported from
+   * up_vector.S
+   */
+
+  up_copyvectorblock();
+}
diff --git a/nuttx/arch/arm/src/dm320/dm320_doirq.c b/nuttx/arch/arm/src/dm320/dm320_doirq.c
new file mode 100644
index 000000000..66b55f75f
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_doirq.c
@@ -0,0 +1,119 @@
+/********************************************************************************
+ * dm320/dm320_doirq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************/
+
+/********************************************************************************
+ * Included Files
+ ********************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/********************************************************************************
+ * Definitions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Functions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Funtions
+ ********************************************************************************/
+
+void up_doirq(uint32* regs)
+{
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  lib_lowprintf("Unexpected IRQ\n");
+  current_regs = regs;
+  PANIC(OSERR_ERREXCEPTION);
+#else
+  /* Decode the interrupt.  First, fetch the interrupt id register. */
+
+  uint16 irqentry = getreg16(DM320_INTC_IRQENTRY0);
+
+  /* The irqentry value is an offset into a table.  Zero means no interrupt. */
+
+  if (irqentry != 0)
+    {
+      /* If non-zero, then we can map the table offset into an IRQ number */
+
+      int irq = (irqentry >> 2) - 1;
+
+      /* Verify that the resulting IRQ number is valie */
+
+      if ((unsigned)irq < NR_IRQS)
+        {
+          /* Mask and acknowledge the interrupt */
+
+          up_maskack_irq(irq);
+
+          /* Current regs non-zero indicates that we are processing an interrupt;
+           * current_regs is also used to manage interrupt level context switches.
+           */
+
+          current_regs = regs;
+
+          /* Deliver the IRQ */
+
+          irq_dispatch(irq, regs);
+
+          /* Indicate that we are no long in an interrupt handler */
+
+          current_regs = NULL;
+
+          /* Unmask the last interrupt (global interrupts are still
+           * disabled.
+           */
+
+          up_enable_irq(irq);
+        }
+    }
+#endif
+}
diff --git a/nuttx/arch/arm/src/dm320/dm320_gio.h b/nuttx/arch/arm/src/dm320/dm320_gio.h
new file mode 100644
index 000000000..9b9a206f3
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_gio.h
@@ -0,0 +1,175 @@
+/************************************************************************************
+ * dm320/dm320_gio.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_DM320GIO_H
+#define __DM320_DM320GIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* General I/O Registers */
+
+#define DM320_GIO_DIR0    (DM320_PERIPHERALS_VADDR + 0x0580) /* GIO Direction Register 0 */
+#define DM320_GIO_DIR1    (DM320_PERIPHERALS_VADDR + 0x0582) /* GIO Direction Register 1 */
+#define DM320_GIO_DIR2    (DM320_PERIPHERALS_VADDR + 0x0584) /* GIO Direction Register 2 */
+#define DM320_GIO_INV0    (DM320_PERIPHERALS_VADDR + 0x0586) /* GIO Inversion Register 0 */
+#define DM320_GIO_INV1    (DM320_PERIPHERALS_VADDR + 0x0588) /* GIO Inversion Register 1 */
+#define DM320_GIO_INV2    (DM320_PERIPHERALS_VADDR + 0x058A) /* GIO Inversion Register 2 */
+#define DM320_GIO_BITSET0 (DM320_PERIPHERALS_VADDR + 0x058C) /* GIO Bit Set Register 0 */
+#define DM320_GIO_BITSET1 (DM320_PERIPHERALS_VADDR + 0x058E) /* GIO Bit Set Register 1 */
+#define DM320_GIO_BITSET2 (DM320_PERIPHERALS_VADDR + 0x0590) /* GIO Bit Set Register 2 */
+#define DM320_GIO_BITCLR0 (DM320_PERIPHERALS_VADDR + 0x0592) /* GIO Bit Clear Register 0 */
+#define DM320_GIO_BITCLR1 (DM320_PERIPHERALS_VADDR + 0x0594) /* GIO Bit Clear Register 1 */
+#define DM320_GIO_BITCLR2 (DM320_PERIPHERALS_VADDR + 0x0596) /* GIO Bit Clear Register 2 */
+#define DM320_GIO_IRQPORT (DM320_PERIPHERALS_VADDR + 0x0598) /* GIO IRQ Port Setting Register */
+#define DM320_GIO_IRQEDGE (DM320_PERIPHERALS_VADDR + 0x059A) /* GIO IRQ Edge Setting Register */
+#define DM320_GIO_CHAT0   (DM320_PERIPHERALS_VADDR + 0x059C) /* GIO Chatter Setting Register 0 */
+#define DM320_GIO_CHAT1   (DM320_PERIPHERALS_VADDR + 0x059E) /* GIO Chatter Setting Register 1 */
+#define DM320_GIO_CHAT2   (DM320_PERIPHERALS_VADDR + 0x05A0) /* GIO Chatter Setting Register 2 */
+#define DM320_GIO_NCHAT   (DM320_PERIPHERALS_VADDR + 0x05A2) /* GIO Chatter Value Register */
+#define DM320_GIO_FSEL0   (DM320_PERIPHERALS_VADDR + 0x05A4) /* GIO Function Select Register 0 */
+#define DM320_GIO_FSEL1   (DM320_PERIPHERALS_VADDR + 0x05A6) /* GIO Function Select Register 1 */
+#define DM320_GIO_FSEL2   (DM320_PERIPHERALS_VADDR + 0x05A8) /* GIO Function Select Register 2 */
+#define DM320_GIO_FSEL3   (DM320_PERIPHERALS_VADDR + 0x05AA) /* GIO Function Select Register 3 */
+
+/* Macros for GIO access */
+
+#define _GIO_READ_REG(pin, reg0, reg1, reg2, bval) \
+  do { \
+    register uint32 _reg; register int _pin; \
+    if ((pin) < 16) { _reg = (reg0); _pin = (pin); } \
+    else if ((pin) < 32) { _reg = (reg1); _pin = ((pin) - 16); } \
+    else { _reg = (reg2); _pin = ((pin) - 32); } \
+    bval = ((getreg16(_reg) & (1<<_pin)) != 0); \
+  }
+
+#define _GIO_SET_REG(pin, reg0, reg1, reg2) \
+  do { \
+    register uint32 _reg; register int _pin; \
+    if ((pin) < 16) { _reg = (reg0); _pin = (pin); } \
+    else if ((pin) < 32) { _reg = (reg1); _pin = ((pin) - 16); } \
+    else { _reg = (reg2); _pin = ((pin) - 32); } \
+    putreg16((getreg16(_reg) | (1 << _pin)), _reg)); \
+  } while (0)
+
+#define _GIO_CLEAR_REG(pin, reg0, reg1, reg2) \
+  do { \
+    register uint32 _reg; register int _pin; \
+    if ((pin) < 16) { _reg = (reg0); _pin = (pin); } \
+    else if ((pin) < 32) { _reg = (reg1); _pin = ((pin) - 16); } \
+    else { _reg = (reg2); _pin = ((pin) - 32); } \
+    putreg16((getreg16(_reg) & ~(1 << _pin)), _reg)); \
+  } while (0)
+
+/* Select GIO input or output */
+
+#define GIO_INPUT(pin) \
+  _GIO_SET_REG((pin), DM320_GIO_DIR0, DM320_GIO_DIR1, DM320_GIO_DIR2)
+#define GIO_OUTPUT(pin) \
+  _GIO_CLEAR_REG((pin), DM320_GIO_DIR0, DM320_GIO_DIR1, DM320_GIO_DIR2)
+
+/* Select inverted or non-inverted GIO */
+
+#define GIO_INVERTED(pin) \
+  _GIO_SET_REG((pin), DM320_GIO_INV0, DM320_GIO_INV1, DM320_GIO_INV2)
+#define GIO_NONINVERTED(pin) \
+  _GIO_CLEAR_REG((pin), DM320_GIO_INV0, DM320_GIO_INV1, DM320_GIO_INV2)
+
+/* Set and clear outputs */
+
+#define GIO_SET_OUTPUT(pin) \
+  _GIO_SET_REG((pin), DM320_GIO_BITSET0, DM320_GIO_BITSET1, DM320_GIO_BITSET2)
+#define GIO_CLEAR_OUTPUT(pin) \
+ _GIO_SET_REG((pin), DM320_GIO_BITCLR0, DM320_GIO_BITCLR1, DM320_GIO_BITCLR2)
+
+/* Read input */
+
+#define GIO_READ_INPUT(pin, bval) \
+  _GIO_READ_REG((pin), DM320_GIO_BITSET0, DM320_GIO_BITSET1, DM320_GIO_BITSET2, (bval))
+
+/* Configure GIO pins */
+
+#define _GIO_SET_CONFIG(reg, sh, val) \
+    putreg16(((getreg16(reg) & ~(3 << sh)) | (val << sh)), (reg))
+
+#define GIO_CONFIGURE(pin, val) \
+  do {\
+    if ((pin) < 10) _GIO_SET_CONFIG(DM320_GIO_FSEL0, 0, (val)); \
+    else if ((pin) < 17) _GIO_SET_CONFIG(DM320_GIO_FSEL0, 2*((pin)-9), (val)); \
+    else if ((pin) < 25) _GIO_SET_CONFIG(DM320_GIO_FSEL1, 2*((pin)-17), (val)); \
+    else if ((pin) < 33) _GIO_SET_CONFIG(DM320_GIO_FSEL2, 2*((pin)-25), (val)); \
+    else _GIO_SET_CONFIG(DM320_GIO_FSEL3, 2*((pin)-33), (val)); \
+  }
+
+/* Configure GIO interrupts (pins 1-15) */
+
+#define GIO_INTERRUPT(pin) \
+  if (pin < 16) putreg16((getreg16(DM320_GIO_IRQPORT) | (1<<(pin))), DM320_GIO_IRQPORT)
+#define GIO_NONINTERRUPT(pin) \
+  if (pin < 16) putreg16((getreg16(DM320_GIO_IRQPORT) & ~(1<<(pin))), DM320_GIO_IRQPORT)
+#define GIO_FALLINGEDGE(pin) \
+  if (pin < 16) { \
+    putreg16((getreg16(DM320_GIO_IRQEDGE) & ~(1<<(pin))), DM320_GIO_IRQEDGE) \
+    putreg16((getreg16(DM320_GIO_INV0) & ~(1<<(pin))), DM320_GIO_INV0); \
+  }
+#define GIO_RISINGEDGE(pin) \
+  if (pin < 16) { \
+    putreg16((getreg16(DM320_GIO_IRQEDGE) & ~(1<<(pin))), DM320_GIO_IRQEDGE); \
+    putreg16((getreg16(DM320_GIO_INV0) | (1<<(pin))), DM320_GIO_INV0); \
+  }
+#define GIO_BOTHEDGES(pin) \
+  if (pin < 16) { \
+    putreg16((getreg16(DM320_GIO_IRQEDGE) | (1<<(pin))), DM320_GIO_IRQEDGE); \
+    putreg16((getreg16(DM320_GIO_INV0) & ~(1<<(pin))), DM320_GIO_INV0); \
+  }
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_DM320_GIO_H */
diff --git a/nuttx/arch/arm/src/dm320/dm320_intc.h b/nuttx/arch/arm/src/dm320/dm320_intc.h
new file mode 100644
index 000000000..9795718b2
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_intc.h
@@ -0,0 +1,105 @@
+/************************************************************************************
+ * dm320/dm320_intc.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_DM320_INTC_H
+#define __DM320_DM320_INTC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Interrupt Controller Registers */
+
+#define DM320_INTC_FIQ0       (DM320_PERIPHERALS_VADDR + 0x0500) /* FIQ Interrupt Flag Register #0 */
+#define DM320_INTC_FIQ1       (DM320_PERIPHERALS_VADDR + 0x0502) /* FIQ Interrupt Flag Register #1 */
+#define DM320_INTC_FIQ2       (DM320_PERIPHERALS_VADDR + 0x0504) /* FIQ Interrupt Flag Register #2 */
+#define DM320_INTC_IRQ0       (DM320_PERIPHERALS_VADDR + 0x0508) /* IRQ Interrupt Flag Register #0 */
+#define DM320_INTC_IRQ1       (DM320_PERIPHERALS_VADDR + 0x050A) /* IRQ Interrupt Flag Register #1 */
+#define DM320_INTC_IRQ2       (DM320_PERIPHERALS_VADDR + 0x050C) /* IRQ Interrupt Flag Register #2 */
+#define DM320_INTC_FIQENTRY0  (DM320_PERIPHERALS_VADDR + 0x0510) /* FIQ Entry Address Register #0 */
+#define DM320_INTC_FIQENTRY1  (DM320_PERIPHERALS_VADDR + 0x0512) /* FIQ Entry Address Register #1 */
+#define DM320_INTC_FIQENTLCK0 (DM320_PERIPHERALS_VADDR + 0x0514) /* FIQ Lock Entry Address Register #1 */
+#define DM320_INTC_FIQENTLCK1 (DM320_PERIPHERALS_VADDR + 0x0516) /* FIQ Lock Entry Address Register #1 */
+#define DM320_INTC_IRQENTRY0  (DM320_PERIPHERALS_VADDR + 0x0518) /* IRQ Entry Address Register #0 */
+#define DM320_INTC_IRQENTRY1  (DM320_PERIPHERALS_VADDR + 0x051A) /* IRQ Entry Address Register #1 */
+#define DM320_INTC_IRQENTLCK0 (DM320_PERIPHERALS_VADDR + 0x051C) /* IRQ Lock Entry Address Register #1 */
+#define DM320_INTC_IRQENTLCK1 (DM320_PERIPHERALS_VADDR + 0x051E) /* Lock Entry Address Register #1 */
+#define DM320_INTC_FISEL0     (DM320_PERIPHERALS_VADDR + 0x0520) /* FIQ select register #0 */
+#define DM320_INTC_FISEL1     (DM320_PERIPHERALS_VADDR + 0x0522) /* FIQ select register #1 */
+#define DM320_INTC_FISEL2     (DM320_PERIPHERALS_VADDR + 0x0524) /* FIQ select register #2 */
+#define DM320_INTC_EINT0      (DM320_PERIPHERALS_VADDR + 0x0528) /* Interrupt Enable Register #0 */
+#define DM320_INTC_EINT1      (DM320_PERIPHERALS_VADDR + 0x052A) /* Interrupt Enable Register #1 */
+#define DM320_INTC_EINT2      (DM320_PERIPHERALS_VADDR + 0x052C) /* Interrupt Enable Register #2 */
+#define DM320_INTC_INTRAW     (DM320_PERIPHERALS_VADDR + 0x0530) /* Interrupt Raw Register */
+#define DM320_INTC_EABASE0    (DM320_PERIPHERALS_VADDR + 0x0538) /* Entry Table Base Address Register #0 */
+#define DM320_INTC_EABASE1    (DM320_PERIPHERALS_VADDR + 0x053A) /* Entry Table Base Address Register #1 */
+#define DM320_INTC_INTPRI00   (DM320_PERIPHERALS_VADDR + 0x0540) /* Interrupt Priority Register #0 */
+#define DM320_INTC_INTPRI01   (DM320_PERIPHERALS_VADDR + 0x0542) /* Interrupt Priority Register #1 */
+#define DM320_INTC_INTPRI02   (DM320_PERIPHERALS_VADDR + 0x0544) /* Interrupt Priority Register #2 */
+#define DM320_INTC_INTPRI03   (DM320_PERIPHERALS_VADDR + 0x0546) /* Interrupt Priority Register #3 */
+#define DM320_INTC_INTPRI04   (DM320_PERIPHERALS_VADDR + 0x0548) /* Interrupt Priority Register #4 */
+#define DM320_INTC_INTPRI05   (DM320_PERIPHERALS_VADDR + 0x054A) /* Interrupt Priority Register #5 */
+#define DM320_INTC_INTPRI06   (DM320_PERIPHERALS_VADDR + 0x054C) /* Interrupt Priority Register #6 */
+#define DM320_INTC_INTPRI07   (DM320_PERIPHERALS_VADDR + 0x054E) /* Interrupt Priority Register #7 */
+#define DM320_INTC_INTPRI08   (DM320_PERIPHERALS_VADDR + 0x0550) /* Interrupt Priority Register #8 */
+#define DM320_INTC_INTPRI09   (DM320_PERIPHERALS_VADDR + 0x0552) /* Interrupt Priority Register #9 */
+#define DM320_INTC_INTPRI10   (DM320_PERIPHERALS_VADDR + 0x0554) /* Interrupt Priority Register #10 */
+#define DM320_INTC_INTPRI11   (DM320_PERIPHERALS_VADDR + 0x0556) /* Interrupt Priority Register #11 */
+#define DM320_INTC_INTPRI12   (DM320_PERIPHERALS_VADDR + 0x0558) /* Interrupt Priority Register #12 */
+#define DM320_INTC_INTPRI13   (DM320_PERIPHERALS_VADDR + 0x055A) /* Interrupt Priority Register #13 */
+#define DM320_INTC_INTPRI14   (DM320_PERIPHERALS_VADDR + 0x055C) /* Interrupt Priority Register #14 */
+#define DM320_INTC_INTPRI15   (DM320_PERIPHERALS_VADDR + 0x055E) /* Interrupt Priority Register #15 */
+#define DM320_INTC_INTPRI16   (DM320_PERIPHERALS_VADDR + 0x0560) /* Interrupt Priority Register #16 */
+#define DM320_INTC_INTPRI17   (DM320_PERIPHERALS_VADDR + 0x0562) /* Interrupt Priority Register #17 */
+#define DM320_INTC_INTPRI18   (DM320_PERIPHERALS_VADDR + 0x0564) /* Interrupt Priority Register #18 */
+#define DM320_INTC_INTPRI19   (DM320_PERIPHERALS_VADDR + 0x0566) /* Interrupt Priority Register #19 */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_DM320_INTC_H */
diff --git a/nuttx/arch/arm/src/dm320/dm320_irq.c b/nuttx/arch/arm/src/dm320/dm320_irq.c
new file mode 100644
index 000000000..692d06a98
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_irq.c
@@ -0,0 +1,245 @@
+/************************************************************
+ * dm320/dm320_irq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/************************************************************
+ * Public Data
+ ************************************************************/
+
+uint32 *current_regs;
+
+/************************************************************
+ * Private Data
+ ************************************************************/
+
+/* The value of _vflashstart is defined in ld.script.  It
+ * could be hard-coded because we know that correct IRAM
+ * area is 0xffc00000.
+ */
+
+extern int _svectors; /* Type does not matter */
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_irqinitialize
+ ************************************************************/
+
+void up_irqinitialize(void)
+{
+  /* Clear, disable and configure all interrupts. */
+
+  putreg16(0, DM320_INTC_EINT0);      /* Mask all IRQs/FIQs */
+  putreg16(0, DM320_INTC_EINT1);
+  putreg16(0, DM320_INTC_EINT2);
+
+  putreg16(0, DM320_INTC_INTRAW);     /* No masked interrupts in status */
+
+  putreg16(0, DM320_INTC_FISEL0);     /* No FIQs */
+  putreg16(0, DM320_INTC_FISEL1);
+  putreg16(0, DM320_INTC_FISEL2);
+
+  putreg16(0xffff, DM320_INTC_FIQ0);  /* Clear all pending FIQs */
+  putreg16(0xffff, DM320_INTC_FIQ1);
+  putreg16(0xffff, DM320_INTC_FIQ2);
+
+  putreg16(0xffff, DM320_INTC_IRQ0);  /* Clear all pending IRQs */
+  putreg16(0xffff, DM320_INTC_IRQ1);
+  putreg16(0xffff, DM320_INTC_IRQ2);
+
+ /* Make sure that the base addresses are zero and that
+  * the table increment is 4 bytes.
+  */
+
+  putreg16(0, DM320_INTC_EABASE0);
+  putreg16(0, DM320_INTC_EABASE1);
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  irqrestore(SVC_MODE | PSR_F_BIT);
+#endif
+}
+
+/************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ************************************************************/
+
+void up_disable_irq(int irq)
+{
+  /* Disable the interrupt by clearing the corresponding bit in
+   * the IRQ enable register.
+   */
+
+  if (irq < 16)
+    {
+      /* IRQs0-15 are controlled by the IRQ0 enable register
+       * Clear the associated bit to disable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT0) & ~(1 << irq)), DM320_INTC_EINT0);
+    }
+  else if (irq < 32)
+    {
+      /* IRQs16-31 are controlled by the IRQ1 enable register
+       * Clear the associated bit to disable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT1) & ~(1 << (irq-16))), DM320_INTC_EINT1);
+    }
+  else
+    {
+      /* IRQs32- are controlled by the IRQ2 enable register
+       * Clear the associated bit to disable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT2) & ~(1 << (irq-32))), DM320_INTC_EINT2);
+    }
+}
+
+/************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ************************************************************/
+
+void up_enable_irq(int irq)
+{
+  /* Enable the interrupt by setting the corresponding bit in
+   * the IRQ enable register.
+   */
+
+  if (irq < 16)
+    {
+      /* IRQs0-15 are controlled by the IRQ0 enable register
+       * Set the associated bit to enable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT0) | (1 << irq)), DM320_INTC_EINT0);
+    }
+  else if (irq < 32)
+    {
+      /* IRQs16-31 are controlled by the IRQ1 enable register
+       * Set the associated bit to enable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT1) | (1 << (irq-16))), DM320_INTC_EINT1);
+    }
+  else
+    {
+      /* IRQs32- are controlled by the IRQ2 enable register
+       * Set the associated bit to enable the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT2) | (1 << (irq-32))), DM320_INTC_EINT2);
+    }
+}
+
+/************************************************************
+ * Name: up_maskack_irq
+ *
+ * Description:
+ *   Mask the IRQ and acknowledge it
+ *
+ ************************************************************/
+
+void up_maskack_irq(int irq)
+{
+  /* Disable the interrupt by clearing the corresponding bit in
+   * the IRQ enable register.  And acknowlege it by setting the
+   * corresponding bit in the IRQ status register.
+   */
+
+  if (irq < 16)
+    {
+      /* IRQs0-15 are controlled by the IRQ0 enable register
+       * Clear the associated enable bit to disable the interrupt
+       * Set the associated status bit to clear the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT0) & ~(1<< irq)), DM320_INTC_EINT0);
+      putreg16((1 << irq), DM320_INTC_IRQ0);
+    }
+  else if (irq < 32)
+    {
+      /* IRQs16-31 are controlled by the IRQ1 enable register
+       * Clear the associated enable bit to disable the interrupt
+       * Set the associated status bit to clear the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT1) & ~(1<< (irq-16))), DM320_INTC_EINT1);
+      putreg16((1 << (irq-16)), DM320_INTC_IRQ1);
+    }
+  else
+    {
+      /* IRQs32- are controlled by the IRQ2 enable register
+       * Clear the associated enable bit to disable the interrupt
+       * Set the associated status bit to clear the interrupt
+       */
+
+      putreg16((getreg16(DM320_INTC_EINT2) & ~(1<< (irq-32))), DM320_INTC_EINT2);
+      putreg16((1 << (irq-32)), DM320_INTC_IRQ2);
+    }
+}
diff --git a/nuttx/arch/arm/src/dm320/dm320_lowputc.S b/nuttx/arch/arm/src/dm320/dm320_lowputc.S
new file mode 100644
index 000000000..c27918262
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_lowputc.S
@@ -0,0 +1,127 @@
+/**************************************************************************
+ * dm320/dm320_lowputc.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ **************************************************************************/
+
+/* This assembly language version has the advantage that it can does not
+ * require a C stack and uses only r0-r1.  Hence it can be used during
+ * early boot phases.
+ */
+
+	.text
+	.global	up_lowputc
+	.type	up_lowputc, function
+up_lowputc:
+	/* On entry, r0 holds the character to be printed */
+
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+	ldr	r2, =DM320_UART0_REGISTER_BASE	/* r2=UART0 base */
+#else
+	ldr	r2, =DM320_UART1_REGISTER_BASE	/* r2=UART1 base */
+#endif
+
+	/* Poll the TX fifo trigger level bit of the UART_SSR
+	 * register.  When the bit is non-zero, the TX FIFO is no
+	 * longer full
+	 */
+
+1:	ldrh	r1, [r2, #UART_SR]
+	tst	r1, #UART_SR_TFTI
+	beq	1b
+
+	/* Send the character by writing it into the UART_DTRR
+	 * register.
+	 */
+
+	strh	r0, [r2, #UART_DTRR]
+
+	/* Wait for the tranmsit regiser to be emptied. This is
+	 * detemined when TX register empty bit of the SR is zero.
+	 */
+
+2:	ldrh	r1, [r2, #UART_SR]
+	tst	r1, #UART_SR_TREF
+	bne	2b
+
+	/* If the character that we just sent was a linefeed,
+	 * then send a carriage return as well.
+	 */
+
+	teq     r0, #'\n'
+	moveq   r0, #'\r'
+	beq     1b
+
+	/* And return */
+
+	mov     pc, lr
+
diff --git a/nuttx/arch/arm/src/dm320/dm320_memorymap.h b/nuttx/arch/arm/src/dm320/dm320_memorymap.h
new file mode 100644
index 000000000..d53de2f96
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_memorymap.h
@@ -0,0 +1,238 @@
+/************************************************************************************
+ * dm320/dm320_memorymap.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_MEMORYMAP_H
+#define __DM320_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Mapped base of all registers *****************************************************/
+
+/* DM320 Physical Memory Map, where:
+ *
+ *   CW = cachable with write buffering
+ *   -W = Write buffering only
+ *   -- = Neither
+ *
+ * The DM320 only has a single control line for external peripherals.
+ * To support more than one peripheral, most hardware will use an 
+ * external memory decode logic, so that physical memory regions is
+ * in the hardware specific files dm320-*.h
+ */
+
+#if CONFIG_DRAM_START != 0x01000000
+# error "Invalid setting for CONFIG_DRAM_START
+#endif
+
+/* Section/Region Name             Phys Address    Size  TLB Enty        CW */
+#define DM320_PERIPHERALS_PSECTION   0x00000000 /*   1Mb   1 section     -- */
+#define   DM320_IRAM_PADDR           0x00000000 /*  16Kb   1 large page  CW */
+#define   DM320_PERIPHERALS_PADDR    0x00030000 /*   4Kb   1 small pages -- */
+#define   DM320_DSP_ONCHIP_RAM_PADDR 0x00040000 /* 128Kb   1 large page  -- */
+#define   DM320_AHB_PADDR            0x00060000 /*   4Kb   1 small page  -- */
+#define   DM320_COPRO_SUB_PADDR      0x00080000 /* 128Kb                 -- */
+#define DM320_FLASH_PSECTION         0x00100000 /*  16Mb  many sections  -- */
+#define   DM320_EXT_MEM_PADDR        0x00100000 /*  16Mb flash           -- */
+#define DM320_SDRAM_PSECTION         0x01000000 /* 496Mb  many section   -- */
+#define   DM320_SDRAM_PADDR          0x01000000 /* 496Mb  many sections  CW */
+#define DM320_CFI_PSECTION           0x40000000 /*  16Mb  16 sections    -- */
+#define   DM320_CFI_PADDR            0x40000000 /*  16Mb  16 sections    -- */
+#define DM320_SSFDC_PSECTION         0x48000000 /*  16Mb  16 sections    -- */
+#define   DM320_SSFDC_PADDR          0x48000000 /*  16Mb  16 sections    -- */
+#define DM320_CE1_PSECTION           0x50000000 /*  16Mb  16 sections    -- */
+#define   DM320_CE1_PADDR            0x50000000 /*  16Mb  16 sections    -- */
+#define DM320_CE2_PSECTION           0x60000000 /*  16Mb  16 sections    -- */
+#define   DM320_CE2_PADDR            0x60000000 /*  16Mb  16 sections    -- */
+#define DM320_VLYNQ_PSECTION         0x70000000 /*  64MB  64 sections    -- */
+#define   DM320_VLYNQ_PADDR          0x70000000 /*  64MB  64 sections    -- */
+#define DM320_USBOTG_PSECTION        0x80000000 /*   1Mb   1 section     -- */
+#define   DM320_USBOTG_PADDR         0x80000000 /*   1Kb   1 small page  -- */
+
+/* Sizes of sections/regions */
+
+/* Section / Region Name             Size */
+#define DM320_PERIPHERALS_NSECTIONS  1          /*   1Mb   1 section     -- */
+#define   DM320_IRAM_SIZE            (16*1024)
+#define   DM320_PERIPHERALS_SIZE     (4*1024)
+#define   DM320_DSP_ONCHIP_RAM_SIZE  (128*1024)
+#define   DM320_AHB_SIZE             (4*1024)
+#define   DM320_COPRO_SUB_SIZE       (128*1024)
+#define DM320_FLASH_NSECTIONS        16         /*  16Mb  16 sections    -- */
+#define   DM320_EXT_MEM_SIZE         (16*1024*1024)
+#define DM320_CFI_NSECTIONS          16         /*  16Mb  16 sections    -- */
+#define   DM320_CFI_SIZE             (16*1024*1024)
+#define DM320_SSFDC_NSECTIONS        16         /*  16Mb  16 sections    -- */
+#define   DM320_SSFDC_SIZE           (16*1024*1024) 
+#define DM320_CE1_NSECTIONS          16         /*  16Mb  16 sections    -- */
+#define   DM320_CE1_SIZE             (16*1024*1024)
+#define DM320_CE2_NSECTIONS          16         /*  16Mb  16 sections    -- */
+#define   DM320_CE2_SIZE             (16*1024*1024)
+#define DM320_VLYNQ_NSECTIONS        64         /*  64MB  64 sections    -- */
+#define   DM320_VLYNQ_SIZE           (64*1024*1024)
+#define DM320_USBOTG_NSECTIONS       1          /*   1Mb   1 section     -- */
+#define   DM320_USBOTG_SIZE          (1024)
+
+/* DM320 Virtual Memory Map */
+
+#if CONFIG_DRAM_VSTART != 0x00000000
+# error "Invalid setting for CONFIG_DRAM_VSTART
+#endif
+
+/* Section/Region Name               Virt Address  End        Size  CW */
+#define DM320_SDRAM_VSECTION         0x00000000 /* 0x1effffff 496Mb CW */
+#define   DM320_SDRAM_VADDR          0x00000000 /* 0x1effffff 496Mb CW */
+                                  /* 0x1f000000    0xdfffffff UNMAPPED */
+#define DM320_FLASH_VSECTION         0xc0000000 /* 0xc0ffffff  16Mb -- */
+#define   DM320_EXT_MEM_VADDR        0xc0000000 /* 0xc0ffffff  16Mb -- */
+#define DM320_CFI_VSECTION           0xc4000000 /* 0xc4ffffff  16Mb -- */
+#define   DM320_CFI_VADDR            0xc4000000 /* 0xc4ffffff  16Mb -- */
+#define DM320_SSFDC_VSECTION         0xc8000000 /* 0xc8ffffff  16Mb -- */
+#define   DM320_SSFDC_VADDR          0xc8000000 /* 0xc8ffffff  16Mb -- */
+#define DM320_CE1_VSECTION           0xcc000000 /* 0xccffffff  16Mb -- */
+#define   DM320_CE1_VADDR            0xcc000000 /* 0xccffffff  16Mb -- */
+#define DM320_CE2_VSECTION           0xd0000000 /* 0xd0ffffff  16Mb -- */
+#define   DM320_CE2_VADDR            0xd0000000 /* 0xd0ffffff  16Mb -- */
+#define DM320_USBOTG_VSECTION        0xd4000000 /* 0xd40fffff   1Mb -- */
+#define   DM320_USBOTG_VADDR         0xd4000000 /* 0xd40003ff   1Kb -- */
+#define DM320_VLYNQ_VSECTION         0xe0000000 /* 0xefffffff  64Mb -- */
+#define   DM320_VLYNQ_VADDR          0xe0000000 /* 0xefffffff  64Mb -- */
+#define DM320_PERIPHERALS_VSECTION   0xf0000000 /* 0xf00fffff   1Mb -- */
+#define   DM320_IRAM_VADDR           0xf0000000 /* 0xf0003fff  16Kb -- */
+#define   DM320_PERIPHERALS_VADDR    0xf0030000 /* 0xf0030fff   4Kb -- */
+#define   DM320_DSP_ONCHIP_RAM_VADDR 0xf0040000 /* 0xf005ffff 128Kb -- */
+#define   DM320_AHB_VADDR            0xf0060000 /* 0xf0060fff   4Kb -- */
+#define   DM320_COPRO_SUB_VADDR      0xf0080000 /* 0xf009ffff 128Kb -- */
+                                  /* 0xf0100000    0xffefffff UNMAPPED */
+#define DM320_VECTOR_VCOARSE         0xfff00000 /* 0xffffffff   1Mb -- */
+                                  /* 0xfff00000    0xfffeffff UNMAPPED */
+#define   DM320_VECTOR_VADDR         0xffff0000 /* 0xffff3fff  16Kb -- */
+                                  /* 0xffff4000    0xffffffff UNMAPPED */
+
+/* The NuttX entry point starts at an offset from the virtual beginning of DRAM.
+ * This offset reserves space for the MMU page cache.
+ */
+
+#define NUTTX_START_VADDR            (DM320_SDRAM_VADDR+PGTABLE_SIZE)
+
+/* Section MMU Flags                 Flags              CW */
+#define DM320_FLASH_MMUFLAGS         MMU_IOFLAGS     /* -- */
+#define DM320_CFI_MMUFLAGS           MMU_IOFLAGS     /* -- */
+#define DM320_SSFDC_MMUFLAGS         MMU_IOFLAGS     /* -- */
+#define DM320_CE1_MMUFLAGS           MMU_IOFLAGS     /* -- */
+#define DM320_CE2_MMUFLAGS           MMU_IOFLAGS     /* -- */
+#define DM320_VLYNQ_MMUFLAGS         MMU_IOFLAGS     /* -- */
+#define DM320_USBOTG_MMUFLAGS        MMU_IOFLAGS     /* -- */
+#define DM320_PERIPHERALS_MMUFLAGS   MMU_IOFLAGS     /* -- */
+
+/* 16Kb of memory is reserved at the beginning of SDRAM to hold the
+ * page table for the virtual mappings.  A portion of this table is
+ * not accessible in the virtual address space (for normal operation).
+ * We will reuse this memory for coarse page tables as follows:
+ */
+
+#define PGTABLE_BASE_PADDR          DM320_SDRAM_PADDR
+#define PGTABLE_SDRAM_PADDR         PGTABLE_BASE_PADDR
+#define PGTABLE_COARSE_BASE_PADDR   (PGTABLE_BASE_PADDR+0x00000800)
+#define PGTABLE_COARSE_END_PADDR    (PGTABLE_BASE_PADDR+0x00003000)
+#define PTTABLE_PERIPHERALS_PADDR   (PGTABLE_BASE_PADDR+0x00003000)
+#define PGTABLE_END_PADDR           (PGTABLE_BASE_PADDR+0x00004000)
+
+#define PGTABLE_BASE_VADDR          DM320_SDRAM_VADDR
+#define PGTABLE_SDRAM_VADDR         PGTABLE_BASE_VADDR
+#define PGTABLE_COARSE_BASE_VADDR   (PGTABLE_BASE_VADDR+0x00000800)
+#define PGTABLE_COARSE_END_VADDR    (PGTABLE_BASE_VADDR+0x00003000)
+#define PTTABLE_PERIPHERALS_VADDR   (PGTABLE_BASE_VADDR+0x00003000)
+#define PGTABLE_END_VADDR           (PGTABLE_BASE_VADDR+0x00004000)
+
+#define PGTBALE_COARSE_TABLE_SIZE   (4*256)
+#define PGTABLE_COARSE_ALLOC        (PGTABLE_COARSE_END_VADDR-PGTABLE_COARSE_BASE_VADDR)
+#define PGTABLE_NCOARSE_TABLES      (PGTABLE_COARSE_SIZE / PGTBALE_COARSE_TABLE_ALLOC)
+
+/* This is the base address of the interrupt vectors on the ARM926 */
+
+#define VECTOR_BASE                 DM320_VECTOR_VADDR
+
+/* DM320 Peripheral Registers */
+
+#define DM320_TIMER0_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0000) /* Timer 0 */
+#define DM320_TIMER1_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0080) /* Timer 1 */
+#define DM320_TIMER2_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0100) /* Timer 2 */
+#define DM320_TIMER3_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0180) /* Timer 3 */
+#define DM320_SERIAL0_REGISTER_BASE (DM320_PERIPHERALS_VADDR + 0x0200) /* Serial port 0 */
+#define DM320_SERIAL1_REGISTER_BASE (DM320_PERIPHERALS_VADDR + 0x0280) /* Serial port 1 */
+#define DM320_UART0_REGISTER_BASE   (DM320_PERIPHERALS_VADDR + 0x0300) /* UART 0 */
+#define DM320_UART1_REGISTER_BASE   (DM320_PERIPHERALS_VADDR + 0x0380) /* UART 1 */
+#define DM320_WDT_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0400) /* Watchdog timer */
+#define DM320_MMCSD_REGISTER_BASE   (DM320_PERIPHERALS_VADDR + 0x0480) /* MMC/SD */
+#define DM320_INTC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0500) /* Interrupt controller */
+#define DM320_GIO_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0580) /* GIO */
+#define DM320_DSPC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0600) /* DSP controller */
+#define DM320_OSD_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0680) /* OSD */
+#define DM320_CCDC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0700) /* CCD controller */
+#define DM320_VENC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0800) /* Video encoder */
+#define DM320_CLKC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0880) /* Clock controller */
+#define DM320_BUSC_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0900) /* Bus controller */
+#define DM320_SDRAMC_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0980) /* SDRAM controller */
+#define DM320_EMIF_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0A00) /* External memory interface */
+#define DM320_PREV_REGISTER_BASE    (DM320_PERIPHERALS_VADDR + 0x0A80) /* Preview engine */
+#define DM320_AF_REGISTER_BASE      (DM320_PERIPHERALS_VADDR + 0x0B80) /* Hardware 3A (AF/AE/AWB) */
+#define DM320_MSTICK_REGISTER_BASE  (DM320_PERIPHERALS_VADDR + 0x0C80) /* Memory stick */
+#define DM320_I2C_REGISTER_BASE     (DM320_PERIPHERALS_VADDR + 0x0D80) /* I2C */
+#define DM320_USB_REGISTER_BASE     (DM320_USBOTG_VADDR + 0x0000)      /* USB full speed OTG */
+#define DM320_USBDMA_REGISTER_BASE  (DM320_USBOTG_VADDR + 0x0200)      /* USB DMA */
+#define DM320_VLYNQ_REGISTER_BASE   (DM320_AHB_VADDR + 0x0300)         /* VLYNQ */
+#define DM320_AHBBUSC_REGISTER_BASE (DM320_AHB_VADDR + 0x0F00)         /* AHBBUSC */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_MEMORYMAP_H */
diff --git a/nuttx/arch/arm/src/dm320/dm320_restart.S b/nuttx/arch/arm/src/dm320/dm320_restart.S
new file mode 100644
index 000000000..1ce9e373f
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_restart.S
@@ -0,0 +1,136 @@
+/********************************************************************
+ * dm320/dm320_restart.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/* Since the page table is closely related to the NuttX base
+ * address, we can convert the page table base address to the
+ * base address of the section containing both.
+ */
+
+	.macro	mksection, section, pgtable
+	bic	\section, \pgtable, #0x000ff000
+	.endm
+
+/**************************************************************************
+ * Name: up_restart
+ **************************************************************************/
+
+	.text
+	.globl	up_restart
+	.type	up_restart, %function
+up_restart:
+	/* Make sure that we are in SVC mode with all IRQs disabled */
+
+	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
+	msr	cpsr_c, r0
+
+	/* Create identity mapping for first MB section to support
+	 * this re-start logic executing out of the physical address
+	 * space.
+	 */
+
+	mksection r0, r4			/* r0=phys. base section */
+	ldr	r1, .LCmmuflags		/* FLGS=MMU_MEMFLAGS */
+	add	r3, r1, r0		/* r3=flags + base */
+	str	r3, [r4, r0, lsr #18]	/* identity mapping */
+
+	/* Jump into the physical address space */
+
+	ldr	pc, .LCphysrestart
+	nop
+	nop
+
+	/* We are now executing at our physical address, with the
+	 * MMU disabled.
+	 */
+
+up_phyrestart:
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7		/* Invalidate I,D caches */
+	mcr	p15, 0, r0, c7, c10, 4	/* Drain write buffer */
+	mcr	p15, 0, r0, c8, c7		/* Invalidate I,D TLBs */
+
+	/* Clear bits in control register (see start.h): Disable,
+	 * MMU, Data cache, alignment traps, write buffer, Instruction
+	 * cache, exceptions at 0xffff0000, round robin)
+	 */
+
+	mrc	p15, 0, r0, c1, c0		/* Get control register */
+	bic	r0, r0, #(CR_M|CR_C|CR_A|CR_W)
+	bic	r0, r0, #(CR_S|CR_I|CR_V|CR_RR)
+	mcr	p15, 0, r0, c1, c0, 0		/* Write control reg */
+
+	/* We know that the the bootloader entry point is at the
+	 * beginning of flash.
+	 */
+#if 1
+	ldr	pc, .LCbtldrentry		/* Restart bootloader */
+#else
+	b	__start				/* Restart Nuttx */
+#endif
+
+	.type	.LCphysrestart, %object
+.LCphysrestart:
+	.long	(up_phyrestart - CONFIG_DRAM_VSTART - CONFIG_DRAM_START)
+.LCbtldrentry:
+	.long	DM320_EXT_MEM_PADDR
+
+/**************************************************************************
+ * PC_Relative Data
+ **************************************************************************/
+
+	.type	.LCmmuflags, %object
+.LCmmuflags:
+	.long	MMU_MEMFLAGS
+	.size	up_restart, .-up_restart
+
+	.end
+
diff --git a/nuttx/arch/arm/src/dm320/dm320_serial.c b/nuttx/arch/arm/src/dm320/dm320_serial.c
new file mode 100644
index 000000000..8051393cf
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_serial.c
@@ -0,0 +1,725 @@
+/************************************************************
+ * dm320/dm320_serial.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial.h>
+#include <arch/serial.h>
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define BASE_BAUD 115200
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+struct up_dev_s
+{
+  uint32               uartbase;	/* Base address of UART
+					 * registers */
+  uint32               baud;		/* Configured baud */
+  uint16               msr;		/* Saved MSR value */
+  ubyte                irq;		/* IRQ associated with
+					 * this UART */
+  ubyte                parity;		/* 0=none, 1=odd, 2=even */
+  ubyte                bits;		/* Number of bits (7 or 8) */
+  boolean              stopbits2;	/* TRUE: Configure with 2
+					 * stop bits instead of 1 */
+};
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+static int     up_setup(struct uart_dev_s *dev);
+static void    up_shutdown(struct uart_dev_s *dev);
+static int     up_interrupt(int irq, void *context);
+static int     up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int     up_receive(struct uart_dev_s *dev, uint32 *status);
+static void    up_rxint(struct uart_dev_s *dev, boolean enable);
+static boolean up_rxfifonotempty(struct uart_dev_s *dev);
+static void    up_send(struct uart_dev_s *dev, int ch);
+static void    up_txint(struct uart_dev_s *dev, boolean enable);
+static boolean up_txfifonotfull(struct uart_dev_s *dev);
+static boolean up_txfifoempty(struct uart_dev_s *dev);
+
+/************************************************************
+ * Private Variables
+ ************************************************************/
+
+struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .handler        = up_interrupt,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxfifonotempty = up_rxfifonotempty,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txfifonotfull  = up_txfifonotfull,
+  .txfifoempty    = up_txfifoempty,
+};
+
+/* I/O buffers */
+
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* This describes the state of the DM320 uart0 port. */
+
+static struct up_dev_s g_uart0priv =
+{
+  .uartbase       = DM320_UART0_REGISTER_BASE,
+  .baud           = CONFIG_UART0_BAUD,
+  .parity         = CONFIG_UART0_PARITY,
+  .bits           = CONFIG_UART0_BITS,
+  .stopbits2      = CONFIG_UART0_2STOP,
+};
+
+static uart_dev_t g_uart0port =
+{
+  .irq      = DM320_IRQ_UART0,
+  .recv     =
+  {
+    .size   = CONFIG_UART0_RXBUFSIZE,
+    .buffer = g_uart0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART0_TXBUFSIZE,
+    .buffer = g_uart0txbuffer,
+  },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart0priv,
+};
+
+/* This describes the state of the DM320 uart1 port. */
+
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase       = DM320_UART1_REGISTER_BASE,
+  .baud           = CONFIG_UART1_BAUD,
+  .parity         = CONFIG_UART1_PARITY,
+  .bits           = CONFIG_UART1_BITS,
+  .stopbits2      = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .irq      = DM320_IRQ_UART1,
+  .recv     =
+  {
+    .size   = CONFIG_UART1_RXBUFSIZE,
+    .buffer = g_uart1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_UART1_TXBUFSIZE,
+    .buffer = g_uart1txbuffer,
+   },
+  .ops      = &g_uart_ops,
+  .priv     = &g_uart1priv,
+};
+
+/* Now, which one with be tty0/console and which tty1? */
+
+#ifdef CONFIG_SERIAL_IRDA_CONSOLE
+# define CONSOLE_DEV     g_uart1port
+# define TTYS0_DEV       g_uart1port
+# define TTYS1_DEV       g_uart0port
+#else
+# define CONSOLE_DEV     g_uart0port
+# define TTYS0_DEV       g_uart0port
+# define TTYS1_DEV       g_uart1port
+#endif
+
+/************************************************************
+ * Private Functions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_serialin
+ ************************************************************/
+
+static inline uint16 up_serialin(struct up_dev_s *priv, uint32 offset)
+{
+  return getreg16(priv->uartbase + offset);
+}
+
+/************************************************************
+ * Name: up_serialout
+ ************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, uint32 offset, uint16 value)
+{
+  putreg16(value, priv->uartbase + offset);
+}
+
+/************************************************************
+ * Name: up_disableuartint
+ ************************************************************/
+
+static inline void up_disableuartint(struct up_dev_s *priv, uint16 *msr)
+{
+  if (msr)
+    {
+      *msr = priv->msr & UART_MSR_ALLIE;
+    }
+
+  priv->msr &= ~UART_MSR_ALLIE;
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_restoreuartint
+ ************************************************************/
+
+static inline void up_restoreuartint(struct up_dev_s *priv, uint16 msr)
+{
+  priv->msr |= msr & UART_MSR_ALLIE;
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_waittxfifonotfull
+ ************************************************************/
+
+static inline void up_waittxfifonotfull(struct up_dev_s *priv)
+{
+  int tmp;
+
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      if ((up_serialin(priv, UART_SR) & UART_SR_TFTI) != 0)
+        {
+          break;
+        }
+    }
+}
+
+/************************************************************
+ * Name: up_enablebreaks
+ ************************************************************/
+
+static inline void up_enablebreaks(struct up_dev_s *priv, boolean enable)
+{
+  uint16 lcr = up_serialin(priv, UART_LCR);
+  if (enable)
+    {
+      lcr |= UART_LCR_BOC;
+    }
+  else
+    {
+      lcr &= ~UART_LCR_BOC;
+    }
+  up_serialout(priv, UART_LCR, lcr);
+}
+
+/************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+#ifdef CONFIG_SUPPRESS_UART_CONFIG
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint16 brsr;
+
+  /* Clear fifos */
+
+  up_serialout(priv, UART_DM320_RFCR, 0x8000);
+  up_serialout(priv, UART_DM320_TFCR, 0x8000);
+
+  /* Set rx and tx triggers */
+
+  up_serialout(priv, UART_DM320_RFCR, UART_RFCR_RTL_1);
+  up_serialout(priv, UART_DM320_TFCR, UART_TFCR_TTL_16);
+
+  /* Set up the MSR */
+
+  priv->msr = up_serialin(priv, UART_MSR);
+  if (priv->bits == 7)
+    {
+      priv->msr |= UART_DATABIT_7;
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_CLS;
+    }
+
+  if (priv->stopbits2)
+    {
+      priv->msr |= UART_STOPBIT_2;
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_SBLS;
+    }
+
+  if (priv->parity == 1)
+    {
+      priv->msr |= UART_ODDPARITY;
+    }
+  else if (priv->parity == 2)
+    {
+      priv->msr |= UART_EVENPARITY;
+    }
+  else
+    {
+      priv->msr &= ~(UART_MSR_PSB|UART_MSR_PEB);
+    }
+
+  /* Set up the BRSR */
+
+  switch (dev->baud)
+    {
+      case 2400:
+        brsr = UART_BAUD_2400;
+        break;
+      case 4800:
+        brsr = UART_BAUD_4800;
+        break;
+      default:
+      case 9600:
+        brsr = UART_BAUD_9600;
+        break;
+      case 14400:
+        brsr = UART_BAUD_14400;
+        break;
+      case 19200:
+        brsr = UART_BAUD_19200;
+        break;
+      case 28800:
+        brsr = UART_BAUD_28800;
+        break;
+      case 3840:
+        brsr = UART_BAUD_38400;
+        break;
+      case 57600:
+        brsr = UART_BAUD_57600;
+        break;
+      case 115200:
+        brsr = UART_BAUD_115200;
+        break;
+      case 230400:
+        brsr = UART_BAUD_230400;
+        break;
+      case 460800:
+        brsr = UART_BAUD_460800;
+        break;
+      case 921600:
+        brsr = UART_BAUD_921600;
+        break;
+    }
+
+  /* Setup the new UART configuration */
+
+  up_serialout(priv,UART_MSR, priv->msr);
+  up_serialout(priv, UART_DM320_BRSR, brsr);
+  up_enablebreaks(priv, FALSE);
+#endif
+  return OK;
+}
+
+/************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial
+ *   port is closed
+ *
+ ************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disableuartint(priv, NULL);
+}
+
+/************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   uart_dev_s structure in order to call these functions.
+ *
+ ************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+  uint16             status;
+  int                passes = 0;
+
+  if (g_uart1port.irq == irq)
+    {
+      dev = &g_uart1port;
+    }
+  else if (g_uart0port.irq == irq)
+    {
+      dev = &g_uart0port;
+    }
+  else
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  for(;;)
+    {
+      /* Get the current UART status and check for loop
+       * termination conditions
+       */
+
+      status  = up_serialin(priv, UART_SR);
+      status &= (UART_SR_RFTI | UART_SR_TFTI);
+
+      if (status == 0 || passes > 256) 
+        {
+          return OK;
+        }
+
+      /* Handline incoming, receive bytes */
+
+      if (status & UART_SR_RFTI)
+        {
+          uart_recvchars(dev);
+        }
+
+      /* Handle outgoing, transmit bytes */
+
+      if (status & UART_SR_TFTI)
+        {
+          uart_xmitchars(dev);
+        }
+
+      /* Keep track of how many times we do this in case there
+       * is some hardware failure condition.
+       */
+
+      passes++;
+    }
+}
+
+/************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+  struct up_dev_s   *priv  = (struct up_dev_s*)dev->priv;
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+    case TIOCSERGSTRUCT:
+      {
+         struct up_dev_s *user = (struct up_dev_s*)arg;
+         if (!user)
+           {
+             *get_errno_ptr() = EINVAL;
+             ret = ERROR;
+           }
+         else
+           {
+             memcpy(user, dev, sizeof(struct up_dev_s));
+           }
+       }
+       break;
+
+    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
+      {
+        irqstate_t flags = irqsave();
+        up_enablebreaks(priv, TRUE);
+        irqrestore(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
+      {
+        irqstate_t flags;
+        flags = irqsave();
+        up_enablebreaks(priv, FALSE);
+        irqrestore(flags);
+      }
+      break;
+
+    default:
+      *get_errno_ptr() = ENOTTY;
+      ret = ERROR;
+      break;
+    }
+
+  return ret;
+}
+
+/************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the the return 'status'.
+ *
+ ************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, uint32 *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint16 dtrr;
+
+  dtrr    = up_serialin(priv, UART_DTRR);
+  *status = dtrr;
+  return dtrr & UART_DTRR_DTR_MASK;
+}
+
+/************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->msr |= UART_MSR_RFTIE;
+#endif
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_RFTIE;
+    }
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_rxfifonotempty
+ *
+ * Description:
+ *   Return TRUE if the receive fifo is not empty
+ *
+ ************************************************************/
+
+static boolean up_rxfifonotempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, UART_SR) & UART_SR_RFNEF) != 0);
+}
+
+/************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_serialout(priv, UART_DTRR, (uint16)ch);
+}
+
+/************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, boolean enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->msr |= UART_MSR_TFTIE;
+#endif
+    }
+  else
+    {
+      priv->msr &= ~UART_MSR_TFTIE;
+    }
+  up_serialout(priv, UART_MSR, priv->msr);
+}
+
+/************************************************************
+ * Name: up_txfifonotfull
+ *
+ * Description:
+ *   Return TRUE if the tranmsit fifo is not full
+ *
+ ************************************************************/
+
+static boolean up_txfifonotfull(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, UART_SR) & UART_SR_TFTI) != 0);
+}
+
+/************************************************************
+ * Name: up_txfifoempty
+ *
+ * Description:
+ *   Return TRUE if the transmit fifo is empty
+ *
+ ************************************************************/
+
+static boolean up_txfifoempty(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, UART_SR) & UART_SR_TREF) == 0);
+}
+
+/************************************************************
+ * Public Funtions
+ ************************************************************/
+
+/************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_serialinit.
+ *
+ ************************************************************/
+
+void up_earlyserialinit(void)
+{
+  up_disableuartint(TTYS0_DEV.priv, NULL);
+  up_disableuartint(TTYS1_DEV.priv, NULL);
+
+  CONSOLE_DEV.isconsole = TRUE;
+  up_setup(&CONSOLE_DEV);
+}
+
+/************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ************************************************************/
+
+void up_serialinit(void)
+{
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+}
+
+/************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug
+ *   writes
+ *
+ ************************************************************/
+
+int up_putc(int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint16  ier;
+
+  up_disableuartint(priv, &ier);
+  up_waittxfifonotfull(priv);
+  up_serialout(priv, UART_DTRR, (uint16)ch);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxfifonotfull(priv);
+      up_serialout(priv, UART_DTRR, '\r');
+    }
+
+  up_waittxfifonotfull(priv);
+  up_restoreuartint(priv, ier);
+  return ch;
+}
+
diff --git a/nuttx/arch/arm/src/dm320/dm320_timer.h b/nuttx/arch/arm/src/dm320/dm320_timer.h
new file mode 100644
index 000000000..6c76f4824
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_timer.h
@@ -0,0 +1,112 @@
+/************************************************************************************
+ * dm320/dm320_timer.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_TIMER_H
+#define __DM320_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Timer Registers */
+
+#define DM320_TIMER0_TMMD         (DM320_PERIPHERALS_VADDR + 0x0000) /* Timer 0 Mode */
+#define DM320_TIMER0_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0004) /* Timer 0 Prescalar */
+#define DM320_TIMER0_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0006) /* Timer 0 Divisor (count) */
+#define DM320_TIMER0_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0008) /* Timer 0 One-Shot Trigger */
+#define DM320_TIMER0_TMCNT        (DM320_PERIPHERALS_VADDR + 0x000A) /* Timer 0 Count */
+
+#define DM320_TIMER1_TMMD         (DM320_PERIPHERALS_VADDR + 0x0080) /* Timer 1 Mode */
+#define DM320_TIMER1_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0084) /* Timer 1 Prescalar */
+#define DM320_TIMER1_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0086) /* Timer 1 Divisor (count) */
+#define DM320_TIMER1_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0088) /* Timer 1 One-Shot Trigger */
+#define DM320_TIMER1_TMCNT        (DM320_PERIPHERALS_VADDR + 0x008A) /* Timer 1 Count */
+
+#define DM320_TIMER2_TMMD         (DM320_PERIPHERALS_VADDR + 0x0100) /* Timer 2 Mode */
+#define DM320_TIMER2_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0104) /* Timer 2 Prescalar */
+#define DM320_TIMER2_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0106) /* Timer 2 Divisor (count) */
+#define DM320_TIMER2_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0108) /* Timer 2 One-Shot Trigger */
+#define DM320_TIMER2_TMCNT        (DM320_PERIPHERALS_VADDR + 0x010A) /* Timer 2 Count */
+
+#define DM320_TIMER3_TMMD         (DM320_PERIPHERALS_VADDR + 0x0180) /* Timer 2 Mode */
+#define DM320_TIMER3_TMPRSCL      (DM320_PERIPHERALS_VADDR + 0x0184) /* Timer 2 Prescalar */
+#define DM320_TIMER3_TMDIV        (DM320_PERIPHERALS_VADDR + 0x0186) /* Timer 2 Divisor (count) */
+#define DM320_TIMER3_TMTRG        (DM320_PERIPHERALS_VADDR + 0x0188) /* Timer 2 One-Shot Trigger */
+#define DM320_TIMER3_TMCNT        (DM320_PERIPHERALS_VADDR + 0x018A) /* Timer 2 Count */
+
+/* Timer 0,1,2,3 Mode Register Bits: */
+
+#define  DM320_TMR_MODE_TEST_MASK 0x00fc /* Bits 7:2=Test */
+#define  DM320_TMR_MODE_MODE_MASK 0x0003 /* Bits 1:0=timer mode */
+
+# define DM320_TMR_MODE_STOP      0x0000 /* Stop Timer */
+# define DM320_TMR_MODE_ONESHOT   0x0001 /* Start one-shot timer */
+# define DM320_TMR_MODE_FREERUN   0x0002 /* Start free-running timer */
+
+/* Timer 0,1,2,3 Clock Select Register Bits: */
+
+#define  DM320_TMR_PRSCL_MASK     0x03ff /* Bits 0:9=Timer prescale value */
+
+/* Timer 0,1,2,3 Clock Divisor (Count) Register Bits: */
+
+#define  DM320_TMR_DIV_MASK       0xffff /* Bits 0:15=Timer divisor value */
+
+/* Timer 0,1,2,3 Timer One-Short Trigger Register Bits: */
+
+#define  DM320_TMR_TMTRG_MASK     0x0001 /* Bit 0=One short trigger */
+
+# define DM320_TMR_TMTRG_START    0x0001 /* 1 starts one shot timer */
+
+/* Timer 0,1,2,3 Timer Counter Register Bits: */
+
+#define DM320_TMR_COUNT_MASK      0xffff /* Bits 0:15=Current counter value */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#endif  /* __DM320_TIMER_H */
diff --git a/nuttx/arch/arm/src/dm320/dm320_timerisr.c b/nuttx/arch/arm/src/dm320/dm320_timerisr.c
new file mode 100644
index 000000000..603a66c91
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_timerisr.c
@@ -0,0 +1,153 @@
+/************************************************************
+ * dm320/dm320_timerisr.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+/* DM320 Timers
+ *
+ * Each of the general-purpose timers can run in one of two modes:  one-
+ * shot mode and free-run mode.  In one-shot mode, an interrupt only 
+ * occurs once and then the timer must be explicitly reset to begin the 
+ * timing operation again.  In free-run mode, when the timer generates an 
+ * interrupt, the timer counter is automatically reloaded to start the count 
+ * operation again.  Use the bit field MODE in TMMDx to configure the 
+ * timer for one-shot more or free-run mode. The bit field MODE in TMMDx
+ * also allows you to stop the timer.
+ * 
+ * Either the ARM clock divided by 2 (CLK_ARM/2) or an external clock 
+ * connected to the M27XI pin can be selected as the clock source of the 
+ * timer.
+ *
+ * The actual clock frequency used in the timer count operation is the input 
+ * clock divided by: 1 plus the value set in the bit field PRSCL of the 
+ * register TMPRSCLx (10 bits).  The timer expires when it reaches the 
+ * value set in the bit field DIV of the register TMDIVx (16 bits) plus 1. 
+ * PRSCL+1 is the source clock frequency divide factor and DIV+1 is the 
+ * timer count value.  The frequency of a timer interrupt is given by the 
+ * following equation:
+ *
+ * Interrupt Frequency = (Source Clock Frequency) / (PRSCL+1) / (DIV+1)
+ */
+
+/* System Timer
+ *
+ * Timer0 is dedicated as the system timer.  The rate of system timer
+ * interrupts is assumed to to 10MS per tick / 100Hz. The following
+ * register settings are used for timer 0
+ *
+ * System clock formula:
+ *   Interrupt Frequency = (Source Clock Frequency) / (PRSCL+1) / (DIV+1)
+ *   Source Clock Frequency = 27MHz  (PLL clock)
+ *   DIV                    = 26,999 (Yields 1Khz timer clock)
+ *   PRSCL                  = 9      (Produces 100Hz interrupts)
+ */
+
+#define DM320_TMR0_MODE  DM320_TMR_MODE_FREERUN /* Free running */
+#define DM320_TMR0_DIV   26999                  /* (see above) */
+#define DM320_TMR0_PRSCL 9                      /* (see above) */
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for
+ *   various portions of the systems.
+ *
+ ************************************************************/
+
+int up_timerisr(int irq, uint32 *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ************************************************************/
+
+void up_timerinit(void)
+{
+  up_disable_irq(DM320_IRQ_SYSTIMER);
+
+  /* Start timer0 running so that an interrupt is generated at
+   * the rate MSEC_PER_TICK.
+   */
+
+  putreg16(DM320_TMR0_PRSCL, DM320_TIMER0_TMPRSCL); /* Timer 0 Prescalar */
+  putreg16(DM320_TMR0_DIV, DM320_TIMER0_TMDIV);     /* Timer 0 Divisor (count) */
+
+  /* Start the timer */
+
+  putreg16(DM320_TMR0_MODE, DM320_TIMER0_TMMD); /* Timer 0 Mode */
+
+  /* Attach and enable the timer interrupt */
+
+  irq_attach(DM320_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
+  up_enable_irq(DM320_IRQ_SYSTIMER);
+}
+
diff --git a/nuttx/arch/arm/src/dm320/dm320_uart.h b/nuttx/arch/arm/src/dm320/dm320_uart.h
new file mode 100644
index 000000000..8938018a7
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_uart.h
@@ -0,0 +1,172 @@
+/************************************************************************************
+ * dm320/dm320_uart.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __DM320_UART_H
+#define __DM320_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include <sys/types.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* UART definitions *****************************************************************/
+
+/* UART Registers (offsets from the register base) */
+
+#define UART_DTRR              0    /* Data Transmission/Reception Register */
+#define UART_BRSR              2    /* Bit Rate Set Register */
+#define UART_MSR               4    /* Mode Set Register */
+#define UART_RFCR              6    /* Reception FIFO Control Register */
+#define UART_TFCR              8    /* Transmission FIFO Control Register */
+#define UART_LCR              10    /* Line Control Register */
+#define UART_SR               12    /* Status Register */
+
+/* UART DTRR register bit definitions */
+
+#define UART_DTRR_RVF         0x1000 /* Receive word valid flag */
+#define UART_DTRR_BF          0x0800 /* Break flag */
+#define UART_DTRR_FE          0x0400 /* Framing error */
+#define UART_DTRR_ORF         0x0200 /* Overrun flag */
+#define UART_DTRR_PEF         0x0100 /* Parity error */
+#define UART_DTRR_DTR_MASK    0x00ff /* Data transmit/receive */
+
+/* UART BRSR register bit definitions */
+/* The UART clock is half of the ARM clock */
+
+#define UART_CLK (DM320_ARM_CLOCK / 2)
+
+/* And baud rate = UART_CLK / 16 / (VALUE+1) */
+
+#define UART_BAUD_2400        ((uint16)(((UART_CLK / 16) / 2400  ) - 1))
+#define UART_BAUD_4800        ((uint16)(((UART_CLK / 16) / 4800  ) - 1))
+#define UART_BAUD_9600        ((uint16)(((UART_CLK / 16) / 9600  ) - 1))
+#define UART_BAUD_14400       ((uint16)(((UART_CLK / 16) / 14400 ) - 1))
+#define UART_BAUD_19200       ((uint16)(((UART_CLK / 16) / 19200 ) - 1))
+#define UART_BAUD_28800       ((uint16)(((UART_CLK / 16) / 28800 ) - 1))
+#define UART_BAUD_38400       ((uint16)(((UART_CLK / 16) / 38400 ) - 1))
+#define UART_BAUD_57600       ((uint16)(((UART_CLK / 16) / 57600 ) - 1))
+#define UART_BAUD_115200      ((uint16)(((UART_CLK / 16) / 115200) - 1))
+#define UART_BAUD_230400      ((uint16)(((UART_CLK / 16) / 230400) - 1))
+#define UART_BAUD_460800      ((uint16)(((UART_CLK / 16) / 460800) - 1))
+#define UART_BAUD_921600      ((uint16)(((UART_CLK / 16) / 921600) - 1))
+
+/* UART MSR register bit definitions */
+
+#define UART_MSR_MODE_BITS    0x001f /* Aata length, stop, & parity */
+#define UART_MSR_CLS          0x0001 /* Char length (1=7bit, 0=8bit) */
+#define UART_DATABIT_7        0x0001 /*  Data bit = 7bit */
+#define UART_DATABIT_8        0x0000 /*  Data bit = 8bit */
+#define UART_MSR_SBLS         0x0004 /* Stop bit length selection */
+#define UART_STOPBIT_1        0x0000 /*  Stop bit = 1bit */
+#define UART_STOPBIT_2        0x0004 /*  Stop bit = 2bit */
+#define UART_MSR_PSB          0x0008 /* Parity selection bit */
+#define UART_MSR_PEB          0x0010 /* Parity enable bit */
+#define UART_NOPARITY         0x0000 /*   No-parity */
+#define UART_ODDPARITY        0x0018 /*   Odd parity */
+#define UART_EVENPARITY       0x0010 /*   Even parity */
+#define UART_MSR_RTSC         0x0020 /* RTS receive FIFO control */
+#define UART_MSR_CSTC         0x0040 /* CTS send control */
+#define UART_MSR_TOIC_MASK    0x0c00 /* Timeout interrupt control */
+#define UART_MSR_TOIC_DIS     0x0000 /*   Disabled */
+#define UART_MSR_TOIC_3       0x0400 /*   3 bytes */
+#define UART_MSR_TOIC_7       0x0800 /*   7 bytes */
+#define UART_MSR_TOIC_15      0x0c00 /*  15 bytes */
+#define UART_MSR_ALLIE        0xfc00 /* All interrupt bits */
+#define UART_MSR_LSIE         0x1000 /*  Line status change int. enable */
+#define UART_MSR_REIE         0x2000 /*  Receive error interrupt enable */
+#define UART_MSR_TFTIE        0x4000 /*  Transmit FIFO trigger int. enable */
+#define UART_MSR_RFTIE        0x8000 /*  Receive FIFO trigger int. enable */
+
+#define  UART_MSR_INIT (UART_NOPARITY | UART_STOPBIT_1 | UART_DATABIT_8)
+
+/* UART RFCR register bit definitions */
+
+#define UART_RFCR_RWC_MASK    0x003f /* Receive byte count */
+#define UART_RFCR_RTL_MASK    0x0700 /* Receive trigger level */
+#define UART_RFCR_RTL_1       0x0000 /*   1 byte */
+#define UART_RFCR_RTL_4       0x0100 /*   4 bytes */
+#define UART_RFCR_RTL_8       0x0200 /*   8 bytes */
+#define UART_RFCR_RTL_16      0x0300 /*  16 bytes */
+#define UART_RFCR_RTL_24      0x0400 /*  24 bytes */
+#define UART_RFCR_RTL_32      0x0500 /*  32 bytes */
+#define UART_RFCR_RDEF        0x4000 /* Receive data error flag */
+#define UART_RFCR_RFCB        0x8000 /* Receive FIFO clear bit */
+
+/* UART TFCR register bit definitions */
+
+#define UART_TFCR_TWC_MASK    0x003f /* Transmit byte count */
+#define UART_TFCR_TTL_MASK    0x0700 /* Transmit trigger level */
+#define UART_TFCR_TTL_1       0x0000 /*   1 byte */
+#define UART_TFCR_TTL_4       0x0100 /*   4 bytes */
+#define UART_TFCR_TTL_8       0x0200 /*   8 bytes */
+#define UART_TFCR_TTL_16      0x0300 /*  16 bytes */
+#define UART_TFCR_TTL_24      0x0400 /*  24 bytes */
+#define UART_TFCR_TTL_32      0x0500 /*  32 bytes */
+#define UART_TFCR_TFCB        0x8000 /* Transmit FIFO clear bit */
+
+/* UART LCR register bit definitions */
+
+#define UART_LCR_RTS          0x0004 /* Current RTS value */
+#define UART_LCR_CTS          0x0010 /* Current CTS value */
+#define UART_LCR_DSR          0x0080 /* Current DSR value */
+#define UART_LCR_BOC          0x0100 /* Break output control */
+#define UART_LCR_UTST         0x4000 /* Test mode setting */
+
+#define UART_LCR_INIT         0x0000
+
+/* UART SR register bit definitions */
+
+#define UART_SR_TREF          0x0001 /* Transmit register empty flag */
+#define UART_SR_TFEF          0x0002 /* Transmit FIFO empty flag */
+#define UART_SR_RFNEF         0x0004 /* Receive FIFO not empty flag */
+#define UART_SR_TOIF          0x0100 /* Timeout Interrupt flag */
+#define UART_SR_RFER          0x0200 /* Receive data error flag */
+#define UART_SR_TFTI          0x0400 /* Transmit FIFO trigger level */
+#define UART_SR_RFTI          0x0800 /* Receive FIFO trigger level */
+#define UART_SR_CTSS          0x1000 /* CTS status */
+#define UART_SR_DSRS          0x8000 /* DSR status */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#endif  /* __DM320_UART_H */
diff --git a/nuttx/arch/arm/src/dm320/dm320_vectors.S b/nuttx/arch/arm/src/dm320/dm320_vectors.S
new file mode 100644
index 000000000..2f22f2b42
--- /dev/null
+++ b/nuttx/arch/arm/src/dm320/dm320_vectors.S
@@ -0,0 +1,449 @@
+/********************************************************************
+ * dm320/dm320_vectors.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include "up_arch.h"
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/********************************************************************
+ * Global Data
+ ********************************************************************/
+
+	.data
+g_irqtmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+g_undeftmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+g_aborttmp:
+	.word	0		/* Saved lr */
+	.word	0		/* Saved spsr */
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/********************************************************************
+ * Private Functions
+ ********************************************************************/
+
+	.text
+
+/********************************************************************
+ * Public Functions
+ ********************************************************************/
+
+	.text
+
+/********************************************************************
+ * Name: up_vectorirq
+ *
+ * Description:
+ *   Interrupt excetpion. Entered in IRQ mode with spsr = SVC
+ *   CPSR, lr = SVC PC
+ ********************************************************************/
+
+	.globl	up_vectorirq
+	.type	up_vectorirq, %function
+up_vectorirq:
+	/* On entry, we are in IRQ mode.  We are free to use
+	 * the IRQ mode r13 and r14.
+         *
+	 */
+
+	ldr	r13, .Lirqtmp
+	sub	lr, lr, #4
+	str	lr, [r13]			@ save lr_IRQ
+	mrs	lr, spsr
+	str	lr, [r13, #4]			@ save spsr_IRQ
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lirqtmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the IRQ handler with interrupts disabled. */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_doirq		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+.Lnoirqset:
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lirqtmp:
+	.word	g_irqtmp
+
+	.align	5
+
+/********************************************************************
+ * Function: up_vectorswi
+ * 
+ * Description:
+ *   SWI interrupt. We enter the SWI in SVC mode
+ ********************************************************************/
+
+	.globl	up_vectorswi
+	.type	up_vectorswi, %function
+up_vectorswi:
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp), r14(lr), r15(pc)
+	 * and CPSR in r1-r4 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14			/* R14 is altered on return from SWI */
+	mov	r3, r14			/* Save r14 as the PC as well */
+	mrs	r4, spsr		/* Get the saved CPSR */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the SWI handler with interrupt disabled.
+	 * void up_syscall(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_syscall		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectordata
+ *
+ * Description:
+ *   Data abort Exception dispatcher. Give control to data
+ *   abort handler.  This function is entered in ABORT mode
+ *   with spsr = SVC CPSR, lr = SVC PC
+ *
+ ********************************************************************/
+	
+	.globl	up_vectordata
+	.type	up_vectordata, %function
+up_vectordata:
+	/* On entry we are free to use the ABORT mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Ldaborttmp	/* Points to temp storage */
+	sub	lr, lr, #8		/* Fixup return */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Ldaborttmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the data abort handler with interrupt disabled.
+	 * void up_dataabort(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_dataabort		/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Ldaborttmp:
+	.word	g_aborttmp
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorprefetch
+ *
+ * Description:
+ *    Prefetch abort exception.  Entered in ABT mode with
+ *    spsr = SVC CPSR, lr = SVC PC
+ ********************************************************************/
+	
+	.globl	up_vectorprefetch
+	.type	up_vectorprefetch, %function
+up_vectorprefetch:
+	/* On entry we are free to use the ABORT mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Lpaborttmp	/* Points to temp storage */
+	sub	lr, lr, #4		/* Fixup return */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lpaborttmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the prefetch abort handler with interrupt disabled.
+	 * void up_prefetchabort(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_prefetchabort	/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lpaborttmp:
+	.word	g_aborttmp
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorundefinsn
+ *
+ * Description:
+ *   Undefined instruction entry exception.  Entered in
+ *   UND mode, spsr = SVC  CPSR, lr = SVC PC
+ *
+ ********************************************************************/
+	
+	.globl	up_vectorundefinsn
+	.type	up_vectorundefinsn, %function
+up_vectorundefinsn:
+	/* On entry we are free to use the UND mode registers
+	 * r13 and r14
+	 */
+
+	ldr	r13, .Lundeftmp		/* Points to temp storage */
+	str	lr, [r13]		/* Save in temp storage */
+	mrs	lr, spsr		/* Get SPSR */
+	str	lr, [r13, #4]		/* Save in temp storage */
+
+	/* Then switch back to SVC mode */
+
+	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	msr	cpsr_c, lr		/* Switch to SVC mode */
+
+	/* Create a context structure.  First set aside a stack frame
+	 * and store r0-r12 into the frame.
+	 */
+
+	sub	sp, sp, #XCPTCONTEXT_SIZE
+	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
+
+	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
+
+	add	r1, sp, #XCPTCONTEXT_SIZE
+	mov	r2, r14
+
+	/* Get the values for r15(pc) and CPSR in r3 and r4 */
+
+	ldr	r0, .Lundeftmp		/* Points to temp storage */
+	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
+
+	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
+	stmia	r0, {r1-r4}
+
+	/* Then call the undef insn handler with interrupt disabled.
+	 * void up_undefinedinsn(struct xcptcontext *xcp)
+	 */
+
+	mov	fp, #0			/* Init frame pointer */
+	mov	r0, sp			/* Get r0=xcp */
+	bl	up_undefinedinsn	/* Call the handler */
+
+	/* Restore the CPSR, SVC modr registers and return */
+
+	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
+	msr	spsr_cxsf, r0
+	ldmia	sp, {r0-r15}^		/* Return */
+
+.Lundeftmp:
+	.word	g_undeftmp
+
+	.align	5
+
+/********************************************************************
+ * Name: up_vectorfiq
+ *
+ * Description:
+ *   Shouldn't happen
+ ********************************************************************/
+
+	.globl	up_vectorfiq
+	.type	up_vectorfiq, %function
+up_vectorfiq:
+	subs	pc, lr, #4
+
+/********************************************************************
+ *  Name: up_vectoraddrexcption
+ *
+ * Description:
+ *   Shouldn't happen
+ *
+ ********************************************************************/
+
+	.globl	up_vectoraddrexcptn
+	.type	up_vectoraddrexcptn, %function
+up_vectoraddrexcptn:
+	b	up_vectoraddrexcptn
+
+/**************************************************************************
+ * Vector initialization block.
+ **************************************************************************/
+
+/* These will be relocated to VECTOR_BASE. */
+
+	.globl	_vector_start
+_vector_start:
+	ldr	pc, .Lresethandler		/* 0x00: Reset */
+	ldr	pc, .Lundefinedhandler		/* 0x04: Undefined instruction */
+	ldr	pc, .Lswihandler		/* 0x08: Software interrupt */
+	ldr	pc, .Lprefetchaborthandler	/* 0x0c: Prefetch abort */
+	ldr	pc, .Ldataaborthandler		/* 0x10: Data abort */
+	ldr	pc, .Laddrexcptnhandler		/* 0x14: Address exception */
+	ldr	pc, .Lirqhandler		/* 0x18: IRQ */
+	ldr	pc, .Lfiqhandler		/* 0x1c: FIQ */
+
+.Lresethandler:
+	.long   __start
+.Lundefinedhandler:
+	.long	up_vectorundefinsn
+.Lswihandler:
+	.long	up_vectorswi
+.Lprefetchaborthandler:
+	.long	up_vectorprefetch
+.Ldataaborthandler:
+	.long	up_vectordata
+.Laddrexcptnhandler:
+	.long	up_vectoraddrexcptn
+.Lirqhandler:
+	.long	up_vectorirq
+.Lfiqhandler:
+	.long	up_vectorfiq
+	.globl	_vector_end
+_vector_end:
+	.end