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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-03-08 12:31:06 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-03-08 12:31:06 -0600 |
| commit | 39d69550a195f226b1985ebc62f760d286cd68c8 (patch) | |
| tree | 3efd0ea969c684d257a3266235b5685977d913ce /nuttx/arch/arm/src/lm/chip | |
| parent | d6ad8ebe0f0051c96688a0302154117c16d413de (diff) | |
| download | px4-nuttx-39d69550a195f226b1985ebc62f760d286cd68c8.tar.gz px4-nuttx-39d69550a195f226b1985ebc62f760d286cd68c8.tar.bz2 px4-nuttx-39d69550a195f226b1985ebc62f760d286cd68c8.zip | |
The old lm/ directories were enamed tiva/ to better support new products coming down the pipe from TI
Diffstat (limited to 'nuttx/arch/arm/src/lm/chip')
20 files changed, 0 insertions, 5941 deletions
diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h deleted file mode 100644 index d4bae8358..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_memorymap.h +++ /dev/null @@ -1,360 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_memorymap.h - * - * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory map ***********************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ - defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) -# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */ - /* -0xdfffffff: Reserved */ -# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x1fffffff: Reserved */ -# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ - /* -0x5fffffff: Reserved */ -# define LM_EPI0RAM_BASE 0x60000000 /* -0xdfffffff: EPI0 mapped peripheral and RAM */ -# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ - /* -0xffffffff: Reserved */ -#else -# error "Memory map not specified for this LM3S chip" -#endif - -/* Peripheral base addresses ********************************************************/ -/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few differnt - * peripheral modules. They could probably be combined into one peripheral memory - * map. However, keeping them separate does also provide so early, compile-time - * error detection that makes the duplication worthwhile. - */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -/* FiRM Peripheral Base Addresses */ - -# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ - /* -0x0bfff: Reserved */ -# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ - /* -0x2ffff: Reserved */ -# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -/* FiRM Peripheral Base Addresses */ - -# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2ffff: Reserved */ -# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ - /* -0x37fff: Reserved */ -# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ - -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -/* FiRM Peripheral Base Addresses */ - -# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x47fff: Reserved */ -# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -/* FiRM Peripheral Base Addresses */ - -# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ - /* -0x23fff: Reserved */ -# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ - /* -0x27fff: Reserved */ -# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */ - /* -0x3bfff: Reserved */ -# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x3fffff: Reserved */ -# define LM_CANCON_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ - /* -0x47fff: Reserved */ -# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0xfcfff: Reserved */ -# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ - /* -0x1ffffff: Reserved */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -/* FiRM Peripheral Base Addresses */ - -# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ - /* -0x03fff: Reserved */ -# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ - /* -0x0bfff: Reserved */ -# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ -# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ - /* -0x23fff: Reserved */ -# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ -# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ -# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ - -# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ - /* -0x2bfff: Reserved */ -# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ -# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ - /* -0x2ffff: Reserved */ -# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ -# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ -# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ -# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ - /* -0x37fff: Reserved */ -# define LM_ADC0_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ -# define LM_ADC1_BASE (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ - /* -0x3bfff: Reserved */ -# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ -# define LM_GPIOJ_BASE (LM_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ - /* -0x3ffff: Reserved */ -# define LM_CAN0_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ -# define LM_CAN1_BASE (LM_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ - /* -0x47fff: Reserved */ -# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ - /* -0x49fff: Reserved */ -# define LM_USB_BASE (LM_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ - /* -0x53fff: Reserved */ -# define LM_I2S0_BASE (LM_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ - /* -0x57fff: Reserved */ -# define LM_GPIOAAHB_BASE (LM_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ -# define LM_GPIOBAHB_BASE (LM_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ -# define LM_GPIOCAHB_BASE (LM_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */ -# define LM_GPIODAHB_BASE (LM_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */ -# define LM_GPIOEAHB_BASE (LM_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */ -# define LM_GPIOFAHB_BASE (LM_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */ -# define LM_GPIOGAHB_BASE (LM_PERIPH_BASE + 0x5e000) /* -0x5efff: GPIO Port G (AHB aperture) */ -# define LM_GPIOHAHB_BASE (LM_PERIPH_BASE + 0x5f000) /* -0x5ffff: GPIO Port H (AHB aperture) */ -# define LM_GPIOJAHB_BASE (LM_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ - /* -0xcffff: Reserved */ -# define LM_EPI0_BASE (LM_PERIPH_BASE + 0xd0000) /* -0xd0fff: EPI 0 */ - /* -0xfcfff: Reserved */ -# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ -# define LM_UDMA_BASE (LM_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */ - /* -0x1ffffff: Reserved */ -#else -# error "Peripheral base addresses not specified for this Stellaris chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h deleted file mode 100644 index ca1d53064..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_pinmap.h +++ /dev/null @@ -1,281 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_pinmap.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* The following lists the input value to lm_configgpio to setup the alternate, - * hardware function for each pin. - */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM1 (CCP1) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 0) /* PB0: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 1) /* PB1: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_TMR5_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 4) /* PC4: Capture/Compare/PWM5 (CCP5) */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_TMR4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 0) /* PD0: PWM Generator 0, PWM0 */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PD7: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ -# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_PORTA | 6) /* PA6: I2C1 clock (I2C1SCL) */ -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFINPUT | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ -# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ -# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ -# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ -# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ -# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ -# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ - -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ -# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */ -# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ -# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ -# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ -# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) (differs) */ -# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ -# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ -# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ -# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ -# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */ -# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */ -# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */ -# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ -# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ -# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */ -# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */ -# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: QEI module 0 index */ -# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ -# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ -# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ -# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ -# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */ -# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ -# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ -# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ -#else -# error "Unknown Stellaris chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h deleted file mode 100644 index a8e216778..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_syscontrol.h +++ /dev/null @@ -1,495 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_syscontrol.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* System Control Register Offsets **************************************************/ - -#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ -#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ -#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ -#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ -#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ -#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ -#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ -#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ -#define LM_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */ -#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ -#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ -#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/ -#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ -#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ -#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ -#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ -#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ -#define LM_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */ -#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ -#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ -#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ -#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ -#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ -#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ -#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ -#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ -#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ -#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ -#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ - -/* System Control Register Addresses ************************************************/ - -#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET) -#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET) -#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET) -#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET) -#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET) -#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET) -#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET) -#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET) -#define LM_SYSCON_LDOPCTL (LM_SYSCON_BASE + LM_SYSCON_LDOPCTL_OFFSET) -#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET) -#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET) -#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET) -#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET) -#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET) -#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET) -#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET) -#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET) -#define LM_SYSCON_PLLCFG (LM_SYSCON_BASE + LM_SYSCON_PLLCFG_OFFSET) -#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET) -#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET) -#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET) -#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET) -#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET) -#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET) -#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET) -#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET) -#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET) -#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET) -#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET) - -/* System Control Register Bit Definitions ******************************************/ - -/* Device Identification 0 (DID0), offset 0x000 */ - -#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ -#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) -#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ -#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) -#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ -#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) -#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ -#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) - -/* Device Identification 1 (DID1), offset 0x004 */ - -#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ -#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) -#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ -#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ -#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) -#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ -#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) -#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ -#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) -#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ -#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) -#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ -#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) -#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ -#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) - -/* Device Capabilities 0 (DC0), offset 0x008 */ - -#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ -#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) -#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ -#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) - -/* Device Capabilities 1 (DC1), offset 0x010 */ - -#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ -#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ -#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ -#define SYSCON_DC1_WDT (1 << 3) /* Bit 3: Watchdog Timer Present */ -#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ -#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ -#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ -#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ -#define SYSCON_DC1_MAXADCSPD_SHIFT 8 /* Bits 9-8: Max ADC Speed */ -#define SYSCON_DC1_MAXADCSPD_MASK (0x03 << SYSCON_DC1_MAXADCSPD_SHIFT) -#define SYSCON_DC1_ADC (1 << 16) /* Bit 16: ADC Module Present */ -#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 15-12: System Clock Divider Minimum */ -#define SYSCON_DC1_MINSYSDIV_MASK (0x0f << SYSCON_DC1_MINSYSDIV_SHIFT) - -/* Device Capabilities 2 (DC2), offset 0x014 */ - -#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Present */ -#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Present */ -#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Present */ -#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Present */ -#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ -#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ -#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ -#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ -#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ -#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ -#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ -#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ - -/* Device Capabilities 3 (DC3), offset 0x018 */ - -#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ -#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ -#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ -#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ -#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ -#define SYSCON_DC3_ADC0 (1 << 16) /* Bit 16: ADC0 Pin Present */ -#define SYSCON_DC3_ADC1 (1 << 17) /* Bit 17: ADC1 Pin Present */ -#define SYSCON_DC3_ADC2 (1 << 18) /* Bit 18: ADC2 Pin Present */ -#define SYSCON_DC3_ADC3 (1 << 19) /* Bit 19: ADC3 Pin Present */ -#define SYSCON_DC3_ADC4 (1 << 20) /* Bit 20: ADC4 Pin Present */ -#define SYSCON_DC3_ADC5 (1 << 21) /* Bit 21: ADC5 Pin Present */ -#define SYSCON_DC3_ADC6 (1 << 22) /* Bit 22: ADC6 Pin Present */ -#define SYSCON_DC3_ADC7 (1 << 23) /* Bit 23: ADC7 Pin Present */ -#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: CCP0 Pin Present */ -#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: CCP1 Pin Present */ -#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: CCP2 Pin Present */ -#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: CCP3 Pin Present */ -#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: CCP4 Pin Present */ -#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: CCP5 Pin Present */ -#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ - -/* Device Capabilities 4 (DC4), offset 0x01c */ - -#define SYSCON_DC4_GPIO(n) (1 << (n)) -#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ -#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ -#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ -#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ -#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ -#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ -#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ -#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ -#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ -#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ - -/* Brown-Out Reset Control (PBORCTL), offset 0x030 */ - -#define SYSCON_PBORCTL_BORIOR (1 << 1) /* Bit 1: BOR Interrupt or Reset */ - -/* LDO Power Control (LDOPCTL), offset 0x034 */ - -#define SYSCON_LDOPCTL_VADJ_SHIFT 0 /* Bits 5-0: LDO Output Voltage */ -#define SYSCON_LDOPCTL_VADJ_MASK (0x3f << SYSCON_LDOPCTL_VADJ_SHIFT) -# define SYSCON_LPDOPCTL_2500MV (0x00 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.5V (reset)*/ -# define SYSCON_LPDOPCTL_2450MV (0x01 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.45V */ -# define SYSCON_LPDOPCTL_2400MV (0x02 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.4V */ -# define SYSCON_LPDOPCTL_2350MV (0x03 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.35V */ -# define SYSCON_LPDOPCTL_2300MV (0x04 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.3V */ -# define SYSCON_LPDOPCTL_2250MV (0x05 << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.25V */ -# define SYSCON_LPDOPCTL_2750MV (0x1b << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.75V */ -# define SYSCON_LPDOPCTL_2700MV (0x1c << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.7V */ -# define SYSCON_LPDOPCTL_2650MV (0x1d << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.65V */ -# define SYSCON_LPDOPCTL_2600MV (0x1e << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.6V */ -# define SYSCON_LPDOPCTL_2550MV (0x1f << SYSCON_LDOPCTL_VADJ_SHIFT) /* 2.55V */ - -/* Software Reset Control 0 (SRCR0), offset 0x040 */ - -#define SYSCON_SRCR0_WDT (1 << 3) /* Bit 3: WDT Reset Control */ -#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: HIB Reset Control */ -#define SYSCON_SRCR0_ADC (1 << 16) /* Bit 16: ADC0 Reset Control */ - -/* Software Reset Control 1 (SRCR1), offset 0x044 */ - -#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ -#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ -#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control1 */ -#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ -#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C0 Reset Control */ -#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C1 Reset Control */ -#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ -#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ -#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ -#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ -#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comp 0 Reset Control */ -#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comp 1 Reset Control */ - -/* Software Reset Control 2 (SRCR2), offset 0x048 */ - -#define SYSCON_SRCR2_GPIO(n) (1 << (n)) -#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ -#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ -#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ -#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ -#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ -#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ -#define SYSCON_SRCR2_GPIOG (1 << 6) /* Bit 6: Port G Reset Control */ -#define SYSCON_SRCR2_GPIOH (1 << 7) /* Bit 7: Port H Reset Control */ -#define SYSCON_SRCR2_EMAC0 (1 << 28) /* Bit 28: MAC0 Reset Control */ -#define SYSCON_SRCR2_EPHY0 (1 << 30) /* Bit 30: PHY0 Reset Control */ - -/* Raw Interrupt Status (RIS), offset 0x050 */ - -#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */ -#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ - -/* Interrupt Mask Control (IMC), offset 0x054 */ - -#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */ -#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */ - -/* Masked Interrupt Status and Clear (MISC), offset 0x058 */ - -#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */ -#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ - -/* Reset Cause (RESC), offset 0x05C */ - -#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ -#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ -#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ -#define SYSCON_RESC_WDT (1 << 3) /* Bit 3: Watchdog Timer Reset */ -#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ - -/* Run-Mode Clock Configuration (RCC), offset 0x060 */ - -#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ -#define SYSCON_RCC_IOSCDIS (1 << 1) /* Bit 1: Internal Oscillator Disable */ -#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ -#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) -# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ -# define SYSCON_RCC_OSCSRC_PIOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC_OSCSRC_PIOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC_OSCSRC_LFIOSC (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ -#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ -#define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) -# define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL1843KHZ ( 1 << SYSCON_RCC_XTAL_SHIFT) /* 1.8432MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2000KHZ ( 2 << SYSCON_RCC_XTAL_SHIFT) /* 2.0000MHz (NO PLL) */ -# define SYSCON_RCC_XTAL2580KHZ ( 3 << SYSCON_RCC_XTAL_SHIFT) /* 2.4576MHz (NO PLL) */ -# define SYSCON_RCC_XTAL3580KHZ ( 4 << SYSCON_RCC_XTAL_SHIFT) /* 3.5795MHz */ -# define SYSCON_RCC_XTAL3686KHZ ( 5 << SYSCON_RCC_XTAL_SHIFT) /* 3.6864MHz */ -# define SYSCON_RCC_XTAL4000KHZ ( 6 << SYSCON_RCC_XTAL_SHIFT) /* 4.0000MHz */ -# define SYSCON_RCC_XTAL4096KHZ ( 7 << SYSCON_RCC_XTAL_SHIFT) /* 4.0960MHz */ -# define SYSCON_RCC_XTAL4915KHZ ( 8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152MHz */ -# define SYSCON_RCC_XTAL5000KHZ ( 9 << SYSCON_RCC_XTAL_SHIFT) /* 5.0000MHz */ -# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.1200MHz */ -# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6.0000MHz (reset value) */ -# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.1440MHz */ -# define SYSCON_RCC_XTAL7373KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728MHz */ -# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8.0000MHz */ -# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.1920MHz */ -#ifdef CONFIG_ARCH_CHIP_LM3S9B96 -# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12888KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ -# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ -# define SYSCON_RCC_XTAL14318KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ -# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ -# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ -#endif -#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ -#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ -#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ -#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ -#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) -# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) -#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ - -/* XTAL to PLL Translation (PLLCFG), offset 0x064 */ - -#define SYSCON_PLLCFG_F_SHIFT 5 /* Bits 13-5: PLL F Value */ -#define SYSCON_PLLCFG_F_MASK (0x1ff << SYSCON_PLLCFG_F_SHIFT) -#define SYSCON_PLLCFG_R_SHIFT 0 /* Bits 4-0: PLL R Value */ -#define SYSCON_PLLCFG_R_MASK (0x1f << SYSCON_PLLCFG_R_SHIFT) - -/* Run-Mode Clock Configuration 2 (RCC2), offset 0x070 */ - -#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ -#define SYSCON_RCC2_OSCSRC2_MASK (0x07 << SYSCON_RCC2_OSCSRC2_SHIFT) -# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ -# define SYSCON_RCC2_OSCSRC2_PIOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator (reset) */ -# define SYSCON_RCC2_OSCSRC2_PIOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ -# define SYSCON_RCC2_OSCSRC2_LFIOSC (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ -# define SYSCON_RCC2_OSCSRC2_32768HZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ -#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ -#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ -#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ -#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) -# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) -#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ - -/* Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 */ - -#define SYSCON_RCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_RCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_RCGC0_MAXADCSPD_MASK (0x03 << SYSCON_RCGC0_MAXADCSPD_SHIFT) -#define SYSCON_RCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 */ - -#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 */ - -#define SYSCON_RCGC2_GPIO(n) (1 << (n)) -#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_RCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_RCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_RCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_RCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 */ - -#define SYSCON_SCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_SCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_SCGC0_MAXADCSPD_MASK (0x03 << SYSCON_SCGC0_MAXADCSPD_SHIFT) -#define SYSCON_SCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 */ - -#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 */ - -#define SYSCON_SCGC2_GPIO(n) (1 << (n)) -#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_SCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_SCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_SCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_SCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 */ - -#define SYSCON_DCGC0_WDT (1 << 3) /* Bit 3: WDT Clock Gating Control */ -#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_DCGC0_MAXADCSPD_SHIFT 8 /* Bits 9-8: ADC Sample Speed */ -#define SYSCON_DCGC0_MAXADCSPD_MASK (0x03 << SYSCON_DCGC0_MAXADCSPD_SHIFT) -#define SYSCON_DCGC0_ADC (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 */ - -#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 */ - -#define SYSCON_DCGC2_GPIO(n) (1 << (n)) -#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_DCGC2_GPIOG (1 << 6) /* Bit 6: Port G Clock Gating Control */ -#define SYSCON_DCGC2_GPIOH (1 << 7) /* Bit 7: Port H Clock Gating Control */ -#define SYSCON_DCGC2_EMAC0 (1 << 28) /* Bit 28: MAC0 Clock Gating Control */ -#define SYSCON_DCGC2_EPHY0 (1 << 30) /* Bit 30: PHY0 Clock Gating Control */ - -/* Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 */ - -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) -#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ -#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h b/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h deleted file mode 100644 index 58447793d..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm3s_vectors.h +++ /dev/null @@ -1,439 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm3s_vectors.S - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Preprocessor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Vectors - ************************************************************************************/ - -/* This file is included by lm_vectors.S. It provides the macro VECTOR that - * supplies ach Stellaris vector in terms of a (lower-case) ISR label and an - * (upper-case) IRQ number as defined in arch/arm/include/lm/lm3s_irq.h. - * lm_vectors.S will define the VECTOR in different ways in order to generate - * the interrupt vectors and handlers in their final form. - */ - -#if defined(CONFIG_ARCH_CHIP_LM3S6918) - -/* If the common ARMv7-M vector handling is used, then all it needs is the following - * definition that provides the number of supported vectors. - */ - -#ifdef CONFIG_ARMV7M_CMNVECTOR - -/* Reserve 71 interrupt table entries for I/O interrupts. */ - -# define ARMV7M_PERIPHERAL_INTERRUPTS 71 - -#else - -VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ -VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ -VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ -VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ - -VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ -VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ -VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ -VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ -VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ -UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */ -UNUSED(LM_RESERVED_26) /* Vector 26: Reserved */ -UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */ -UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */ -UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */ - -VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ -VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ -VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ -VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ -VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ -VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ -VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ -VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ -VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ -VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ - -VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ -VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ -VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ -UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ -VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ -VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ -VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ -VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ -VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */ -UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */ - -VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: SSI 1 */ -VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ -VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ -VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ -UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */ -UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */ -UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ -UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ -VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ -VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */ - -UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ -UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ -UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ -UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ -UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ -UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ -UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ -UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ -UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ -UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ - -UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ -#endif - -#elif defined(CONFIG_ARCH_CHIP_LM3S6432) - -/* If the common ARMv7-M vector handling is used, then all it needs is the following - * definition that provides the number of supported vectors. - */ - -#ifdef CONFIG_ARMV7M_CMNVECTOR - -/* Reserve 71 interrupt table entries for I/O interrupts. */ - -# define ARMV7M_PERIPHERAL_INTERRUPTS 71 - -#else - -VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ -VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ -VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ -VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ - -VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ -VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ -VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ -VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ -VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ -UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */ -VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ -UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */ -UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */ -UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */ - -VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ -VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ -VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ -VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ -VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ -VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ -VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ -VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ -VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ -VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ - -VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ -VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ -VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ -UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ -VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ -VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ -VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ -VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ -UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */ -UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */ - -UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */ -UNUSED(LM_RESERVED_51) /* Vector 51: Reserved */ -UNUSED(LM_RESERVED_52) /* Vector 52: Reserved */ -UNUSED(LM_RESERVED_53) /* Vector 53: Reserved */ -UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */ -UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */ -UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ -UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ -VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ -UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */ - -UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ -UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ -UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ -UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ -UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ -UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ -UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ -UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ -UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ -UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ - -UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ -#endif - -#elif defined(CONFIG_ARCH_CHIP_LM3S6965) - -/* If the common ARMv7-M vector handling is used, then all it needs is the following - * definition that provides the number of supported vectors. - */ - -#ifdef CONFIG_ARMV7M_CMNVECTOR - -/* Reserve 71 interrupt table entries for I/O interrupts. */ - -# define ARMV7M_PERIPHERAL_INTERRUPTS 71 - -#else - -VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ -VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ -VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ -VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ - -VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ -VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ -VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ -VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ -VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ -VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */ -VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ -VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */ -VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */ -VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */ - -VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ -VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ -VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ -VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ -VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ -VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ -VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ -VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ -VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ -VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ - -VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ -VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ -VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ -UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ -VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ -VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ -VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ -VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ -UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */ -VECTOR(lm_uart2, LM_IRQ_UART1) /* Vector 49: UART 1 */ - -UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */ -VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ -VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ -VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ -VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */ -UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */ -UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ -UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ -VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ -VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */ - -UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ -UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ -UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ -UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ -UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ -UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ -UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ -UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ -UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ -UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ - -UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ -#endif - -#elif defined(CONFIG_ARCH_CHIP_LM3S8962) - -/* If the common ARMv7-M vector handling is used, then all it needs is the following - * definition that provides the number of supported vectors. - */ - -#ifdef CONFIG_ARMV7M_CMNVECTOR - -/* Reserve 71 interrupt table entries for I/O interrupts. */ - -# define ARMV7M_PERIPHERAL_INTERRUPTS 71 - -#else - -VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ -VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ -VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ -VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ - -VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ -VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ -VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ -VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ -VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ -VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */ -VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ -VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */ -VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */ -VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */ - -VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ -VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ -VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ -VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ -VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ -VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ -VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ -VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ -VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ -VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ - -VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ -VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ -UNUSED(LM_RESERVED_42) /* Vector 42: Reserved */ -UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ -VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ -VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ -VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ -VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ -UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */ -UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */ - -UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */ -VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ -VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ -VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ -VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */ -VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */ -UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ -UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ -VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ -VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */ - -UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */ -UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ -UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */ -UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */ -UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */ -UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */ -UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */ -UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */ -UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ -UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ - -UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ -#endif - -#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) - -/* If the common ARMv7-M vector handling is used, then all it needs is the following - * definition that provides the number of supported vectors. - */ - -#ifdef CONFIG_ARMV7M_CMNVECTOR - -/* Reserve 72 interrupt table entries for I/O interrupts. */ - -# define ARMV7M_PERIPHERAL_INTERRUPTS 72 - -#else - -VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ -VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ -VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ -VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ -VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ - -VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ -VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ -VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ -VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ -VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */ -VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */ -VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */ -VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */ -VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */ - -VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ -VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ -VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ -VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ -VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */ -VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */ -VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */ -VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */ -VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */ -VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */ - -VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */ -VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ -VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ -VECTOR(lm_cmp2, LM_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 */ -VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ -VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */ -VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ -VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */ -VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */ -VECTOR(lm_uart2, LM_IRQ_UART2) /* Vector 49: UART 2 */ - -VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: GPIO Port H */ -VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */ -VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */ -VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ -VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */ -VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */ -VECTOR(lm_can1, LM_IRQ_CAN1) /* Vector 56: CAN 1 */ -UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ -VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */ -UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */ - -VECTOR(lm_usb, LM_IRQ_USB) /* Vector 60: USB */ -VECTOR(lm_pwm3, LM_IRQ_PWM3) /* Vector 61: PWM 3 */ -VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software */ -VECTOR(lm_udmaerror, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */ -VECTOR(lm_adc1_0, LM_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */ -VECTOR(lm_adc1_1, LM_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */ -VECTOR(lm_adc1_2, LM_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */ -VECTOR(lm_adc1_3, LM_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */ -VECTOR(lm_i2s0, LM_IRQ_I2S0) /* Vector 68: I2S 0 */ -VECTOR(lm_epi, LM_IRQ_EPI) /* Vector 69: EPI */ - -VECTOR(lm_gpioj, LM_IRQ_GPIOJ) /* Vector 70: GPIO Port J */ -UNUSED(LM_RESERVED_71) /* Vector 71: Reserved */ -#endif - -#else -# error "Vectors not specified for this Stellaris chip" -#endif diff --git a/nuttx/arch/arm/src/lm/chip/lm4f_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm4f_memorymap.h deleted file mode 100644 index 4d715e470..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm4f_memorymap.h +++ /dev/null @@ -1,171 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm4f_memorymap.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt <gnutt@nuttx.org> - * Jose Pablo Carballo <jcarballo@nx-engineering.com> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM4F_MEMORYMAP_H -#define __ARCH_ARM_SRC_LM_CHIP_LM4F_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory map ***********************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_LM4F120) -# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ - /* -0x00ffffff: Reserved */ -# define LM_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */ -# define LM_SRAM_BASE 0x20000000 /* -0x20007fff: Bit-banded on-chip SRAM */ - /* -0x21ffffff: Reserved */ -# define LM_ASRAM_BASE 0x22000000 /* -0x220fffff: Bit-band alias of 20000000- */ - /* -0x3fffffff: Reserved */ -# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ - /* -0x41ffffff: Peripherals */ -# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alias of 40000000- */ - /* -0xdfffffff: Reserved */ -# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ -# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ -# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ -# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ - /* -0xe003ffff: Reserved */ -# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ -# define LM_ETM_BASE 0xe0041000 /* -0xe0041fff: Embedded Trace Macrocell */ - /* -0xffffffff: Reserved */ -#else -# error "Memory map not specified for this LM4F chip" -#endif - -/* Peripheral base addresses ********************************************************/ - -#if defined(CONFIG_ARCH_CHIP_LM4F120) -/* FiRM Peripheral Base Addresses */ - -# define LM_WDOG0_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */ -# define LM_WDOG1_BASE (LM_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */ - /* -0x03fff: Reserved */ -# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ -# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ -# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ -# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ -# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ -# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */ -# define LM_SSI2_BASE (LM_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */ -# define LM_SSI3_BASE (LM_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */ -# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ -# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ -# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */ -# define LM_UART3_BASE (LM_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */ -# define LM_UART4_BASE (LM_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */ -# define LM_UART5_BASE (LM_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */ -# define LM_UART6_BASE (LM_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */ -# define LM_UART7_BASE (LM_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */ - /* -0x1ffff: Reserved */ -/* Peripheral Base Addresses */ - -# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ -# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fbf: I2C Slave 0 */ -# define LM_I2CSC0_BASE (LM_PERIPH_BASE + 0x20fc0) /* -0x20fff: I2C Status and Control 0 */ -# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ -# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fbf: I2C Slave 1 */ -# define LM_I2CSC1_BASE (LM_PERIPH_BASE + 0x21fc0) /* -0x21fff: I2C Status and Control 1 */ -# define LM_I2CM2_BASE (LM_PERIPH_BASE + 0x22000) /* -0x227ff: I2C Master 2 */ -# define LM_I2CS2_BASE (LM_PERIPH_BASE + 0x22800) /* -0x22fbf: I2C Slave 2 */ -# define LM_I2CSC2_BASE (LM_PERIPH_BASE + 0x22fc0) /* -0x22fff: I2C Status and Control 2 */ -# define LM_I2CM3_BASE (LM_PERIPH_BASE + 0x23000) /* -0x237ff: I2C Master 3 */ -# define LM_I2CS3_BASE (LM_PERIPH_BASE + 0x23800) /* -0x23fbf: I2C Slave 3 */ -# define LM_I2CSC3_BASE (LM_PERIPH_BASE + 0x23fc0) /* -0x23fff: I2C Status and Control 3 */ -# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ -# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ - /* -0x2ffff: Reserved */ -# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */ -# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */ -# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */ -# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */ -# define LM_TIMER4_BASE (LM_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */ -# define LM_TIMER5_BASE (LM_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */ -# define LM_WTIMER0_BASE (LM_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */ -# define LM_WTIMER1_BASE (LM_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */ -# define LM_ADC0_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ -# define LM_ADC1_BASE (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ - /* -0x3bfff: Reserved */ -# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ - /* -0x43fff: Reserved */ -# define LM_CANCON_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */ - /* -0x4bfff: Reserved */ -# define LM_WTIMER2_BASE (LM_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */ -# define LM_WTIMER3_BASE (LM_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */ -# define LM_WTIMER4_BASE (LM_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */ -# define LM_WTIMER5_BASE (LM_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */ -# define LM_USB_BASE (LM_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ - /* -0x57fff: Reserved */ -# define LM_GPIOAAHB_BASE (LM_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ -# define LM_GPIOBAHB_BASE (LM_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ -# define LM_GPIOCAHB_BASE (LM_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ -# define LM_GPIODAHB_BASE (LM_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ -# define LM_GPIOEAHB_BASE (LM_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ -# define LM_GPIOFAHB_BASE (LM_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ - /* -0xaefff: Reserved */ -# define LM_EEPROM_BASE (LM_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */ - /* -0xf8fff: Reserved */ -# define LM_SYSEXC_BASE (LM_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */ - /* -0xfbfff: Reserved */ -# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */ -# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ -# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ -# define LM_UDMA_BASE (LM_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */ -#else -# error "Peripheral base addresses not specified for this Stellaris chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM4F_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm4f_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm4f_pinmap.h deleted file mode 100644 index 6f4bc27a6..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm4f_pinmap.h +++ /dev/null @@ -1,215 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm4f_pinmap.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM4F_PINMAP_H -#define __ARCH_ARM_SRC_LM_CHIP_LM4F_PINMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Alternate Pin Functions. All members of the LM4F family share the same pin - * multiplexing (although they may differ in the pins physically available). - * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if - * CAN1_RX connects vis PA11 on some board, then the following definitions should - * appear inthe board.h header file for that board: - * - * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 - * - * The driver will then automatically configre PA11 as the CAN1 RX pin. - */ - -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. - */ - -#if defined(CONFIG_ARCH_CHIP_LM4F120) - -# define GPIO_ADC_IN0 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_3) -# define GPIO_ADC_IN1 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_2) -# define GPIO_ADC_IN2 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_1) -# define GPIO_ADC_IN3 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_0) -# define GPIO_ADC_IN4 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_3) -# define GPIO_ADC_IN5 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_2) -# define GPIO_ADC_IN6 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_1) -# define GPIO_ADC_IN7 (GPIO_FUNC_ANINPUT | GPIO_PORTD | GPIO_PIN_0) -# define GPIO_ADC_IN8 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_5) -# define GPIO_ADC_IN9 (GPIO_FUNC_ANINPUT | GPIO_PORTE | GPIO_PIN_4) -# define GPIO_ADC_IN10 (GPIO_FUNC_ANINPUT | GPIO_PORTB | GPIO_PIN_4) -# define GPIO_ADC_IN11 (GPIO_FUNC_ANINPUT | GPIO_PORTB | GPIO_PIN_5) - -# define GPIO_CAN0_RX_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_3 | GPIO_PORTF | GPIO_PIN_0) -# define GPIO_CAN0_RX_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTB | GPIO_PIN_4) -# define GPIO_CAN0_RX_3 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTE | GPIO_PIN_4) -# define GPIO_CAN0_TX_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_3 | GPIO_PORTF | GPIO_PIN_3) -# define GPIO_CAN0_TX_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTB | GPIO_PIN_5) -# define GPIO_CAN0_TX_3 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTE | GPIO_PIN_5) - -# define GPIO_CMP0_NIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_7) -# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_ALT_9 | GPIO_PORTF | GPIO_PIN_0) -# define GPIO_CMP0_PIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_6) -# define GPIO_CMP1_NIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_4) -# define GPIO_CMP1_OUT (GPIO_FUNC_PFOUTPUT | GPIO_ALT_9 | GPIO_PORTF | GPIO_PIN_1) -# define GPIO_CMP1_PIN (GPIO_FUNC_ANINPUT | GPIO_PORTC | GPIO_PIN_5) - -# define GPIO_CORE_TRCLK (GPIO_FUNC_PFOUTPUT | GPIO_ALT_14 | GPIO_PORTF | GPIO_PIN_3) -# define GPIO_CORE_TRD0 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_14 | GPIO_PORTF | GPIO_PIN_2) -# define GPIO_CORE_TRD1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_14 | GPIO_PORTF | GPIO_PIN_1) - -# define GPIO_I2C0_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTB | GPIO_PIN_2) -# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTB | GPIO_PIN_3) -# define GPIO_I2C1_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTA | GPIO_PIN_6) -# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTA | GPIO_PIN_7) -# define GPIO_I2C2_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTE | GPIO_PIN_4) -# define GPIO_I2C2_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTE | GPIO_PIN_5) -# define GPIO_I2C3_SCL (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTD | GPIO_PIN_0) -# define GPIO_I2C3_SDA (GPIO_FUNC_PFODIO | GPIO_ALT_3 | GPIO_PORTD | GPIO_PIN_1) - -# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_0) -# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_1) -# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_3) -# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_0) -# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_2) -# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_3) -# define GPIO_JTAG_TMS (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_1) - -# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_2) -# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_3) -# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_4) -# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTA | GPIO_PIN_5) -# define GPIO_SSI1_CLK_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_0) -# define GPIO_SSI1_CLK_2 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_2) -# define GPIO_SSI1_FSS_1 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_1) -# define GPIO_SSI1_FSS_2 (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_3) -# define GPIO_SSI1_RX_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_2) -# define GPIO_SSI1_RX_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_0) -# define GPIO_SSI1_TX_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTD | GPIO_PIN_3) -# define GPIO_SSI1_TX_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTF | GPIO_PIN_1) -# define GPIO_SSI2_CLK (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_4) -# define GPIO_SSI2_FSS (GPIO_FUNC_PFIO | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_5) -# define GPIO_SSI2_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_6) -# define GPIO_SSI2_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTB | GPIO_PIN_7) -# define GPIO_SSI3_CLK (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_0) -# define GPIO_SSI3_FSS (GPIO_FUNC_PFIO | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_1) -# define GPIO_SSI3_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_2) -# define GPIO_SSI3_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_3) - -# define GPIO_SYSCON_NMI_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTD | GPIO_PIN_7) -# define GPIO_SYSCON_NMI_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTF | GPIO_PIN_0) - -# define GPIO_TIM0_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_6) -# define GPIO_TIM0_CCP0_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_0) -# define GPIO_TIM0_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_7) -# define GPIO_TIM0_CCP1_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_1) -# define GPIO_TIM1_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_4) -# define GPIO_TIM1_CCP0_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_2) -# define GPIO_TIM1_CCP1_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_5) -# define GPIO_TIM1_CCP1_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_3) -# define GPIO_TIM2_CCP0_1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_0) -# define GPIO_TIM2_CCP0_2 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTF | GPIO_PIN_4) -# define GPIO_TIM2_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_1) -# define GPIO_TIM3_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_2) -# define GPIO_TIM3_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTB | GPIO_PIN_3) -# define GPIO_TIM4_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_0) -# define GPIO_TIM4_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_1) -# define GPIO_TIM5_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_2) -# define GPIO_TIM5_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_3) - -# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTA | GPIO_PIN_0) -# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTA | GPIO_PIN_1) -# define GPIO_UART1_CTS_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTF | GPIO_PIN_1) -# define GPIO_UART1_CTS_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_8 | GPIO_PORTC | GPIO_PIN_5) -# define GPIO_UART1_RTS_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTF | GPIO_PIN_0) -# define GPIO_UART1_RTS_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_8 | GPIO_PORTC | GPIO_PIN_4) -# define GPIO_UART1_RX_1 (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTB | GPIO_PIN_0) -# define GPIO_UART1_RX_2 (GPIO_FUNC_PFINPUT | GPIO_ALT_2 | GPIO_PORTC | GPIO_PIN_4) -# define GPIO_UART1_TX_1 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTB | GPIO_PIN_1) -# define GPIO_UART1_TX_2 (GPIO_FUNC_PFOUTPUT | GPIO_ALT_2 | GPIO_PORTC | GPIO_PIN_5) -# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_6) -# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_7) -# define GPIO_UART3_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_6) -# define GPIO_UART3_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_7) -# define GPIO_UART4_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_4) -# define GPIO_UART4_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTC | GPIO_PIN_5) -# define GPIO_UART5_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_4) -# define GPIO_UART5_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_5) -# define GPIO_UART6_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_4) -# define GPIO_UART6_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTD | GPIO_PIN_5) -# define GPIO_UART7_RX (GPIO_FUNC_PFINPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_0) -# define GPIO_UART7_TX (GPIO_FUNC_PFOUTPUT | GPIO_ALT_1 | GPIO_PORTE | GPIO_PIN_1) - -# define GPIO_USB0_DM (GPIO_FUNC_ANIO | GPIO_PORTD | GPIO_PIN_4) -# define GPIO_USB0_DP (GPIO_FUNC_ANIO | GPIO_PORTD | GPIO_PIN_5) - -# define GPIO_WTIM0_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_4) -# define GPIO_WTIM0_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_5) -# define GPIO_WTIM1_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_6) -# define GPIO_WTIM1_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTC | GPIO_PIN_7) -# define GPIO_WTIM2_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_0) -# define GPIO_WTIM2_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_1) -# define GPIO_WTIM3_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_2) -# define GPIO_WTIM3_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_3) -# define GPIO_WTIM4_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_4) -# define GPIO_WTIM4_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_5) -# define GPIO_WTIM5_CCP0 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_6) -# define GPIO_WTIM5_CCP1 (GPIO_FUNC_PFIO | GPIO_ALT_7 | GPIO_PORTD | GPIO_PIN_7) - -#else -# error "Unknown Stellaris chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM4F_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm4f_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm4f_syscontrol.h deleted file mode 100644 index cc7659f29..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm4f_syscontrol.h +++ /dev/null @@ -1,1532 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/lm/chip/lm4f_syscontrol.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM4F_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM_CHIP_LM4F_SYSCONTROL_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include <nuttx/config.h> - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* System Control Register Offsets **********************************************************/ - -#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ -#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ -#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */ -#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */ -#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */ -#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */ -#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */ -#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */ -#define LM_SYSCON_GPIOHBCTL_OFFSET 0x06c /* GPIO High-Performance Bus Control */ -#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */ -#define LM_SYSCON_MOSCCTL_OFFSET 0x07c /* Main Oscillator Control */ -#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration */ -#define LM_SYSCON_SYSPROP_OFFSET 0x14c /* System Properties */ -#define LM_SYSCON_PIOSCCAL_OFFSET 0x150 /* Precision Internal Oscillator Calibration */ -#define LM_SYSCON_PIOSCSTAT_OFFSET 0x154 /* Precision Internal Oscillator Statistics */ -#define LM_SYSCON_PLLFREQ0_OFFSET 0x160 /* PLL 0 Frequency */ -#define LM_SYSCON_PLLFREQ1_OFFSET 0x164 /* PLL 1 Frequency */ -#define LM_SYSCON_PLLSTAT_OFFSET 0x168 /* PLL Status */ - -#define LM_SYSCON_PPWD_OFFSET 0x300 /* Watchdog Timer Peripheral Present */ -#define LM_SYSCON_PPTIMER_OFFSET 0x304 /* 16/32-Bit Timer Peripheral Present */ -#define LM_SYSCON_PPGPIO_OFFSET 0x308 /* GPIO Peripheral Present */ -#define LM_SYSCON_PPDMA_OFFSET 0x30c /* uDMA Peripheral Present */ -#define LM_SYSCON_PPHIB_OFFSET 0x314 /* Hibernation Peripheral Present */ -#define LM_SYSCON_PPUART_OFFSET 0x318 /* UART Present */ -#define LM_SYSCON_PPSSI_OFFSET 0x31c /* SSI Peripheral Present */ -#define LM_SYSCON_PPI2C_OFFSET 0x320 /* I2C Peripheral Present */ -#define LM_SYSCON_PPUSB_OFFSET 0x328 /* USB Peripheral Present */ -#define LM_SYSCON_PPCAN_OFFSET 0x334 /* CAN Peripheral Present */ -#define LM_SYSCON_PPADC_OFFSET 0x338 /* ADC Peripheral Present */ -#define LM_SYSCON_PPACMP_OFFSET 0x33c /* Analog Comparator Peripheral Present */ -#define LM_SYSCON_PPPWM_OFFSET 0x340 /* Pulse Width Modulator Peripheral Present */ -#define LM_SYSCON_PPQEI_OFFSET 0x344 /* Quadrature Encoder Peripheral Present */ -#define LM_SYSCON_PPEEPROM_OFFSET 0x358 /* EEPROM Peripheral Present */ -#define LM_SYSCON_PPWTIMER_OFFSET 0x35c /* 32/64-Bit Wide Timer Peripheral Present */ - -#define LM_SYSCON_SRWD_OFFSET 0x500 /* Watchdog Timer Software Reset */ -#define LM_SYSCON_SRTIMER_OFFSET 0x504 /* 16/32-Bit Timer Software Reset */ -#define LM_SYSCON_SRGPIO_OFFSET 0x508 /* GPIO Software Reset */ -#define LM_SYSCON_SRDMA_OFFSET 0x50c /* uDMA Software Reset */ -#define LM_SYSCON_SRHIB_OFFSET 0x514 /* Hibernation Software Reset */ -#define LM_SYSCON_SRUART_OFFSET 0x518 /* UART Software Reset*/ -#define LM_SYSCON_SRSSI_OFFSET 0x51c /* SSI Software Reset */ -#define LM_SYSCON_SRI2C_OFFSET 0x520 /* I2C Software Reset */ -#define LM_SYSCON_SRUSB_OFFSET 0x528 /* USB Software Reset */ -#define LM_SYSCON_SRCAN_OFFSET 0x534 /* CAN Software Reset */ -#define LM_SYSCON_SRADC_OFFSET 0x538 /* ADC Software Reset */ -#define LM_SYSCON_SRACMP_OFFSET 0x53c /* Analog Comparator Software Reset */ -#define LM_SYSCON_SREEPROM_OFFSET 0x558 /* EEPROM Software Reset */ -#define LM_SYSCON_SRWTIMER_OFFSET 0x55c /* 32/64-Bit Wide Timer Software Reset */ - -#define LM_SYSCON_RCGCWD_OFFSET 0x600 /* Watchdog Timer Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCTIMER_OFFSET 0x604 /* 16/32-Bit Timer Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCGPIO_OFFSET 0x608 /* GPIO Run Mode Clock Gating Control*/ -#define LM_SYSCON_RCGCDMA_OFFSET 0x60c /* uDMA Run Mode Clock Gating Control*/ -#define LM_SYSCON_RCGCHIB_OFFSET 0x614 /* Hibernation Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCUART_OFFSET 0x618 /* UART Run Mode Clock Gating Control*/ -#define LM_SYSCON_RCGCSSI_OFFSET 0x61c /* SSI Run Mode Clock Gating Control*/ -#define LM_SYSCON_RCGCI2C_OFFSET 0x620 /* I2C Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCUSB_OFFSET 0x628 /* USB Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCCAN_OFFSET 0x634 /* CAN Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCADC_OFFSET 0x638 /* ADC Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCACMP_OFFSET 0x63c /* Analog Comparator Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCEEPROM_OFFSET 0x658 /* EEPROM Run Mode Clock Gating Control */ -#define LM_SYSCON_RCGCWTIMER_OFFSET 0x65c /* 32/64-BitWide Timer Run Mode Clock Gating Control */ - -#define LM_SYSCON_SCGCWD_OFFSET 0x700 /* Watchdog Timer Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCTIMER_OFFSET 0x704 /* 16/32-Bit Timer Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCGPIO_OFFSET 0x708 /* GPIO Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCDMA_OFFSET 0x70c /* uDMA Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCHIB_OFFSET 0x714 /* Hibernation Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCUART_OFFSET 0x718 /* UART Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCSSI_OFFSET 0x71c /* SSI Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCI2C_OFFSET 0x720 /* I2C Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCUSB_OFFSET 0x728 /* USB Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCCAN_OFFSET 0x734 /* CAN Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCADC_OFFSET 0x738 /* ADC Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCACMP_OFFSET 0x73c /* Analog Comparator Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCEEPROM_OFFSET 0x758 /* EEPROM Sleep Mode Clock Gating Control */ -#define LM_SYSCON_SCGCWTIMER_OFFSET 0x75c /* 32/64-BitWide Timer Sleep Mode Clock Gating Control */ - -#define LM_SYSCON_DCGCWD_OFFSET 0x800 /* Watchdog Timer Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCTIMER_OFFSET 0x804 /* Clock Gating Control */ -#define LM_SYSCON_DCGCGPIO_OFFSET 0x808 /* GPIO Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCDMA_OFFSET 0x80c /* uDMA Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCHIB_OFFSET 0x814 /* Hibernation Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCUART_OFFSET 0x818 /* UART Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCSSI_OFFSET 0x81c /* SSI Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCI2C_OFFSET 0x820 /* I2C Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCUSB_OFFSET 0x828 /* USB Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCCAN_OFFSET 0x834 /* CAN Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCADC_OFFSET 0x838 /* ADC Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCACMP_OFFSET 0x83c /* Analog Comparator Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCEEPROM_OFFSET 0x858 /* EEPROM Deep-Sleep Mode Clock Gating Control */ -#define LM_SYSCON_DCGCWTIMER_OFFSET 0x85c /* 32/64-BitWide Timer Deep-Sleep Mode Clock Gating Control */ - -#define LM_SYSCON_PRWD_OFFSET 0xa00 /* Watchdog Timer Peripheral Ready */ -#define LM_SYSCON_PRTIMER_OFFSET 0xa04 /* 16/32-Bit Timer Peripheral Ready */ -#define LM_SYSCON_PRGPIO_OFFSET 0xa08 /* GPIO Peripheral Ready */ -#define LM_SYSCON_PRDMA_OFFSET 0xa0c /* uDMA Peripheral Ready */ -#define LM_SYSCON_PRHIB_OFFSET 0xa14 /* Hibernation Peripheral Ready */ -#define LM_SYSCON_PRUART_OFFSET 0xa18 /* UART Peripheral Ready */ -#define LM_SYSCON_PRSSI_OFFSET 0xa1c /* SSI Peripheral Ready */ -#define LM_SYSCON_PRI2C_OFFSET 0xa20 /* I2C Peripheral Ready */ -#define LM_SYSCON_PRUSB_OFFSET 0xa28 /* USB Peripheral Ready */ -#define LM_SYSCON_PRCAN_OFFSET 0xa34 /* CAN Peripheral Ready */ -#define LM_SYSCON_PRADC_OFFSET 0xa38 /* ADC Peripheral Ready */ -#define LM_SYSCON_PRACMP_OFFSET 0xa3c /* Analog Comparator Peripheral Ready */ -#define LM_SYSCON_PREEPROM_OFFSET 0xa58 /* EEPROM Peripheral Ready */ -#define LM_SYSCON_PRWTIMER_OFFSET 0xa5c /* 2/64-BitWide Timer Peripheral Ready */ - -/* System Control Legacy Register Offsets ***************************************************/ - -#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ -#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ -#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */ -#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */ -#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */ -#define LM_SYSCON_DC5_OFFSET 0x020 /* Device Capabilities 5 */ -#define LM_SYSCON_DC6_OFFSET 0x024 /* Device Capabilities 6 */ -#define LM_SYSCON_DC7_OFFSET 0x028 /* Device Capabilities 7 */ -#define LM_SYSCON_DC8_OFFSET 0x02c /* Device Capabilities 8 */ - -#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */ -#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */ -#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2 */ - -#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */ -#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */ -#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */ - -#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */ -#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */ -#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */ - -#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */ -#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */ -#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ - -#define LM_SYSCON_DC9_OFFSET 0x190 /* Device Capabilities */ -#define LM_SYSCON_NVMSTAT_OFFSET 0x1a0 /* Non-Volatile Memory Information */ - -/* System Control Register Addresses ********************************************************/ - -#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET) -#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET) -#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET) -#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET) -#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET) -#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET) -#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET) -#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET) -#define LM_SYSCON_GPIOHBCTL (LM_SYSCON_BASE + LM_SYSCON_GPIOHBCTL_OFFSET) -#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET) -#define LM_SYSCON_MOSCCTL (LM_SYSCON_BASE + LM_SYSCON_MOSCCTL_OFFSET) -#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET) -#define LM_SYSCON_SYSPROP (LM_SYSCON_BASE + LM_SYSCON_SYSPROP_OFFSET) -#define LM_SYSCON_PIOSCCAL (LM_SYSCON_BASE + LM_SYSCON_PIOSCCAL_OFFSET) -#define LM_SYSCON_PIOSCSTAT (LM_SYSCON_BASE + LM_SYSCON_PIOSCSTAT_OFFSET) -#define LM_SYSCON_PLLFREQ0 (LM_SYSCON_BASE + LM_SYSCON_PLLFREQ0_OFFSET) -#define LM_SYSCON_PLLFREQ1 (LM_SYSCON_BASE + LM_SYSCON_PLLFREQ1_OFFSET) -#define LM_SYSCON_PLLSTAT (LM_SYSCON_BASE + LM_SYSCON_PLLSTAT_OFFSET) - -#define LM_SYSCON_PPWD (LM_SYSCON_BASE + LM_SYSCON_PPWD_OFFSET) -#define LM_SYSCON_PPTIMER (LM_SYSCON_BASE + LM_SYSCON_PPTIMER_OFFSET) -#define LM_SYSCON_PPGPIO (LM_SYSCON_BASE + LM_SYSCON_PPGPIO_OFFSET) -#define LM_SYSCON_PPDMA (LM_SYSCON_BASE + LM_SYSCON_PPDMA_OFFSET) -#define LM_SYSCON_PPHIB (LM_SYSCON_BASE + LM_SYSCON_PPHIB_OFFSET) -#define LM_SYSCON_PPUART (LM_SYSCON_BASE + LM_SYSCON_PPUART_OFFSET) -#define LM_SYSCON_PPSSI (LM_SYSCON_BASE + LM_SYSCON_PPSSI_OFFSET) -#define LM_SYSCON_PPI2C (LM_SYSCON_BASE + LM_SYSCON_PPI2C_OFFSET) -#define LM_SYSCON_PPUSB (LM_SYSCON_BASE + LM_SYSCON_PPUSB_OFFSET) -#define LM_SYSCON_PPCAN (LM_SYSCON_BASE + LM_SYSCON_PPCAN_OFFSET) -#define LM_SYSCON_PPADC (LM_SYSCON_BASE + LM_SYSCON_PPADC_OFFSET) -#define LM_SYSCON_PPACMP (LM_SYSCON_BASE + LM_SYSCON_PPACMP_OFFSET) -#define LM_SYSCON_PPPWM (LM_SYSCON_BASE + LM_SYSCON_PPPWM_OFFSET) -#define LM_SYSCON_PPQEI (LM_SYSCON_BASE + LM_SYSCON_PPQEI_OFFSET) -#define LM_SYSCON_PPEEPROM (LM_SYSCON_BASE + LM_SYSCON_PPEEPROM_OFFSET) -#define LM_SYSCON_PPWTIMER (LM_SYSCON_BASE + LM_SYSCON_PPWTIMER_OFFSET) - -#define LM_SYSCON_SRWD (LM_SYSCON_BASE + LM_SYSCON_SRWD_OFFSET) -#define LM_SYSCON_SRTIMER (LM_SYSCON_BASE + LM_SYSCON_SRTIMER_OFFSET) -#define LM_SYSCON_SRGPIO (LM_SYSCON_BASE + LM_SYSCON_SRGPIO_OFFSET) -#define LM_SYSCON_SRDMA (LM_SYSCON_BASE + LM_SYSCON_SRDMA_OFFSET) -#define LM_SYSCON_SRHIB (LM_SYSCON_BASE + LM_SYSCON_SRHIB_OFFSET) -#define LM_SYSCON_SRUART (LM_SYSCON_BASE + LM_SYSCON_SRUART_OFFSET) -#define LM_SYSCON_SRSSI (LM_SYSCON_BASE + LM_SYSCON_SRSSI_OFFSET) -#define LM_SYSCON_SRI2C (LM_SYSCON_BASE + LM_SYSCON_SRI2C_OFFSET) -#define LM_SYSCON_SRUSB (LM_SYSCON_BASE + LM_SYSCON_SRUSB_OFFSET) -#define LM_SYSCON_SRCAN (LM_SYSCON_BASE + LM_SYSCON_SRCAN_OFFSET) -#define LM_SYSCON_SRADC (LM_SYSCON_BASE + LM_SYSCON_SRADC_OFFSET) -#define LM_SYSCON_SRACMP (LM_SYSCON_BASE + LM_SYSCON_SRACMP_OFFSET) -#define LM_SYSCON_SREEPROM (LM_SYSCON_BASE + LM_SYSCON_SREEPROM_OFFSET) -#define LM_SYSCON_SRWTIMER (LM_SYSCON_BASE + LM_SYSCON_SRWTIMER_OFFSET) - -#define LM_SYSCON_RCGCWD (LM_SYSCON_BASE + LM_SYSCON_RCGCWD_OFFSET) -#define LM_SYSCON_RCGCTIMER (LM_SYSCON_BASE + LM_SYSCON_RCGCTIMER_OFFSET) -#define LM_SYSCON_RCGCGPIO (LM_SYSCON_BASE + LM_SYSCON_RCGCGPIO_OFFSET) -#define LM_SYSCON_RCGCDMA (LM_SYSCON_BASE + LM_SYSCON_RCGCDMA_OFFSET) -#define LM_SYSCON_RCGCHIB (LM_SYSCON_BASE + LM_SYSCON_RCGCHIB_OFFSET) -#define LM_SYSCON_RCGCUART (LM_SYSCON_BASE + LM_SYSCON_RCGCUART_OFFSET) -#define LM_SYSCON_RCGCSSI (LM_SYSCON_BASE + LM_SYSCON_RCGCSSI_OFFSET) -#define LM_SYSCON_RCGCI2C (LM_SYSCON_BASE + LM_SYSCON_RCGCI2C_OFFSET) -#define LM_SYSCON_RCGCUSB (LM_SYSCON_BASE + LM_SYSCON_RCGCUSB_OFFSET) -#define LM_SYSCON_RCGCCAN (LM_SYSCON_BASE + LM_SYSCON_RCGCCAN_OFFSET) -#define LM_SYSCON_RCGCADC (LM_SYSCON_BASE + LM_SYSCON_RCGCADC_OFFSET) -#define LM_SYSCON_RCGCACMP (LM_SYSCON_BASE + LM_SYSCON_RCGCACMP_OFFSET) -#define LM_SYSCON_RCGCEEPROM (LM_SYSCON_BASE + LM_SYSCON_RCGCEEPROM_OFFSET) -#define LM_SYSCON_RCGCWTIMER (LM_SYSCON_BASE + LM_SYSCON_RCGCWTIMER_OFFSET) - -#define LM_SYSCON_SCGCWD (LM_SYSCON_BASE + LM_SYSCON_SCGCWD_OFFSET) -#define LM_SYSCON_SCGCTIMER (LM_SYSCON_BASE + LM_SYSCON_SCGCTIMER_OFFSET) -#define LM_SYSCON_SCGCGPIO (LM_SYSCON_BASE + LM_SYSCON_SCGCGPIO_OFFSET) -#define LM_SYSCON_SCGCDMA (LM_SYSCON_BASE + LM_SYSCON_SCGCDMA_OFFSET) -#define LM_SYSCON_SCGCHIB (LM_SYSCON_BASE + LM_SYSCON_SCGCHIB_OFFSET) -#define LM_SYSCON_SCGCUART (LM_SYSCON_BASE + LM_SYSCON_SCGCUART_OFFSET) -#define LM_SYSCON_SCGCSSI (LM_SYSCON_BASE + LM_SYSCON_SCGCSSI_OFFSET) -#define LM_SYSCON_SCGCI2C (LM_SYSCON_BASE + LM_SYSCON_SCGCI2C_OFFSET) -#define LM_SYSCON_SCGCUSB (LM_SYSCON_BASE + LM_SYSCON_SCGCUSB_OFFSET) -#define LM_SYSCON_SCGCCAN (LM_SYSCON_BASE + LM_SYSCON_SCGCCAN_OFFSET) -#define LM_SYSCON_SCGCADC (LM_SYSCON_BASE + LM_SYSCON_SCGCADC_OFFSET) -#define LM_SYSCON_SCGCACMP (LM_SYSCON_BASE + LM_SYSCON_SCGCACMP_OFFSET) -#define LM_SYSCON_SCGCEEPROM (LM_SYSCON_BASE + LM_SYSCON_SCGCEEPROM_OFFSET) -#define LM_SYSCON_SCGCWTIMER (LM_SYSCON_BASE + LM_SYSCON_SCGCWTIMER_OFFSET) - -#define LM_SYSCON_DCGCWD (LM_SYSCON_BASE + LM_SYSCON_DCGCWD_OFFSET) -#define LM_SYSCON_DCGCTIMER (LM_SYSCON_BASE + LM_SYSCON_DCGCTIMER_OFFSET) -#define LM_SYSCON_DCGCGPIO (LM_SYSCON_BASE + LM_SYSCON_DCGCGPIO_OFFSET) -#define LM_SYSCON_DCGCDMA (LM_SYSCON_BASE + LM_SYSCON_DCGCDMA_OFFSET) -#define LM_SYSCON_DCGCHIB (LM_SYSCON_BASE + LM_SYSCON_DCGCHIB_OFFSET) -#define LM_SYSCON_DCGCUART (LM_SYSCON_BASE + LM_SYSCON_DCGCUART_OFFSET) -#define LM_SYSCON_DCGCSSI (LM_SYSCON_BASE + LM_SYSCON_DCGCSSI_OFFSET) -#define LM_SYSCON_DCGCI2C (LM_SYSCON_BASE + LM_SYSCON_DCGCI2C_OFFSET) -#define LM_SYSCON_DCGCUSB (LM_SYSCON_BASE + LM_SYSCON_DCGCUSB_OFFSET) -#define LM_SYSCON_DCGCCAN (LM_SYSCON_BASE + LM_SYSCON_DCGCCAN_OFFSET) -#define LM_SYSCON_DCGCADC (LM_SYSCON_BASE + LM_SYSCON_DCGCADC_OFFSET) -#define LM_SYSCON_DCGCACMP (LM_SYSCON_BASE + LM_SYSCON_DCGCACMP_OFFSET) -#define LM_SYSCON_DCGCEEPROM (LM_SYSCON_BASE + LM_SYSCON_DCGCEEPROM_OFFSET) -#define LM_SYSCON_DCGCWTIMER (LM_SYSCON_BASE + LM_SYSCON_DCGCWTIMER_OFFSET) - -#define LM_SYSCON_PRWD (LM_SYSCON_BASE + LM_SYSCON_PRWD_OFFSET) -#define LM_SYSCON_PRTIMER (LM_SYSCON_BASE + LM_SYSCON_PRTIMER_OFFSET) -#define LM_SYSCON_PRGPIO (LM_SYSCON_BASE + LM_SYSCON_PRGPIO_OFFSET) -#define LM_SYSCON_PRDMA (LM_SYSCON_BASE + LM_SYSCON_PRDMA_OFFSET) -#define LM_SYSCON_PRHIB (LM_SYSCON_BASE + LM_SYSCON_PRHIB_OFFSET) -#define LM_SYSCON_PRUART (LM_SYSCON_BASE + LM_SYSCON_PRUART_OFFSET) -#define LM_SYSCON_PRSSI (LM_SYSCON_BASE + LM_SYSCON_PRSSI_OFFSET) -#define LM_SYSCON_PRI2C (LM_SYSCON_BASE + LM_SYSCON_PRI2C_OFFSET) -#define LM_SYSCON_PRUSB (LM_SYSCON_BASE + LM_SYSCON_PRUSB_OFFSET) -#define LM_SYSCON_PRCAN (LM_SYSCON_BASE + LM_SYSCON_PRCAN_OFFSET) -#define LM_SYSCON_PRADC (LM_SYSCON_BASE + LM_SYSCON_PRADC_OFFSET) -#define LM_SYSCON_PRACMP (LM_SYSCON_BASE + LM_SYSCON_PRACMP_OFFSET) -#define LM_SYSCON_PREEPROM (LM_SYSCON_BASE + LM_SYSCON_PREEPROM_OFFSET) -#define LM_SYSCON_PRWTIMER (LM_SYSCON_BASE + LM_SYSCON_PRWTIMER_OFFSET) - -/* System Control Legacy Register Addresses *************************************************/ - -#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET) -#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET) -#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET) -#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET) -#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET) -#define LM_SYSCON_DC5 (LM_SYSCON_BASE + LM_SYSCON_DC5_OFFSET) -#define LM_SYSCON_DC6 (LM_SYSCON_BASE + LM_SYSCON_DC6_OFFSET) -#define LM_SYSCON_DC7 (LM_SYSCON_BASE + LM_SYSCON_DC7_OFFSET) -#define LM_SYSCON_DC8 (LM_SYSCON_BASE + LM_SYSCON_DC8_OFFSET) - -#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET) -#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET) -#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET) - -#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET) -#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET) -#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET) - -#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET) -#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET) -#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET) - -#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET) -#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET) -#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET) - -#define LM_SYSCON_DC9 (LM_SYSCON_BASE + LM_SYSCON_DC9_OFFSET) -#define LM_SYSCON_NVMSTAT (LM_SYSCON_BASE + LM_SYSCON_NVMSTAT_OFFSET) - -/* System Control Register Bit Definitions **************************************************/ - -/* Device Identification 0 */ - -#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 7-0: Minor Revision of the device */ -#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT) -#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 15-8: Major Revision of the device */ -#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) -#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 23-16: Device Class */ -#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) -#define SYSCON_DID0_VER_SHIFT 28 /* Bits 30-28: DID0 Version */ -#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) - -/* Device Identification 1 */ - -#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ -#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) -#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ -#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ -#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) -#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ -#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) -#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 15-13: Package Pin Count */ -#define SYSCON_DID1_PINCOUNT_MASK (0x07 << SYSCON_DID1_PINCOUNT_SHIFT) -#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 23-16: Part Number */ -#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) -#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 27-24: Family */ -#define SYSCON_DID1_FAM_MASK (0x0f << SYSCON_DID1_FAM_SHIFT) -#define SYSCON_DID1_VER_SHIFT 28 /* Bits 31-28: DID1 Version */ -#define SYSCON_DID1_VER_MASK (0x0f << SYSCON_DID1_VER_SHIFT) - -/* Brown-Out Reset Control */ - -#define SYSCON_PBORCTL_BORI1 (1 << 1) /* Bit 1: VDD under BOR1 Event Action */ -#define SYSCON_PBORCTL_BORI0 (1 << 2) /* Bit 2: VDD under BOR0 Event Action */ - -/* Raw Interrupt Status */ - -#define SYSCON_RIS_BORR1RIS (1 << 1) /* Bit 1: VDD under BOR1 Raw Interrupt Status */ -#define SYSCON_RIS_MOFRIS (1 << 3) /* Bit 3: Main Oscillator Failure Raw Interrupt Status */ -#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */ -#define SYSCON_RIS_USBPLLLRIS (1 << 7) /* Bit 7: USB PLL Lock Raw Interrupt Status */ -#define SYSCON_RIS_MOSCPUPRIS (1 << 8) /* Bit 8: MOSC Power Up Raw Interrupt Status */ -#define SYSCON_RIS_VDDARIS (1 << 10) /* Bit 10: VDDA Power OK Event Raw Interrupt Status */ -#define SYSCON_RIS_BOR0RIS (1 << 11) /* Bit 11: VDD under BOR0 Raw Interrupt Status */ - -/* Interrupt Mask Control */ - -#define SYSCON_IMC_BORR1RIM (1 << 1) /* Bit 1: VDD under BOR1 Raw Interrupt Mask */ -#define SYSCON_IMC_MOFRIM (1 << 3) /* Bit 3: Main Oscillator Failure Raw Interrupt Mask */ -#define SYSCON_IMC_PLLLRIM (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Mask */ -#define SYSCON_IMC_USBPLLLRIM (1 << 7) /* Bit 7: USB PLL Lock Raw Interrupt Mask */ -#define SYSCON_IMC_MOSCPUPRIM (1 << 8) /* Bit 8: MOSC Power Up Raw Interrupt Mask */ -#define SYSCON_IMC_VDDARIM (1 << 10) /* Bit 10: VDDA Power OK Event Raw Interrupt Mask */ -#define SYSCON_IMC_BOR0RIM (1 << 11) /* Bit 11: VDD under BOR0 Raw Interrupt Mask */ - -/* Masked Interrupt Status and Clear */ - -#define SYSCON_MISC_BORR1MIS (1 << 1) /* Bit 1: VDD under BOR1 Masked Interrupt Status */ -#define SYSCON_MISC_MOFMIS (1 << 3) /* Bit 3: Main Oscillator Failure Masked Interrupt Status */ -#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */ -#define SYSCON_MISC_USBPLLLMIS (1 << 7) /* Bit 7: USB PLL Lock Masked Interrupt Status */ -#define SYSCON_MISC_MOSCPUPMIS (1 << 8) /* Bit 8: MOSC Power Up Masked Interrupt Status */ -#define SYSCON_MISC_VDDAMIS (1 << 10) /* Bit 10: VDDA Power OK Event Masked Interrupt Status */ -#define SYSCON_MISC_BOR0MIS (1 << 11) /* Bit 11: VDD under BOR0 Masked Interrupt Status */ - -/* Reset Cause */ - -#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */ -#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */ -#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */ -#define SYSCON_RESC_WDT0 (1 << 3) /* Bit 3: Watchdog Timer 0 Reset */ -#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */ -#define SYSCON_RESC_WDT1 (1 << 5) /* Bit 5: Watchdog Timer 1 Reset */ -#define SYSCON_RESC_MOSCFAIL (1 << 16) /* Bit 16: MOSC Failure Reset */ - -/* Run-Mode Clock Configuration */ - -#define SYSCON_RCC_MOSCDIS (1 << 0) /* Bit 0: Main Oscillator Disable */ -#define SYSCON_RCC_OSCSRC_SHIFT 4 /* Bits 5-4: Oscillator Source */ -#define SYSCON_RCC_OSCSRC_MASK (0x03 << SYSCON_RCC_OSCSRC_SHIFT) -# define SYSCON_RCC_OSCSRC_MOSC (0 << SYSCON_RCC_OSCSRC_SHIFT) /* Main oscillator */ -# define SYSCON_RCC_OSCSRC_PIOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator (reset) */ -# define SYSCON_RCC_OSCSRC_PIOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator / 4 */ -# define SYSCON_RCC_OSCSRC_LFIOSC (3 << SYSCON_RCC_OSCSRC_SHIFT) /* Low-frequency internal oscillator */ -#define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ -#define SYSCON_RCC_XTAL_MASK (31 << SYSCON_RCC_XTAL_SHIFT) -# define SYSCON_RCC_XTAL4000KHZ (6 << SYSCON_RCC_XTAL_SHIFT) /* 4 MHz (NO PLL) */ -# define SYSCON_RCC_XTAL4096KHZ (7 << SYSCON_RCC_XTAL_SHIFT) /* 4.096 MHz (NO PLL) */ -# define SYSCON_RCC_XTAL4915p2KHZ (8 << SYSCON_RCC_XTAL_SHIFT) /* 4.9152 MHz (NO PLL) */ -# define SYSCON_RCC_XTAL5000KHZ (9 << SYSCON_RCC_XTAL_SHIFT) /* 5 MHz (USB) */ -# define SYSCON_RCC_XTAL5120KHZ (10 << SYSCON_RCC_XTAL_SHIFT) /* 5.12 MHz */ -# define SYSCON_RCC_XTAL6000KHZ (11 << SYSCON_RCC_XTAL_SHIFT) /* 6 MHz (USB) */ -# define SYSCON_RCC_XTAL6144KHZ (12 << SYSCON_RCC_XTAL_SHIFT) /* 6.144 MHz */ -# define SYSCON_RCC_XTAL7372p8KHZ (13 << SYSCON_RCC_XTAL_SHIFT) /* 7.3728 MHz */ -# define SYSCON_RCC_XTAL8000KHZ (14 << SYSCON_RCC_XTAL_SHIFT) /* 8 MHz (USB) */ -# define SYSCON_RCC_XTAL8192KHZ (15 << SYSCON_RCC_XTAL_SHIFT) /* 8.192 MHz */ -# define SYSCON_RCC_XTAL10000KHZ (16 << SYSCON_RCC_XTAL_SHIFT) /* 10.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12000KHZ (17 << SYSCON_RCC_XTAL_SHIFT) /* 12.0 MHz (USB) */ -# define SYSCON_RCC_XTAL12288KHZ (18 << SYSCON_RCC_XTAL_SHIFT) /* 12.288 MHz */ -# define SYSCON_RCC_XTAL13560KHZ (19 << SYSCON_RCC_XTAL_SHIFT) /* 13.56 MHz */ -# define SYSCON_RCC_XTAL14318p18KHZ (20 << SYSCON_RCC_XTAL_SHIFT) /* 14.31818 MHz */ -# define SYSCON_RCC_XTAL16000KHZ (21 << SYSCON_RCC_XTAL_SHIFT) /* 16.0 MHz (USB) */ -# define SYSCON_RCC_XTAL16384KHZ (22 << SYSCON_RCC_XTAL_SHIFT) /* 16.384 MHz */ -# define SYSCON_RCC_XTAL18000KHZ (23 << SYSCON_RCC_XTAL_SHIFT) /* 18.0 MHz (USB) */ -# define SYSCON_RCC_XTAL20000KHZ (24 << SYSCON_RCC_XTAL_SHIFT) /* 20.0 MHz (USB) */ -# define SYSCON_RCC_XTAL24000KHZ (25 << SYSCON_RCC_XTAL_SHIFT) /* 24.0 MHz (USB) */ -# define SYSCON_RCC_XTAL25000KHZ (26 << SYSCON_RCC_XTAL_SHIFT) /* 25.0 MHz (USB) */ -#define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ -#define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ -#define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ -#define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ -#define SYSCON_RCC_SYSDIV_MASK (0x0f << SYSCON_RCC_SYSDIV_SHIFT) -# define SYSCON_RCC_SYSDIV(n) (((n)-1) << SYSCON_RCC_SYSDIV_SHIFT) -#define SYSCON_RCC_ACG (1 << 27) /* Bit 27: Auto Clock Gating */ - -/* GPIO High-Performance Bus Control */ - -#define SYSCON_GPIOHBCTL_PORTA (1 << 0) /* Bit 0: Port A Advanced High-Performance Bus */ -#define SYSCON_GPIOHBCTL_PORTB (1 << 1) /* Bit 1: Port B Advanced High-Performance Bus */ -#define SYSCON_GPIOHBCTL_PORTC (1 << 2) /* Bit 2: Port C Advanced High-Performance Bus */ -#define SYSCON_GPIOHBCTL_PORTD (1 << 3) /* Bit 3: Port D Advanced High-Performance Bus */ -#define SYSCON_GPIOHBCTL_PORTE (1 << 4) /* Bit 4: Port E Advanced High-Performance Bus */ -#define SYSCON_GPIOHBCTL_PORTF (1 << 5) /* Bit 5: Port F Advanced High-Performance Bus */ - -/* Run-Mode Clock Configuration 2 */ - -#define SYSCON_RCC2_OSCSRC2_SHIFT 4 /* Bits 6-4: Oscillator Source */ -#define SYSCON_RCC2_OSCSRC2_MASK (7 << SYSCON_RCC2_OSCSRC2_SHIFT) -# define SYSCON_RCC2_OSCSRC2_MOSC (0 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Main oscillator */ -# define SYSCON_RCC2_OSCSRC2_PIOSC (1 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Precision internal oscillator (reset) */ -# define SYSCON_RCC2_OSCSRC2_PIOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Precision internal oscillator / 4 */ -# define SYSCON_RCC2_OSCSRC2_LFIOSC (4 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Low-frequency internal oscillator */ -# define SYSCON_RCC2_OSCSRC2_32768HZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ -#define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ -#define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ -#define SYSCON_RCC2_USBPWRDN (1 << 14) /* Bit 14: Power-Down USB PLL */ -#define SYSCON_RCC2_SYSDIV2LSB (1 << 22) /* Bit 22: Additional LSB for SYSDIV2 */ -#define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ -#define SYSCON_RCC2_SYSDIV2_MASK (0x3f << SYSCON_RCC2_SYSDIV2_SHIFT) -# define SYSCON_RCC2_SYSDIV(n) ((n-1) << SYSCON_RCC2_SYSDIV2_SHIFT) -# define SYSCON_RCC2_SYSDIV_DIV400(n) (((n-1) >> 1) << SYSCON_RCC2_SYSDIV2_SHIFT) -#define SYSCON_RCC2_DIV400 (1 << 30) /* Bit 30: Divide PLL as 400 MHz vs. 200 MHz */ -#define SYSCON_RCC2_USERCC2 (1 << 31) /* Bit 31: Use RCC2 When set */ - -/* Main Oscillator Control */ - -#define SYSCON_MOSCCTL_CVAL (1 << 0) /* Bit 0: Clock Validation for MOSC */ -#define SYSCON_MOSCCTL_MOSCIM (1 << 1) /* Bit 1: MOSC Failure Action */ -#define SYSCON_MOSCCTL_NOXTAL (1 << 2) /* Bit 2: No Crystal Connected */ - -/* Deep Sleep Clock Configuration */ - -#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ -#define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (7 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) -# define SYSCON_DSLPCLKCFG_DSOSCSRC_MOSC (0 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Main oscillator */ -# define SYSCON_DSLPCLKCFG_DSOSCSRC_PIOSC (1 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Precision internal oscillator (reset) */ -# define SYSCON_DSLPCLKCFG_DSOSCSRC_PIOSC4 (2 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Precision internal oscillator / 4 */ -# define SYSCON_DSLPCLKCFG_DSOSCSRC_LFIOSC (4 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Low-frequency internal oscillator */ -# define SYSCON_DSLPCLKCFG_DSOSCSRC_32768KHZ (7 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* 32.768KHz external oscillator */ -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ -#define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) -# define SYSCON_DSLPCLKCFG_DSDIVORIDE(b) (((n)-1) << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) - -/* System Properties */ - -#define SYSCON_SYSPROP_FPU (1 << 0) /* Bit 0: FPU Present */ - -/* Precision Internal Oscillator Calibration */ - -#define SYSCON_PIOSCCAL_UT_SHIFT (0) /* Bits 0-6: User Trim Value */ -#define SYSCON_PIOSCCAL_UT_MASK (0x7f << SYSCON_PIOSCCAL_UT_SHIFT) -#define SYSCON_PIOSCCAL_UPDATE (1 << 8) /* Bit 8: Update Trim */ -#define SYSCON_PIOSCCAL_CAL (1 << 9) /* Bit 9: Start Calibration */ -#define SYSCON_PIOSCCAL_UTEN (1 << 31) /* Bit 31: Use User Trim Value */ - -/* Precision Internal Oscillator Statistics */ - -#define SYSCON_PIOSCSTAT_CT_SHIFT (0) /* Bits 0-6: Calibration Trim Value */ -#define SYSCON_PIOSCSTAT_CT_MASK (0x7f << SYSCON_PIOSCSTAT_CT_SHIFT) -#define SYSCON_PIOSCSTAT_RESULT_SHIFT (8) /* Bits 8-9: Calibration Result */ -#define SYSCON_PIOSCSTAT_RESULT_MASK (3 << SYSCON_PIOSCSTAT_RESULT_SHIFT) -#define SYSCON_PIOSCSTAT_DT_SHIFT (16) /* Bits 16-22: Default Trim Value */ -#define SYSCON_PIOSCSTAT_DT_MASK (0x7f << SYSCON_PIOSCSTAT_DT_SHIFT) - -/* PLL0 Frequency */ - -#define SYSCON_PLLFREQ0_MINT_SHIFT (0) /* Bits 0-9: PLL M Integer Value */ -#define SYSCON_PLLFREQ0_MINT_MASK (0x3ff << SYSCON_PLLFREQ0_MINT_SHIFT) -#define SYSCON_PLLFREQ0_MFRAC_SHIFT (10) /* Bits 10-19: PLL M Fractional Value */ -#define SYSCON_PLLFREQ0_MFRAC_MASK (0x3ff << SYSCON_PLLFREQ0_MFRAC_SHIFT) - -/* PLL1 Frequency */ - -#define SYSCON_PLLFREQ1_N_SHIFT (0) /* Bits 0-4: PLL N Value */ -#define SYSCON_PLLFREQ1_N_MASK (31 << SYSCON_PLLFREQ1_N_SHIFT) -#define SYSCON_PLLFREQ1_Q_SHIFT (8) /* Bits 8-12: PLL Q Value */ -#define SYSCON_PLLFREQ1_Q_MASK (31 << SYSCON_PLLFREQ1_Q_SHIFT) - -/* PLL Status */ - -#define SYSCON_PLLSTAT_LOCK (1 << 0) /* Bit 0: PLL Lock */ - -/* Watchdog Timer Peripheral Present */ - -#define SYSCON_PPWD(n) (1 << (n)) /* Bit n: WDTn present */ -# define SYSCON_PPWD_P0 (1 << 0) /* Bit 0: WDT0 present */ -# define SYSCON_PPWD_P1 (1 << 1) /* Bit 1: WDT1 present */ - -/* 16/32-Bit Timer Peripheral Present */ - -#define SYSCON_PPTIMER(n) (1 << (n)) /* Bit n: 16/32-Bit General-Purpose Timer n Present */ -# define SYSCON_PPTIMER_P0 (1 << 0) /* Bit 0: 16/32-Bit General-Purpose Timer 0 Present */ -# define SYSCON_PPTIMER_P1 (1 << 1) /* Bit 1: 16/32-Bit General-Purpose Timer 0 Present */ -# define SYSCON_PPTIMER_P2 (1 << 2) /* Bit 2: 16/32-Bit General-Purpose Timer 0 Present */ -# define SYSCON_PPTIMER_P3 (1 << 3) /* Bit 3: 16/32-Bit General-Purpose Timer 0 Present */ -# define SYSCON_PPTIMER_P4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 0 Present */ -# define SYSCON_PPTIMER_P5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 0 Present */ - -/* GPIO Peripheral Present */ - -#define SYSCON_PPGPIO(n) (1 << (n)) /* Bit n: GPIO Port n Present */ -# define SYSCON_PPGPIO_P0 (1 << 0) /* Bit 0: GPIO Port A Present */ -# define SYSCON_PPGPIO_P1 (1 << 1) /* Bit 1: GPIO Port B Present */ -# define SYSCON_PPGPIO_P2 (1 << 2) /* Bit 2: GPIO Port C Present */ -# define SYSCON_PPGPIO_P3 (1 << 3) /* Bit 3: GPIO Port D Present */ -# define SYSCON_PPGPIO_P4 (1 << 4) /* Bit 4: GPIO Port E Present */ -# define SYSCON_PPGPIO_P5 (1 << 5) /* Bit 5: GPIO Port F Present */ -# define SYSCON_PPGPIO_P6 (1 << 6) /* Bit 6: GPIO Port G Present */ -# define SYSCON_PPGPIO_P7 (1 << 7) /* Bit 7: GPIO Port H Present */ -# define SYSCON_PPGPIO_P8 (1 << 8) /* Bit 8: GPIO Port J Present */ -# define SYSCON_PPGPIO_P9 (1 << 9) /* Bit 9: GPIO Port K Present */ -# define SYSCON_PPGPIO_P10 (1 << 10) /* Bit 10: GPIO Port L Present */ -# define SYSCON_PPGPIO_P11 (1 << 11) /* Bit 11: GPIO Port M Present */ -# define SYSCON_PPGPIO_P12 (1 << 12) /* Bit 12: GPIO Port N Present */ -# define SYSCON_PPGPIO_P13 (1 << 13) /* Bit 13: GPIO Port P Present */ -# define SYSCON_PPGPIO_P14 (1 << 14) /* Bit 14: GPIO Port Q Present */ - -/* uDMA Peripheral Present */ - -#define SYSCON_PPDMA_P0 (1 << 0) /* Bit 0: μDMA Module Present */ - -/* Hibernation Peripheral Present */ - -#define SYSCON_PPHIB_P0 (1 << 0) /* Bit 0: Hibernation Module Present */ - -/* UART Present */ - -#define SYSCON_PPUART(n) (1 << (n)) /* Bit n: UART Module n Present */ -# define SYSCON_PPUART_P0 (1 << 0) /* Bit 0: UART Module 0 Present */ -# define SYSCON_PPUART_P1 (1 << 1) /* Bit 1: UART Module 1 Present */ -# define SYSCON_PPUART_P2 (1 << 2) /* Bit 2: UART Module 2 Present */ -# define SYSCON_PPUART_P3 (1 << 3) /* Bit 3: UART Module 3 Present */ -# define SYSCON_PPUART_P4 (1 << 4) /* Bit 4: UART Module 4 Present */ -# define SYSCON_PPUART_P5 (1 << 5) /* Bit 5: UART Module 5 Present */ -# define SYSCON_PPUART_P6 (1 << 6) /* Bit 6: UART Module 6 Present */ -# define SYSCON_PPUART_P7 (1 << 7) /* Bit 7: UART Module 7 Present */ - -/* SSI Peripheral Present */ - -#define SYSCON_PPSSI(n) (1 << (n)) /* Bit n: SSI Module n Present */ -# define SYSCON_PPSSI_P0 (1 << 0) /* Bit 0: SSI Module 0 Present */ -# define SYSCON_PPSSI_P1 (1 << 1) /* Bit 1: SSI Module 1 Present */ -# define SYSCON_PPSSI_P2 (1 << 2) /* Bit 2: SSI Module 2 Present */ -# define SYSCON_PPSSI_P3 (1 << 3) /* Bit 3: SSI Module 3 Present */ - -/* I2C Peripheral Present */ - -#define SYSCON_PPI2C(n) (1 << (n)) /* Bit n: I2C Module n Present */ -# define SYSCON_PPI2C_P0 (1 << 0) /* Bit 0: I2C Module 0 Present */ -# define SYSCON_PPI2C_P1 (1 << 1) /* Bit 1: I2C Module 1 Present */ -# define SYSCON_PPI2C_P2 (1 << 2) /* Bit 2: I2C Module 2 Present */ -# define SYSCON_PPI2C_P3 (1 << 3) /* Bit 3: I2C Module 3 Present */ -# define SYSCON_PPI2C_P4 (1 << 4) /* Bit 4: I2C Module 4 Present */ -# define SYSCON_PPI2C_P5 (1 << 5) /* Bit 5: I2C Module 5 Present */ - -/* USB Peripheral Present */ - -#define SYSCON_PPUSB_P0 (1 << 0) /* USB Module Present */ - -/* CAN Peripheral Present */ - -#define SYSCON_PPCAN(n) (1 << (n)) /* Bit n: CAN Module n Present */ -# define SYSCON_PPCAN_P0 (1 << 0) /* Bit 0: CAN Module 0 Present */ -# define SYSCON_PPCAN_P1 (1 << 1) /* Bit 1: CAN Module 1 Present */ - -/* ADC Peripheral Present */ - -#define SYSCON_PPADC(n) (1 << (n)) /* Bit n: ADC Module n Present */ -# define SYSCON_PPADC_P0 (1 << 0) /* Bit 0: ADC Module 0 Present */ -# define SYSCON_PPADC_P1 (1 << 1) /* Bit 1: ADC Module 1 Present */ - -/* Analog Comparator Peripheral Present */ - -#define SYSCON_PPACMP_P0 (1 << 0) /* Bit 0: Analog Comparator Module Present */ - -/* Pulse Width Modulator Peripheral Present */ - -#define SYSCON_PPWM(n) (1 << (n)) /* Bit n: PWM Module n Present */ -# define SYSCON_PPWM_P0 (1 << 0) /* Bit 0: PWM Module 0 Present */ -# define SYSCON_PPWM_P1 (1 << 1) /* Bit 1: PWM Module 1 Present */ - -/* Quadrature Encoder Peripheral Present */ - -#define SYSCON_PPQEI(n) (1 << (n)) /* Bit n: QEI Module n Present */ -# define SYSCON_PPQEI_P0 (1 << 0) /* Bit 0: QEI Module 0 Present */ -# define SYSCON_PPUART_P1 (1 << 1) /* Bit 1: QEI Module 1 Present */ - -/* EEPROM Peripheral Present */ - -#define SYSCON_PPEEPROM_P0 (1 << 0) /* Bit 0: EEPROM Module Present */ - -/* 32/64-Bit Wide Timer Peripheral Present */ - -#define SYSCON_PPWTIMER(n) (1 << (n)) /* Bit n: 32/64-Bit Wide General-Purpose Timer n Present */ -# define SYSCON_PPWTIMER_P0 (1 << 0) /* Bit 0: 32/64-Bit Wide General-Purpose Timer 0 Present */ -# define SYSCON_PPWTIMER_P1 (1 << 1) /* Bit 1: 32/64-Bit Wide General-Purpose Timer 1 Present */ -# define SYSCON_PPWTIMER_P2 (1 << 2) /* Bit 2: 32/64-Bit Wide General-Purpose Timer 2 Present */ -# define SYSCON_PPWTIMER_P3 (1 << 3) /* Bit 3: 32/64-Bit Wide General-Purpose Timer 3 Present */ -# define SYSCON_PPWTIMER_P4 (1 << 4) /* Bit 4: 32/64-Bit Wide General-Purpose Timer 4 Present */ -# define SYSCON_PPWTIMER_P5 (1 << 5) /* Bit 5: 32/64-Bit Wide General-Purpose Timer 5 Present */ - -/* Watchdog Timer Software Reset */ - -#define SYSCON_SPWD(n) (1 << (n)) /* Bit n: Watchdog Timer n Software Reset */ -# define SYSCON_SPWD_R0 (1 << 0) /* Bit 0: Watchdog Timer 0 Software Reset */ -# define SYSCON_SPWD_R1 (1 << 1) /* Bit 1: Watchdog Timer 1 Software Reset */ - -/* 16/32-Bit Timer Software Reset */ - -#define SYSCON_SRTIMER(n) (1 << (n)) /* Bit n: 16/32-Bit General-Purpose Timer n Software Reset */ -# define SYSCON_SRTIMER_R0 (1 << 0) /* Bit 0: 16/32-Bit General-Purpose Timer 0 Software Reset */ -# define SYSCON_SRTIMER_R1 (1 << 1) /* Bit 1: 16/32-Bit General-Purpose Timer 1 Software Reset */ -# define SYSCON_SRTIMER_R2 (1 << 2) /* Bit 2: 16/32-Bit General-Purpose Timer 2 Software Reset */ -# define SYSCON_SRTIMER_R3 (1 << 3) /* Bit 3: 16/32-Bit General-Purpose Timer 3 Software Reset */ -# define SYSCON_SRTIMER_R4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 4 Software Reset */ -# define SYSCON_SRTIMER_R5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 5 Software Reset */ - -/* GPIO Software Reset */ - -#define SYSCON_SRGPIO(n) (1 << (n)) /* Bit n: GPIO Port n Software Reset */ -# define SYSCON_SRGPIO_R0 (1 << 0) /* Bit 0: GPIO Port A Software Reset */ -# define SYSCON_SRGPIO_R1 (1 << 1) /* Bit 1: GPIO Port B Software Reset */ -# define SYSCON_SRGPIO_R2 (1 << 2) /* Bit 2: GPIO Port C Software Reset */ -# define SYSCON_SRGPIO_R3 (1 << 3) /* Bit 3: GPIO Port D Software Reset */ -# define SYSCON_SRGPIO_R4 (1 << 4) /* Bit 4: GPIO Port E Software Reset */ -# define SYSCON_SRPGIO_R5 (1 << 5) /* Bit 5: GPIO Port F Software Reset */ - -/* uDMA Software Reset */ - -#define SYSCON_SRDMA_R0 (1 << 0) /* Bit 0: μDMA Module Software Reset */ - -/* Hibernation Software Reset */ - -#define SYSCON_SRHIB_R0 (1 << 0) /* Bit 0: Hibernation Module Software Reset */ - -/* UART Software Reset*/ - -#define SYSCON_SRUARTR(n) (1 << (n)) /* Bit n: UART Module n Software Reset */ -# define SYSCON_SRUARTR_R0 (1 << 0) /* Bit 0: UART Module 0 Software Reset */ -# define SYSCON_SRUARTR_R1 (1 << 1) /* Bit 1: UART Module 1 Software Reset */ -# define SYSCON_SRUARTR_R2 (1 << 2) /* Bit 2: UART Module 2 Software Reset */ -# define SYSCON_SRUARTR_R3 (1 << 3) /* Bit 3: UART Module 3 Software Reset */ -# define SYSCON_SRUARTR_R4 (1 << 4) /* Bit 4: UART Module 4 Software Reset */ -# define SYSCON_SRUARTR_R5 (1 << 5) /* Bit 5: UART Module 5 Software Reset */ -# define SYSCON_SRUARTR_R6 (1 << 6) /* Bit 6: UART Module 6 Software Reset */ -# define SYSCON_SRUARTR_R7 (1 << 7) /* Bit 7: UART Module 7 Software Reset */ - -/* SSI Software Reset */ - -#define SYSCON_SRSSI(n) (1 << (n)) /* Bit n: SSI Module n Software Reset */ -# define SYSCON_SRSSI_R0 (1 << 0) /* Bit 0: SSI Module 0 Software Reset */ -# define SYSCON_SRSSI_R1 (1 << 1) /* Bit 1: SSI Module 1 Software Reset */ -# define SYSCON_SRSSI_R2 (1 << 2) /* Bit 2: SSI Module 2 Software Reset */ -# define SYSCON_SRSSI_R3 (1 << 3) /* Bit 3: SSI Module 3 Software Reset */ - -/* I2C Software Reset */ - -#define SYSCON_SRI2C(n) (1 << (n)) /* Bit n: I2C Module n Software Reset */ -# define SYSCON_SRI2C_R0 (1 << 0) /* Bit 0: I2C Module 0 Software Reset */ -# define SYSCON_SRI2C_R1 (1 << 1) /* Bit 1: I2C Module 1 Software Reset */ -# define SYSCON_SRI2C_R2 (1 << 2) /* Bit 2: I2C Module 2 Software Reset */ -# define SYSCON_SRI2C_R3 (1 << 3) /* Bit 3: I2C Module 3 Software Reset */ - -/* USB Software Reset */ - -#define SYSCON_SRUSB_R0 (1 << 0) /* Bit 0: USB Module Software Reset */ - -/* CAN Software Reset */ - -#define SYSCON_SRCAN_R0 (1 << 0) /* Bit 0: CAN Module 0 Software Reset */ - -/* ADC Software Reset */ - -#define SYSCON_SRADC(n) (1 << (n)) /* Bit n: ADC Module n Software Reset */ -# define SYSCON_SRADC_R0 (1 << 0) /* Bit 0: ADC Module 0 Software Reset */ -# define SYSCON_SRADC_R1 (1 << 1) /* Bit 1: ADC Module 1 Software Reset */ - -/* Analog Comparator Software Reset */ - -#define SYSCON_SRACMP_R0 (1 << 0) /* Bit 0: Analog Comparator Module 0 Software Reset */ - -/* EEPROM Software Reset */ - -#define SYSCON_SREEPROM_R0 (1 << 0) /* Bit 0: EEPROM Module Software Reset */ - -/* 32/64-Bit Wide Timer Software Reset */ - -#define SYSCON_SRWTIMER(n) (1 << (n)) /* Bit n: 32/64-Bit Wide General-Purpose Timer n Software Reset */ -# define SYSCON_SRWTIMER_R0 (1 << 0) /* Bit 0: 32/64-Bit Wide General-Purpose Timer 0 Software Reset */ -# define SYSCON_SRWTIMER_R1 (1 << 1) /* Bit 1: 32/64-Bit Wide General-Purpose Timer 1 Software Reset */ -# define SYSCON_SRWTIMER_R2 (1 << 2) /* Bit 2: 32/64-Bit Wide General-Purpose Timer 2 Software Reset */ -# define SYSCON_SRWTIMER_R3 (1 << 3) /* Bit 3: 32/64-Bit Wide General-Purpose Timer 3 Software Reset */ -# define SYSCON_SRWTIMER_R4 (1 << 4) /* Bit 4: 32/64-Bit Wide General-Purpose Timer 4 Software Reset */ -# define SYSCON_SRWTIMER_R5 (1 << 5) /* Bit 5: 32/64-Bit Wide General-Purpose Timer 5 Software Reset */ -# define SYSCON_SRWTIMER_R6 (1 << 6) /* Bit 6: 32/64-Bit Wide General-Purpose Timer 6 Software Reset */ - -/* Watchdog Timer Run Mode Clock Gating Control */ - -#define SYSCON_RCGCWD(n) (1 << (n)) /* Bit n: Watchdog Timer n Run Mode Clock Gating Control */ -# define SYSCON_RCGCWD_R0 (1 << 0) /* Bit 0: Watchdog Timer 0 Run Mode Clock Gating Control */ -# define SYSCON_RCGCWD_R1 (1 << 1) /* Bit 1: Watchdog Timer 1 Run Mode Clock Gating Control */ - -/* 16/32-Bit Timer Run Mode Clock Gating Control */ - -#define SYSCON_RCGCTIMER(n) (1 << (n)) /* Bit n: 16/32-Bit General-Purpose Timer n Run Mode Clock Gating Control */ -# define SYSCON_RCGCTIMER_R0 (1 << 0) /* Bit 0: 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control */ -# define SYSCON_RCGCTIMER_R1 (1 << 1) /* Bit 1: 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control */ -# define SYSCON_RCGCTIMER_R2 (1 << 2) /* Bit 2: 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control */ -# define SYSCON_RCGCTIMER_R3 (1 << 3) /* Bit 3: 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control */ -# define SYSCON_RCGCTIMER_R4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control */ -# define SYSCON_RCGCTIMER_R5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control */ - -/* GPIO Run Mode Clock Gating Control*/ - -#define SYSCON_RCGCGPIO(n) (1 << (n)) /* Bit n: 16/32-Bit GPIO Port n Run Mode Clock Gating Control */ -# define SYSCON_RCGCGPIO_R0 (1 << 0) /* Bit 0: 16/32-Bit GPIO Port A Run Mode Clock Gating Control */ -# define SYSCON_RCGCGPIO_R1 (1 << 1) /* Bit 1: 16/32-Bit GPIO Port B Run Mode Clock Gating Control */ -# define SYSCON_RCGCGPIO_R2 (1 << 2) /* Bit 2: 16/32-Bit GPIO Port C Run Mode Clock Gating Control */ -# define SYSCON_RCGCGPIO_R3 (1 << 3) /* Bit 3: 16/32-Bit GPIO Port D Run Mode Clock Gating Control */ -# define SYSCON_RCGCGPIO_R4 (1 << 4) /* Bit 4: 16/32-Bit GPIO Port E Run Mode Clock Gating Control */ -# define SYSCON_RCGCGPIO_R5 (1 << 5) /* Bit 5: 16/32-Bit GPIO Port F Run Mode Clock Gating Control */ - -/* uDMA Run Mode Clock Gating Control*/ - -#define SYSCON_RCGCDMA_R0 (1 << 0) /* Bit 0: μDMA Module Run Mode Clock Gating Control */ - -/* Hibernation Run Mode Clock Gating Control */ - -#define SYSCON_RCGCHIB_R0 (1 << 0) /* Bit 0: Hibernation Module Run Mode Clock Gating Control */ - -/* UART Run Mode Clock Gating Control*/ - -#define SYSCON_RCGCUART(n) (1 << (n)) /* Bit n: UART Module n Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R0 (1 << 0) /* Bit 0: UART Module 0 Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R1 (1 << 1) /* Bit 1: UART Module 1 Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R2 (1 << 2) /* Bit 2: UART Module 2 Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R3 (1 << 3) /* Bit 3: UART Module 3 Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R4 (1 << 4) /* Bit 4: UART Module 4 Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R5 (1 << 5) /* Bit 5: UART Module 5 Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R6 (1 << 6) /* Bit 6: UART Module 6 Run Mode Clock Gating Control */ -# define SYSCON_RCGCUART_R7 (1 << 7) /* Bit 7: UART Module 7 Run Mode Clock Gating Control */ - -/* SSI Run Mode Clock Gating Control*/ - -#define SYSCON_RCGCSSI(n) (1 << (n)) /* Bit n: SSI Module n Run Mode Clock Gating Control */ -# define SYSCON_RCGCSSI_R0 (1 << 0) /* Bit 0: SSI Module 0 Run Mode Clock Gating Control */ -# define SYSCON_RCGCSSI_R1 (1 << 1) /* Bit 1: SSI Module 1 Run Mode Clock Gating Control */ -# define SYSCON_RCGCSSI_R2 (1 << 2) /* Bit 2: SSI Module 2 Run Mode Clock Gating Control */ -# define SYSCON_RCGCSSI_R3 (1 << 3) /* Bit 3: SSI Module 3 Run Mode Clock Gating Control */ - -/* I2C Run Mode Clock Gating Control */ - -#define SYSCON_RCGCI2C(n) (1 << (n)) /* Bit n: I2C Module n Run Mode Clock Gating Control */ -# define SYSCON_RCGCI2C_R0 (1 << 0) /* Bit 0: I2C Module 0 Run Mode Clock Gating Control */ -# define SYSCON_RCGCI2C_R1 (1 << 1) /* Bit 1: I2C Module 1 Run Mode Clock Gating Control */ -# define SYSCON_RCGCI2C_R2 (1 << 2) /* Bit 2: I2C Module 2 Run Mode Clock Gating Control */ -# define SYSCON_RCGCI2C_R3 (1 << 3) /* Bit 3: I2C Module 3 Run Mode Clock Gating Control */ - -/* USB Run Mode Clock Gating Control */ - -#define SYSCON_RCGCUSB_R0 (1 << 0) /* Bit 0: USB Module Run Mode Clock Gating Control */ - -/* CAN Run Mode Clock Gating Control */ - -#define SYSCON_RCGCCAN_R0 (1 << 0) /* Bit 0: CAN Module 0 Run Mode Clock Gating Control */ - -/* ADC Run Mode Clock Gating Control */ - -#define SYSCON_RCGCADC(n) (1 << (n)) /* Bit n: ADC Module n Run Mode Clock Gating Control */ -# define SYSCON_RCGCADC_R0 (1 << 0) /* Bit 0: ADC Module 0 Run Mode Clock Gating Control */ -# define SYSCON_RCGCADC_R1 (1 << 1) /* Bit 1: ADC Module 1 Run Mode Clock Gating Control */ - -/* Analog Comparator Run Mode Clock Gating Control */ - -#define SYSCON_RCGCACMP_R0 (1 << 0) /* Bit 0: Analog Comparator Module 0 Run Mode Clock Gating Control */ - -/* EEPROM Run Mode Clock Gating Control */ - -#define SYSCON_RCGCEEPROM_R0 (1 << 0) /* Bit 0: EEPROM Module Run Mode Clock Gating Control */ - -/* 32/64-BitWide Timer Run Mode Clock Gating Control */ - -#define SYSCON_RCGCWTIMER(n) (1 << (n)) /* Bit n: 32/64-Bit Wide General-Purpose Timer n Run Mode Clock Gating Control */ -# define SYSCON_RCGCWTIMER_R0 (1 << 0) /* Bit 0: 32/64-Bit Wide General-Purpose Timer 0 Run Mode Clock Gating Control */ -# define SYSCON_RCGCWTIMER_R1 (1 << 1) /* Bit 1: 32/64-Bit Wide General-Purpose Timer 1 Run Mode Clock Gating Control */ -# define SYSCON_RCGCWTIMER_R2 (1 << 2) /* Bit 2: 32/64-Bit Wide General-Purpose Timer 2 Run Mode Clock Gating Control */ -# define SYSCON_RCGCWTIMER_R3 (1 << 3) /* Bit 3: 32/64-Bit Wide General-Purpose Timer 3 Run Mode Clock Gating Control */ -# define SYSCON_RCGCWTIMER_R4 (1 << 4) /* Bit 4: 32/64-Bit Wide General-Purpose Timer 4 Run Mode Clock Gating Control */ -# define SYSCON_RCGCWTIMER_R5 (1 << 5) /* Bit 5: 32/64-Bit Wide General-Purpose Timer 5 Run Mode Clock Gating Control */ - -/* Watchdog Timer Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCWD(n) (1 << (n)) /* Bit n: Watchdog Timer n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S0 (1 << 0) /* Bit 0: Watchdog Timer 0 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S1 (1 << 1) /* Bit 1: Watchdog Timer 1 Sleep Mode Clock Gating Control */ - -/* 16/32-Bit Timer Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCWD(n) (1 << (n)) /* Bit n: 16/32-Bit General-Purpose Timer n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S0 (1 << 0) /* Bit 0: 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S1 (1 << 1) /* Bit 1: 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S2 (1 << 2) /* Bit 2: 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S3 (1 << 3) /* Bit 3: 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWD_S5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control */ - -/* GPIO Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCGPIO(n) (1 << (n)) /* Bit n: GPIO Port n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCGPIO_S0 (1 << 0) /* Bit 0: GPIO Port A Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCGPIO_S1 (1 << 1) /* Bit 1: GPIO Port B Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCGPIO_S2 (1 << 2) /* Bit 2: GPIO Port C Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCGPIO_S3 (1 << 3) /* Bit 3: GPIO Port D Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCGPIO_S4 (1 << 4) /* Bit 4: GPIO Port E Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCGPIO_S5 (1 << 5) /* Bit 5: GPIO Port F Sleep Mode Clock Gating Control */ - -/* uDMA Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCDMA_S0 (1 << 0) /* Bit 0: μDMA Module Sleep Mode Clock Gating Control */ - -/* Hibernation Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCHIB_S0 (1 << 0) /* Bit 0: Hibernation Module Sleep Mode Clock Gating Control */ - -/* UART Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCUART(n) (1 << (n)) /* Bit n: UART Module n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S0 (1 << 0) /* Bit 0: UART Module 0 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S1 (1 << 1) /* Bit 1: UART Module 1 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S2 (1 << 2) /* Bit 2: UART Module 2 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S3 (1 << 3) /* Bit 3: UART Module 3 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S4 (1 << 4) /* Bit 4: UART Module 4 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S5 (1 << 5) /* Bit 5: UART Module 5 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S6 (1 << 6) /* Bit 6: UART Module 6 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCUART_S7 (1 << 7) /* Bit 7: UART Module 7 Sleep Mode Clock Gating Control */ - -/* SSI Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCSSI(n) (1 << (n)) /* Bit n: SSI Module n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCSSI_S0 (1 << 0) /* Bit 0: SSI Module 0 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCSSI_S1 (1 << 1) /* Bit 1: SSI Module 1 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCSSI_S2 (1 << 2) /* Bit 2: SSI Module 2 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCSSI_S3 (1 << 3) /* Bit 3: SSI Module 3 Sleep Mode Clock Gating Control */ - -/* I2C Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCI2C(n) (1 << (n)) /* Bit n: I2C Module n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCI2C_S0 (1 << 0) /* Bit 0: I2C Module 0 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCI2C_S1 (1 << 1) /* Bit 1: I2C Module 1 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCI2C_S2 (1 << 2) /* Bit 2: I2C Module 2 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCI2C_S3 (1 << 3) /* Bit 3: I2C Module 3 Sleep Mode Clock Gating Control */ - -/* USB Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCUSB_S0 (1 << 0) /* Bit 0: USB Module Sleep Mode Clock Gating Control */ - -/* CAN Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCCAN_S0 (1 << 0) /* Bit 0: CAN Module 0 Sleep Mode Clock Gating Control */ - -/* ADC Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCADC(n) (1 << (n)) /* Bit n: ADC Module n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCADC_S0 (1 << 0) /* Bit 0: ADC Module 0 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCADC_S1 (1 << 1) /* Bit 1: ADC Module 1 Sleep Mode Clock Gating Control */ - -/* Analog Comparator Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCACMP_S0 (1 << 0) /* Bit 0: Analog Comparator Module 0 Sleep Mode Clock Gating Control */ - -/* EEPROM Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCEEPROM_S0 (1 << 0) /* Bit 0: EEPROM Module Sleep Mode Clock Gating Control */ - -/* 32/64-BitWide Timer Sleep Mode Clock Gating Control */ - -#define SYSCON_SCGCWTIMER(n) (1 << (n)) /* Bit n: 32/64-Bit Wide General-Purpose Timer n Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWTIMER_S0 (1 << 0) /* Bit 0: 32/64-Bit Wide General-Purpose Timer 0 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWTIMER_S1 (1 << 1) /* Bit 1: 32/64-Bit Wide General-Purpose Timer 1 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWTIMER_S2 (1 << 2) /* Bit 2: 32/64-Bit Wide General-Purpose Timer 2 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWTIMER_S3 (1 << 3) /* Bit 3: 32/64-Bit Wide General-Purpose Timer 3 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWTIMER_S4 (1 << 4) /* Bit 4: 32/64-Bit Wide General-Purpose Timer 4 Sleep Mode Clock Gating Control */ -# define SYSCON_SCGCWTIMER_S5 (1 << 5) /* Bit 5: 32/64-Bit Wide General-Purpose Timer 5 Sleep Mode Clock Gating Control */ - -/* Watchdog Timer Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCWD(n) (1 << (n)) /* Bit n: Watchdog Timer n Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWD_D0 (1 << 0) /* Bit 0: Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWD_D1 (1 << 1) /* Bit 1: Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control */ - -/* Clock Gating Control */ - -#define SYSCON_DCGCTIMER(n) (1 << (n)) /* Bit n: 16/32-Bit General-Purpose Timer n Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCTIMER_D0 (1 << 0) /* Bit 0: 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCTIMER_D1 (1 << 1) /* Bit 1: 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCTIMER_D2 (1 << 2) /* Bit 2: 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCTIMER_D3 (1 << 3) /* Bit 3: 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCTIMER_D4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCTIMER_D5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control */ - -/* GPIO Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCGPIO(n) (1 << (n)) /* Bit n: GPIO Port F Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCGPIO_D0 (1 << 0) /* Bit 0: GPIO Port A Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCGPIO_D1 (1 << 1) /* Bit 1: GPIO Port B Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCGPIO_D2 (1 << 2) /* Bit 2: GPIO Port C Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCGPIO_D3 (1 << 3) /* Bit 3: GPIO Port D Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCGPIO_D4 (1 << 4) /* Bit 4: GPIO Port E Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCGPIO_D5 (1 << 5) /* Bit 5: GPIO Port F Deep-Sleep Mode Clock Gating Control */ - -/* uDMA Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCDMA_D0 (1 << 0) /* Bit 0: μDMA Module Deep-Sleep Mode Clock Gating Control */ - -/* Hibernation Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCHIB_D0 (1 << 0) /* Bit 0: Hibernation Module Deep-Sleep Mode Clock Gating Control */ - -/* UART Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCUART(n) (1 << (n)) /* Bit n: UART Module n Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D0 (1 << 0) /* Bit 0: UART Module 0 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D1 (1 << 1) /* Bit 1: UART Module 1 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D2 (1 << 2) /* Bit 2: UART Module 2 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D3 (1 << 3) /* Bit 3: UART Module 3 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D4 (1 << 4) /* Bit 4: UART Module 4 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D5 (1 << 5) /* Bit 5: UART Module 5 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D6 (1 << 6) /* Bit 6: UART Module 6 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCUART_D7 (1 << 7) /* Bit 7: UART Module 7 Deep-Sleep Mode Clock Gating Control */ - -/* SSI Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCSSI(n) (1 << (n)) /* Bit n: SSI Module n Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCSSI_D0 (1 << 0) /* Bit 0: SSI Module 0 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCSSI_D1 (1 << 1) /* Bit 1: SSI Module 1 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCSSI_D2 (1 << 2) /* Bit 2: SSI Module 2 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCSSI_D3 (1 << 3) /* Bit 3: SSI Module 3 Deep-Sleep Mode Clock Gating Control */ - -/* I2C Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCI2C(n) (1 << (n)) /* Bit n: I2C Module n Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCI2C_D0 (1 << 0) /* Bit 0: I2C Module 0 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCI2C_D1 (1 << 1) /* Bit 1: I2C Module 1 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCI2C_D2 (1 << 2) /* Bit 2: I2C Module 2 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCI2C_D3 (1 << 3) /* Bit 3: I2C Module 3 Deep-Sleep Mode Clock Gating Control */ - -/* USB Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCUSB_D0 (1 << 0) /* Bit 0: USB Module Deep-Sleep Mode Clock Gating Control */ - -/* CAN Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCCAN_D0 (1 << 0) /* Bit 0: CAN Module 0 Deep-Sleep Mode Clock Gating Control */ - -/* ADC Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCADC(n) (1 << (n)) /* Bit n: ADC Module n Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCADC_D0 (1 << 0) /* Bit 0: ADC Module 0 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCADC_D1 (1 << 1) /* Bit 1: ADC Module 1 Deep-Sleep Mode Clock Gating Control */ - -/* Analog Comparator Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCACMP_D0 (1 << 0) /* Bit 0: Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control */ - -/* EEPROM Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCEEPROM_D0 (1 << 0) /* Bit 0: EEPROM Module Deep-Sleep Mode Clock Gating Control */ - - -/* 32/64-BitWide Timer Deep-Sleep Mode Clock Gating Control */ - -#define SYSCON_DCGCWTIMER(n) (1 << (n)) /* Bit n: UART Module n Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWTIMER_D0 (1 << 0) /* Bit 0: UART Module 0 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWTIMER_D1 (1 << 1) /* Bit 1: UART Module 1 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWTIMER_D2 (1 << 2) /* Bit 2: UART Module 2 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWTIMER_D3 (1 << 3) /* Bit 3: UART Module 3 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWTIMER_D4 (1 << 4) /* Bit 4: UART Module 4 Deep-Sleep Mode Clock Gating Control */ -# define SYSCON_DCGCWTIMER_D5 (1 << 5) /* Bit 5: UART Module 5 Deep-Sleep Mode Clock Gating Control */ - -/* Watchdog Timer Peripheral Ready */ - -#define SYSCON_PRWD(n) (1 << (n)) /* Bit n: Watchdog Timer n Peripheral Ready */ -# define SYSCON_PRWD_R0 (1 << 0) /* Bit 0: Watchdog Timer 0 Peripheral Ready */ -# define SYSCON_PRWD_R1 (1 << 1) /* Bit 1: Watchdog Timer 1 Peripheral Ready */ - -/* 16/32-Bit Timer Peripheral Ready */ - -#define SYSCON_PRTIMER(n) (1 << (n)) /* Bit n: 16/32-Bit General-Purpose Timer n Peripheral Ready */ -# define SYSCON_PRTIMER_R0 (1 << 0) /* Bit 0: 16/32-Bit General-Purpose Timer 0 Peripheral Ready */ -# define SYSCON_PRTIMER_R1 (1 << 1) /* Bit 1: 16/32-Bit General-Purpose Timer 1 Peripheral Ready */ -# define SYSCON_PRTIMER_R2 (1 << 2) /* Bit 2: 16/32-Bit General-Purpose Timer 2 Peripheral Ready */ -# define SYSCON_PRTIMER_R3 (1 << 3) /* Bit 3: 16/32-Bit General-Purpose Timer 3 Peripheral Ready */ -# define SYSCON_PRTIMER_R4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 4 Peripheral Ready */ -# define SYSCON_PRTIMER_R5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 5 Peripheral Ready */ - -/* GPIO Peripheral Ready */ - -#define SYSCON_PRGPIO(n) (1 << (n)) /* Bit n: GPIO Port F Peripheral Ready */ -# define SYSCON_PRGPIO_R0 (1 << 0) /* Bit 0: GPIO Port A Peripheral Ready */ -# define SYSCON_PRGPIO_R1 (1 << 1) /* Bit 1: GPIO Port B Peripheral Ready */ -# define SYSCON_PRGPIO_R2 (1 << 2) /* Bit 2: GPIO Port C Peripheral Ready */ -# define SYSCON_PRGPIO_R3 (1 << 3) /* Bit 3: GPIO Port D Peripheral Ready */ -# define SYSCON_PRGPIO_R4 (1 << 4) /* Bit 4: GPIO Port E Peripheral Ready */ -# define SYSCON_PRGPIO_R5 (1 << 5) /* Bit 5: GPIO Port F Peripheral Ready */ - -/* uDMA Peripheral Ready */ - -#define SYSCON_PRDMA_R0 (1 << 0) /* Bit 0: μDMA Module Peripheral Ready */ - -/* Hibernation Peripheral Ready */ - -#define SYSCON_PRHIB_R0 (1 << 0) /* Bit 0: Hibernation Module Peripheral Ready */ - -/* UART Peripheral Ready */ - -#define SYSCON_PRUART(n) (1 << (n)) /* Bit n: UART Module n Peripheral Ready */ -# define SYSCON_PRUART_R0 (1 << 0) /* Bit 0: UART Module 0 Peripheral Ready */ -# define SYSCON_PRUART_R1 (1 << 1) /* Bit 1: UART Module 1 Peripheral Ready */ -# define SYSCON_PRUART_R2 (1 << 2) /* Bit 2: UART Module 2 Peripheral Ready */ -# define SYSCON_PRUART_R3 (1 << 3) /* Bit 3: UART Module 3 Peripheral Ready */ -# define SYSCON_PRUART_R4 (1 << 4) /* Bit 4: UART Module 4 Peripheral Ready */ -# define SYSCON_PRUART_R5 (1 << 5) /* Bit 5: UART Module 5 Peripheral Ready */ -# define SYSCON_PRUART_R6 (1 << 6) /* Bit 6: UART Module 6 Peripheral Ready */ -# define SYSCON_PRUART_R7 (1 << 7) /* Bit 7: UART Module 7 Peripheral Ready */ - -/* SSI Peripheral Ready */ - -#define SYSCON_PRSSI(n) (1 << (n)) /* Bit n: SSI Module n Peripheral Ready */ -# define SYSCON_PRSSI_R0 (1 << 0) /* Bit 0: SSI Module 0 Peripheral Ready */ -# define SYSCON_PRSSI_R1 (1 << 1) /* Bit 1: SSI Module 1 Peripheral Ready */ -# define SYSCON_PRSSI_R2 (1 << 2) /* Bit 2: SSI Module 2 Peripheral Ready */ -# define SYSCON_PRSSI_R3 (1 << 3) /* Bit 3: SSI Module 3 Peripheral Ready */ - -/* I2C Peripheral Ready */ - -#define SYSCON_PRI2C(n) (1 << (n)) /* Bit n: I2C Module n Peripheral Ready */ -# define SYSCON_PRI2C_R0 (1 << 0) /* Bit 0: I2C Module 0 Peripheral Ready */ -# define SYSCON_PRI2C_R1 (1 << 1) /* Bit 1: I2C Module 1 Peripheral Ready */ -# define SYSCON_PRI2C_R2 (1 << 2) /* Bit 2: I2C Module 2 Peripheral Ready */ -# define SYSCON_PRI2C_R3 (1 << 3) /* Bit 3: I2C Module 3 Peripheral Ready */ - -/* USB Peripheral Ready */ - -#define SYSCON_PRUSB_R0 (1 << 0) /* Bit 0: USB Module Peripheral Ready */ - -/* CAN Peripheral Ready */ - -#define SYSCON_PRCAN_R0 (1 << 0) /* Bit 0: CAN Module 0 Peripheral Ready */ - -/* ADC Peripheral Ready */ - -#define SYSCON_PRADC(n) (1 << (n)) /* Bit n: ADC Module n Peripheral Ready */ -# define SYSCON_PRADC_R0 (1 << 0) /* Bit 0: ADC Module 0 Peripheral Ready */ -# define SYSCON_PRADC_R1 (1 << 1) /* Bit 1: ADC Module 1 Peripheral Ready */ - -/* Analog Comparator Peripheral Ready */ - -#define SYSCON_PRACMP_R0 (1 << 0) /* Bit 0: Analog Comparator Module 0 Peripheral Ready */ - -/* EEPROM Peripheral Ready */ - -#define SYSCON_PREEPROM_0 (1 << 0) /* Bit 0: EEPROM Module Peripheral Ready */ - -/* 2/64-BitWide Timer Peripheral Ready */ - -#define SYSCON_PRWTIMER(n) (1 << (n)) /* Bit n: 32/64-Bit Wide General-Purpose Timer n Peripheral Ready */ -# define SYSCON_PRWTIMER_R0 (1 << 0) /* Bit 0: 32/64-Bit Wide General-Purpose Timer 0 Peripheral Ready */ -# define SYSCON_PRWTIMER_R1 (1 << 1) /* Bit 1: 32/64-Bit Wide General-Purpose Timer 1 Peripheral Ready */ -# define SYSCON_PRWTIMER_R2 (1 << 2) /* Bit 2: 32/64-Bit Wide General-Purpose Timer 2 Peripheral Ready */ -# define SYSCON_PRWTIMER_R3 (1 << 3) /* Bit 3: 32/64-Bit Wide General-Purpose Timer 3 Peripheral Ready */ -# define SYSCON_PRWTIMER_R4 (1 << 4) /* Bit 4: 32/64-Bit Wide General-Purpose Timer 4 Peripheral Ready */ -# define SYSCON_PRWTIMER_R5 (1 << 5) /* Bit 5: 32/64-Bit Wide General-Purpose Timer 5 Peripheral Ready */ - -/* System Control Legacy Register Bit Definitions *******************************************/ -/* Device Capabilities 0 */ - -#define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ -#define SYSCON_DC0_FLASHSZ_MASK (0xffff << SYSCON_DC0_FLASHSZ_SHIFT) -#define SYSCON_DC0_SRAMSZ_SHIFT 16 /* Bits 31-16: SRAM Size */ -#define SYSCON_DC0_SRAMSZ_MASK (0xffff << SYSCON_DC0_SRAMSZ_SHIFT) - -/* Device Capabilities 1 */ - -#define SYSCON_DC1_JTAG (1 << 0) /* Bit 0: JTAG Present */ -#define SYSCON_DC1_SWD (1 << 1) /* Bit 1: SWD Present */ -#define SYSCON_DC1_SWO (1 << 2) /* Bit 2: SWO Trace Port Present */ -#define SYSCON_DC1_WDT0 (1 << 3) /* Bit 3: Watchdog Timer 0 Present */ -#define SYSCON_DC1_PLL (1 << 4) /* Bit 4: PLL Present */ -#define SYSCON_DC1_TEMPSNS (1 << 5) /* Bit 5: Temp Sensor Present */ -#define SYSCON_DC1_HIB (1 << 6) /* Bit 6: Hibernation Module Present */ -#define SYSCON_DC1_MPU (1 << 7) /* Bit 7: MPU Present */ -#define SYSCON_DC1_MAXADC0SPD_SHIFT (8) /* Bits 9-8: Max ADC Speed */ -#define SYSCON_DC1_MAXADC0SPD_MASK (3 << SYSCON_DC1_MAXADC0SPD_SHIFT) -#define SYSCON_DC1_MAXADC1SPD_SHIFT (10) /* Bits 10-11: Max ADC Speed */ -#define SYSCON_DC1_MAXADC1SPD_MASK (3 << SYSCON_DC1_MAXADC1SPD_SHIFT) -#define SYSCON_DC1_MINSYSDIV_SHIFT 12 /* Bits 12-15: System Clock Divider Minimum */ -#define SYSCON_DC1_MINSYSDIV_MASK (15 << SYSCON_DC1_MINSYSDIV_SHIFT) -#define SYSCON_DC1_ADC0 (1 << 16) /* Bit 16: ADC0 Module Present */ -#define SYSCON_DC1_ADC1 (1 << 17) /* Bit 17: ADC1 Module Present */ -#define SYSCON_DC1_PWM0 (1 << 20) /* Bit 20: PWM0 Module Present */ -#define SYSCON_DC1_PWM1 (1 << 21) /* Bit 21: PWM1 Module Present */ -#define SYSCON_DC1_CAN0 (1 << 24) /* Bit 24: CAN0 Module Present */ -#define SYSCON_DC1_CAN1 (1 << 25) /* Bit 25: CAN1 Module Present */ -#define SYSCON_DC1_WDT1 (1 << 28) /* Bit 28: Watchdog Timer 1 Present */ - -/* Device Capabilities 2 */ - -#define SYSCON_DC2_UART0 (1 << 0) /* Bit 0: UART0 Module Present */ -#define SYSCON_DC2_UART1 (1 << 1) /* Bit 1: UART1 Module Present */ -#define SYSCON_DC2_UART2 (1 << 2) /* Bit 2: UART2 Module Present */ -#define SYSCON_DC2_SSI0 (1 << 4) /* Bit 4: SSI0 Module Present */ -#define SYSCON_DC2_SSI1 (1 << 5) /* Bit 5: SSI1 Module Present */ -#define SYSCON_DC2_QEI0 (1 << 8) /* Bit 8: QEI0 Module Present */ -#define SYSCON_DC2_QEI1 (1 << 9) /* Bit 9: QEI1 Module Present */ -#define SYSCON_DC2_I2C0 (1 << 12) /* Bit 12: I2C Module 0 Present */ -#define SYSCON_DC2_I2C0HS (1 << 13) /* Bit 13: I2C Module 0 Speed */ -#define SYSCON_DC2_I2C1 (1 << 14) /* Bit 14: I2C Module 1 Present */ -#define SYSCON_DC2_I2C1HS (1 << 15) /* Bit 15: I2C Module 1 Speed */ -#define SYSCON_DC2_TIMER0 (1 << 16) /* Bit 16: Timer 0 Present */ -#define SYSCON_DC2_TIMER1 (1 << 17) /* Bit 17: Timer 1 Present */ -#define SYSCON_DC2_TIMER2 (1 << 18) /* Bit 18: Timer 2 Present */ -#define SYSCON_DC2_TIMER3 (1 << 19) /* Bit 19: Timer 3 Present */ -#define SYSCON_DC2_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Present */ -#define SYSCON_DC2_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Present */ -#define SYSCON_DC2_COMP2 (1 << 26) /* Bit 26: Analog Comparator 2 Present */ -#define SYSCON_DC2_I2S0 (1 << 28) /* Bit 28: I2S Module 0 Present */ -#define SYSCON_DC2_EPI0 (1 << 30) /* Bit 30: EPI Module 0 Present */ - -/* Device Capabilities 3 */ - -#define SYSCON_DC3_PWM0 (1 << 0) /* Bit 0: PWM0 Pin Present */ -#define SYSCON_DC3_PWM1 (1 << 1) /* Bit 1: PWM1 Pin Present */ -#define SYSCON_DC3_PWM2 (1 << 2) /* Bit 2: PWM2 Pin Present */ -#define SYSCON_DC3_PWM3 (1 << 3) /* Bit 3: PWM3 Pin Present */ -#define SYSCON_DC3_PWM4 (1 << 4) /* Bit 4: PWM4 Pin Present */ -#define SYSCON_DC3_PWM5 (1 << 5) /* Bit 5: PWM5 Pin Present */ -#define SYSCON_DC3_C0MINUS (1 << 6) /* Bit 6: C0- Pin Present */ -#define SYSCON_DC3_C0PLUS (1 << 7) /* Bit 7: C0+ Pin Present */ -#define SYSCON_DC3_C0O (1 << 8) /* Bit 8: C0o Pin Present */ -#define SYSCON_DC3_C1MINUS (1 << 9) /* Bit 9: C1- Pin Present */ -#define SYSCON_DC3_C1PLUS (1 << 10) /* Bit 10: C1+ Pin Present */ -#define SYSCON_DC3_C1O (1 << 11) /* Bit 11: C1o Pin Present */ -#define SYSCON_DC3_C2MINUS (1 << 12) /* Bit 12: C2- Pin Present */ -#define SYSCON_DC3_C2PLUS (1 << 13) /* Bit 13: C2+ Pin Present */ -#define SYSCON_DC3_C2O (1 << 14) /* Bit 14: C2o Pin Present */ -#define SYSCON_DC3_PWMFAULT (1 << 15) /* Bit 15: PWM Fault Pin Pre */ -#define SYSCON_DC3_ADC0AIN0 (1 << 16) /* Bit 16: ADC Module 0 AIN0 Pin Present */ -#define SYSCON_DC3_ADC0AIN1 (1 << 17) /* Bit 17: ADC Module 0 AIN1 Pin Present */ -#define SYSCON_DC3_ADC0AIN2 (1 << 18) /* Bit 18: ADC Module 0 AIN2 Pin Present */ -#define SYSCON_DC3_ADC0AIN3 (1 << 19) /* Bit 19: ADC Module 0 AIN3 Pin Present */ -#define SYSCON_DC3_ADC0AIN4 (1 << 20) /* Bit 20: ADC Module 0 AIN4 Pin Present */ -#define SYSCON_DC3_ADC0AIN5 (1 << 21) /* Bit 21: ADC Module 0 AIN5 Pin Present */ -#define SYSCON_DC3_ADC0AIN6 (1 << 22) /* Bit 22: ADC Module 0 AIN6 Pin Present */ -#define SYSCON_DC3_ADC0AIN7 (1 << 23) /* Bit 23: ADC Module 0 AIN7 Pin Present */ -#define SYSCON_DC3_CCP0 (1 << 24) /* Bit 24: T0CCP0 Pin Present */ -#define SYSCON_DC3_CCP1 (1 << 25) /* Bit 25: T0CCP1 Pin Present */ -#define SYSCON_DC3_CCP2 (1 << 26) /* Bit 26: T1CCP0 Pin Present */ -#define SYSCON_DC3_CCP3 (1 << 27) /* Bit 27: T1CCP1 Pin Present */ -#define SYSCON_DC3_CCP4 (1 << 28) /* Bit 28: T2CCP0 Pin Present */ -#define SYSCON_DC3_CCP5 (1 << 29) /* Bit 29: T2CCP1 Pin Present */ -#define SYSCON_DC3_32KHZ (1 << 31) /* Bit 31: 32KHz Input Clock Available */ - -/* Device Capabilities 4 */ - -#define SYSCON_DC4_GPIO(n) (1 << (n)) -#define SYSCON_DC4_GPIOA (1 << 0) /* Bit 0: GPIO Port A Present */ -#define SYSCON_DC4_GPIOB (1 << 1) /* Bit 1: GPIO Port B Present */ -#define SYSCON_DC4_GPIOC (1 << 2) /* Bit 2: GPIO Port C Present */ -#define SYSCON_DC4_GPIOD (1 << 3) /* Bit 3: GPIO Port D Present */ -#define SYSCON_DC4_GPIOE (1 << 4) /* Bit 4: GPIO Port E Present */ -#define SYSCON_DC4_GPIOF (1 << 5) /* Bit 5: GPIO Port F Present */ -#define SYSCON_DC4_GPIOG (1 << 6) /* Bit 6: GPIO Port G Present */ -#define SYSCON_DC4_GPIOH (1 << 7) /* Bit 7: GPIO Port H Present */ -#define SYSCON_DC4_GPIOJ (1 << 8) /* Bit 8: GPIO Port J Present */ - -#define SYSCON_DC4_ROM (1 << 12) /* Bit 12: Internal Code ROM Present */ -#define SYSCON_DC4_UDMA (1 << 13) /* Bit 13: Micro-DMA Module Present */ -#define SYSCON_DC4_CCP6 (1 << 14) /* Bit 14: T3CCP0 Pin Present */ -#define SYSCON_DC4_CCP7 (1 << 15) /* Bit 15: T3CCP1 Pin Present */ -#define SYSCON_DC4_PICAL (1 << 18) /* Bit 18: PIOSC Calibrate */ -#define SYSCON_DC4_E1588 (1 << 24) /* Bit 24: 1588 Capable */ -#define SYSCON_DC4_EMAC0 (1 << 28) /* Bit 28: Ethernet MAC0 Present */ -#define SYSCON_DC4_EPHY0 (1 << 30) /* Bit 30: Ethernet PHY0 Present */ - -/* Device Capabilities 5 */ - -#define LM_SYSCON_DC5_PWM0 (1 << 0) /* Bit 0: PWM0 Pin Present */ -#define LM_SYSCON_DC5_PWM1 (1 << 1) /* Bit 1: PWM1 Pin Present */ -#define LM_SYSCON_DC5_PWM2 (1 << 2) /* Bit 2: PWM2 Pin Present */ -#define LM_SYSCON_DC5_PWM3 (1 << 3) /* Bit 3: PWM3 Pin Present */ -#define LM_SYSCON_DC5_PWM4 (1 << 4) /* Bit 4: PWM4 Pin Present */ -#define LM_SYSCON_DC5_PWM5 (1 << 5) /* Bit 5: PWM5 Pin Present */ -#define LM_SYSCON_DC5_PWM6 (1 << 6) /* Bit 6: PWM6 Pin Present */ -#define LM_SYSCON_DC5_PWM7 (1 << 7) /* Bit 7: PWM7 Pin Present */ -#define LM_SYSCON_DC5_PWMESYNC (1 << 20) /* Bit 20: PWM Extended SYNC Active */ -#define LM_SYSCON_DC5_PWMEFLT (1 << 21) /* Bit 21: PWM Extended Fault Active */ -#define LM_SYSCON_DC5_PWMFAULT0 (1 << 24) /* Bit 24: PWM Fault 0 Pin Present */ -#define LM_SYSCON_DC5_PWMFAULT1 (1 << 25) /* Bit 25: PWM Fault 1 Pin Present */ -#define LM_SYSCON_DC5_PWMFAULT2 (1 << 26) /* Bit 26: PWM Fault 2 Pin Present */ -#define LM_SYSCON_DC5_PWMFAULT3 (1 << 27) /* Bit 27: PWM Fault 3 Pin Present */ - -/* Device Capabilities 6 */ - -#define LM_SYSCON_DC6_USB0_SHIFT (0) /* Bits 0-1: USB Module 0 Present */ -#define LM_SYSCON_DC6_USB0_MASK (3 << LM_SYSCON_DC6_USB0_SHIFT) -# define LM_SYSCON_DC6_USB0_NONE (1 << LM_SYSCON_DC6_USB0_SHIFT) -# define LM_SYSCON_DC6_USB0_DEVICE (2 << LM_SYSCON_DC6_USB0_SHIFT) -# define LM_SYSCON_DC6_USB0_HOST (3 << LM_SYSCON_DC6_USB0_SHIFT) -# define LM_SYSCON_DC6_USB0_OTG (3 << LM_SYSCON_DC6_USB0_SHIFT) -#define LM_SYSCON_DC6_USB0PHY (1 << 4) /* Bit 4: USB Module 0 PHY Present */ - -/* Device Capabilities 7 */ - -#define LM_SYSCON_DC7_DMACH0 (1 << 0) /* Bit 0: DMA Channel 0 */ -#define LM_SYSCON_DC7_DMACH1 (1 << 1) /* Bit 1: DMA Channel 1 */ -#define LM_SYSCON_DC7_DMACH2 (1 << 2) /* Bit 2: DMA Channel 2 */ -#define LM_SYSCON_DC7_DMACH3 (1 << 3) /* Bit 3: DMA Channel 3 */ -#define LM_SYSCON_DC7_DMACH4 (1 << 4) /* Bit 4: DMA Channel 4 */ -#define LM_SYSCON_DC7_DMACH5 (1 << 5) /* Bit 5: DMA Channel 5 */ -#define LM_SYSCON_DC7_DMACH6 (1 << 6) /* Bit 6: DMA Channel 6 */ -#define LM_SYSCON_DC7_DMACH7 (1 << 7) /* Bit 7: DMA Channel 7 */ -#define LM_SYSCON_DC7_DMACH8 (1 << 8) /* Bit 8: DMA Channel 8 */ -#define LM_SYSCON_DC7_DMACH9 (1 << 9) /* Bit 9: DMA Channel 9 */ -#define LM_SYSCON_DC7_DMACH10 (1 << 10) /* Bit 10: DMA Channel 10 */ -#define LM_SYSCON_DC7_DMACH11 (1 << 11) /* Bit 11: DMA Channel 11 */ -#define LM_SYSCON_DC7_DMACH12 (1 << 12) /* Bit 12: DMA Channel 12 */ -#define LM_SYSCON_DC7_DMACH13 (1 << 13) /* Bit 13: DMA Channel 13 */ -#define LM_SYSCON_DC7_DMACH14 (1 << 14) /* Bit 14: DMA Channel 14 */ -#define LM_SYSCON_DC7_DMACH15 (1 << 15) /* Bit 15: DMA Channel 15 */ -#define LM_SYSCON_DC7_DMACH16 (1 << 16) /* Bit 16: DMA Channel 16 */ -#define LM_SYSCON_DC7_DMACH17 (1 << 17) /* Bit 17: DMA Channel 17 */ -#define LM_SYSCON_DC7_DMACH18 (1 << 18) /* Bit 18: DMA Channel 18 */ -#define LM_SYSCON_DC7_DMACH19 (1 << 19) /* Bit 19: DMA Channel 19 */ -#define LM_SYSCON_DC7_DMACH20 (1 << 20) /* Bit 20: DMA Channel 20 */ -#define LM_SYSCON_DC7_DMACH21 (1 << 21) /* Bit 21: DMA Channel 21 */ -#define LM_SYSCON_DC7_DMACH22 (1 << 22) /* Bit 22: DMA Channel 22 */ -#define LM_SYSCON_DC7_DMACH23 (1 << 23) /* Bit 23: DMA Channel 23 */ -#define LM_SYSCON_DC7_DMACH24 (1 << 24) /* Bit 24: DMA Channel 24 */ -#define LM_SYSCON_DC7_DMACH25 (1 << 25) /* Bit 25: DMA Channel 25 */ -#define LM_SYSCON_DC7_DMACH26 (1 << 26) /* Bit 26: DMA Channel 26 */ -#define LM_SYSCON_DC7_DMACH27 (1 << 27) /* Bit 27: DMA Channel 27 */ -#define LM_SYSCON_DC7_DMACH28 (1 << 28) /* Bit 28: DMA Channel 28 */ -#define LM_SYSCON_DC7_DMACH29 (1 << 29) /* Bit 29: DMA Channel 29 */ -#define LM_SYSCON_DC7_DMACH30 (1 << 30) /* Bit 30: DMA Channel 30 */ - -/* Device Capabilities 8 */ - -#define LM_SYSCON_DC8_ADC0AIN0 (1 << 0) /* Bit 0: ADC Module 0 AIN0 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN1 (1 << 1) /* Bit 1: ADC Module 0 AIN1 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN2 (1 << 2) /* Bit 2: ADC Module 0 AIN2 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN3 (1 << 3) /* Bit 3: ADC Module 0 AIN3 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN4 (1 << 4) /* Bit 4: ADC Module 0 AIN4 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN5 (1 << 5) /* Bit 5: ADC Module 0 AIN5 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN6 (1 << 6) /* Bit 6: ADC Module 0 AIN6 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN7 (1 << 7) /* Bit 7: ADC Module 0 AIN7 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN8 (1 << 8) /* Bit 8: ADC Module 0 AIN8 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN9 (1 << 9) /* Bit 9: ADC Module 0 AIN9 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN10 (1 << 10) /* Bit 10: ADC Module 0 AIN10 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN11 (1 << 11) /* Bit 11: ADC Module 0 AIN11 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN12 (1 << 12) /* Bit 12: ADC Module 0 AIN12 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN13 (1 << 13) /* Bit 13: ADC Module 0 AIN13 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN14 (1 << 14) /* Bit 14: ADC Module 0 AIN14 Pin Present */ -#define LM_SYSCON_DC8_ADC0AIN15 (1 << 15) /* Bit 15: ADC Module 0 AIN15 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN0 (1 << 16) /* Bit 16: ADC Module 1 AIN0 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN1 (1 << 17) /* Bit 17: ADC Module 1 AIN1 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN2 (1 << 18) /* Bit 18: ADC Module 1 AIN2 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN3 (1 << 19) /* Bit 19: ADC Module 1 AIN3 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN4 (1 << 20) /* Bit 20: ADC Module 1 AIN4 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN5 (1 << 21) /* Bit 21: ADC Module 1 AIN5 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN6 (1 << 22) /* Bit 22: ADC Module 1 AIN6 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN7 (1 << 23) /* Bit 23: ADC Module 1 AIN7 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN8 (1 << 24) /* Bit 24: ADC Module 1 AIN8 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN9 (1 << 25) /* Bit 25: ADC Module 1 AIN9 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN10 (1 << 26) /* Bit 26: ADC Module 1 AIN10 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN11 (1 << 27) /* Bit 27: ADC Module 1 AIN11 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN12 (1 << 28) /* Bit 28: ADC Module 1 AIN12 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN13 (1 << 29) /* Bit 29: ADC Module 1 AIN13 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN14 (1 << 30) /* Bit 30: ADC Module 1 AIN14 Pin Present */ -#define LM_SYSCON_DC8_ADC1AIN15 (1 << 31) /* Bit 31: ADC Module 1 AIN15 Pin Present */ - -/* Software Reset Control 0 */ - -#define SYSCON_SRCR0_WDT0 (1 << 3) /* Bit 3: Watchdog Timer 0 Reset Control */ -#define SYSCON_SRCR0_HIB (1 << 6) /* Bit 6: Hibernation Module Reset Control */ -#define SYSCON_SRCR0_ADC0 (1 << 16) /* Bit 16: ADC0 Reset Control */ -#define SYSCON_SRCR0_ADC1 (1 << 17) /* Bit 17: ADC1 Reset Control */ -#define SYSCON_SRCR0_CAN0 (1 << 24) /* Bit 24: CAN0 Reset Control */ -#define SYSCON_SRCR0_WDT1 (1 << 28) /* Bit 28: Watchdog Timer 1 Reset Control */ - -/* Software Reset Control 1 */ - -#define SYSCON_SRCR1_UART0 (1 << 0) /* Bit 0: UART0 Reset Control */ -#define SYSCON_SRCR1_UART1 (1 << 1) /* Bit 1: UART1 Reset Control */ -#define SYSCON_SRCR1_UART2 (1 << 2) /* Bit 2: UART2 Reset Control */ -#define SYSCON_SRCR1_SSI0 (1 << 4) /* Bit 4: SSI0 Reset Control */ -#define SYSCON_SRCR1_SSI1 (1 << 5) /* Bit 5: SSI1 Reset Control */ -#define SYSCON_SRCR1_I2C0 (1 << 12) /* Bit 12: I2C 0 Reset Control */ -#define SYSCON_SRCR1_I2C1 (1 << 14) /* Bit 14: I2C 1 Reset Control */ -#define SYSCON_SRCR1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Reset Control */ -#define SYSCON_SRCR1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Reset Control */ -#define SYSCON_SRCR1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Reset Control */ -#define SYSCON_SRCR1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Reset Control */ -#define SYSCON_SRCR1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Reset Control */ -#define SYSCON_SRCR1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Reset Control */ - -/* Software Reset Control 2 */ - -#define SYSCON_SRCR2_GPIO(n) (1 << (n)) -#define SYSCON_SRCR2_GPIOA (1 << 0) /* Bit 0: Port A Reset Control */ -#define SYSCON_SRCR2_GPIOB (1 << 1) /* Bit 1: Port B Reset Control */ -#define SYSCON_SRCR2_GPIOC (1 << 2) /* Bit 2: Port C Reset Control */ -#define SYSCON_SRCR2_GPIOD (1 << 3) /* Bit 3: Port D Reset Control */ -#define SYSCON_SRCR2_GPIOE (1 << 4) /* Bit 4: Port E Reset Control */ -#define SYSCON_SRCR2_GPIOF (1 << 5) /* Bit 5: Port F Reset Control */ -#define SYSCON_SRCR2_UDMA (1 << 13) /* Bit 13: Micro-DMA Reset Control */ -#define SYSCON_SRCR2_USB0 (1 << 16) /* Bit 16: USB0 Reset Control */ - -/* Run Mode Clock Gating Control Register 0 */ - -#define SYSCON_RCGC0_WDT0 (1 << 3) /* Bit 3: WDT0 Clock Gating Control */ -#define SYSCON_RCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_RCGC0_MAXADC0SPD_SHIFT (8) /* Bits 8-9: ADC0 Sample Speed */ -#define SYSCON_RCGC0_MAXADC0SPD_MASK (3 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC0_125KSPS (0 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC0_250KSPS (1 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC0_500KSPS (2 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC0_1MSPS (3 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) -#define SYSCON_RCGC0_MAXADC1SPD_SHIFT (8) /* Bits 10-11: ADC1 Sample Speed */ -#define SYSCON_RCGC0_MAXADC1SPD_MASK (3 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC1_125KSPS (0 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC1_250KSPS (1 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC1_500KSPS (2 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) -# define SYSCON_RCGC0_MAXADC1_1MSPS (3 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) -#define SYSCON_RCGC0_ADC0 (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ -#define SYSCON_RCGC0_CAN0 (1 << 24) /* Bit 24: CAN0 Clock Gating Control */ -#define SYSCON_RCGC0_WDT1 (1 << 28) /* Bit 28: WDT1 Clock Gating Control */ - -/* Run Mode Clock Gating Control Register 1 */ - -#define SYSCON_RCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_RCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_RCGC1_UART2 (1 << 2) /* Bit 2: UART2 Clock Gating Control */ -#define SYSCON_RCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_RCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_RCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_RCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_RCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_RCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_RCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Run Mode Clock Gating Control Register 2 */ - -#define SYSCON_RCGC2_GPIO(n) (1 << (n)) -#define SYSCON_RCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_RCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_RCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_RCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_RCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_RCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_RCGC2_UDMA (1 << 13) /* Bit 13: Micro-DMA Clock Gating Control */ -#define SYSCON_RCGC2_USB0 (1 << 16) /* Bit 16: USB0 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 0 */ - -#define SYSCON_SCGC0_WDT0 (1 << 3) /* Bit 3: WDT0 Clock Gating Control */ -#define SYSCON_SCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_SCGC0_ADC0 (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ -#define SYSCON_SCGC0_ADC1 (1 << 17) /* Bit 17: ADC1 Clock Gating Control */ -#define SYSCON_SCGC0_CAN0 (1 << 24) /* Bit 24: CAN0 Clock Gating Control */ -#define SYSCON_SCGC0_WDT1 (1 << 28) /* Bit 28: WDT1 Clock Gating Control */ - -/* Sleep Mode Clock Gating Control Register 1 */ - -#define SYSCON_SCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_SCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_SCGC1_UART2 (1 << 2) /* Bit 2: UART2 Clock Gating Control */ -#define SYSCON_SCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_SCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_SCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_SCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_SCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_SCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_SCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Sleep Mode Clock Gating Control Register 2 */ - -#define SYSCON_SCGC2_GPIO(n) (1 << (n)) -#define SYSCON_SCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_SCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_SCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_SCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_SCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_SCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_SCGC2_UDMA (1 << 13) /* Bit 13: Micro-DMA Clock Gating Control */ -#define SYSCON_SCGC2_USB0 (1 << 16) /* Bit 16: PHY0 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 0 */ - -#define SYSCON_DCGC0_WDT0 (1 << 3) /* Bit 3: WDT0 Clock Gating Control */ -#define SYSCON_DCGC0_HIB (1 << 6) /* Bit 6: HIB Clock Gating Control */ -#define SYSCON_DCGC0_ADC0 (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ -#define SYSCON_DCGC0_ADC1 (1 << 17) /* Bit 17: ADC1 Clock Gating Control */ -#define SYSCON_DCGC0_CAN0 (1 << 24) /* Bit 24: CAN0 Clock Gating Control */ -#define SYSCON_DCGC0_WDT1 (1 << 28) /* Bit 28: WDT1 Clock Gating Control */ - -/* Deep Sleep Mode Clock Gating Control Register 1 */ - -#define SYSCON_DCGC1_UART0 (1 << 0) /* Bit 0: UART0 Clock Gating Control */ -#define SYSCON_DCGC1_UART1 (1 << 1) /* Bit 1: UART1 Clock Gating Control */ -#define SYSCON_DCGC1_UART2 (1 << 2) /* Bit 2: UART2 Clock Gating Control */ -#define SYSCON_DCGC1_SSI0 (1 << 4) /* Bit 4: SSI0 Clock Gating Control */ -#define SYSCON_DCGC1_SSI1 (1 << 5) /* Bit 5: SSI1 Clock Gating Control */ -#define SYSCON_DCGC1_I2C0 (1 << 12) /* Bit 12: I2C0 Clock Gating Control */ -#define SYSCON_DCGC1_I2C1 (1 << 14) /* Bit 14: I2C1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER0 (1 << 16) /* Bit 16: Timer 0 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER1 (1 << 17) /* Bit 17: Timer 1 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER2 (1 << 18) /* Bit 18: Timer 2 Clock Gating Control */ -#define SYSCON_DCGC1_TIMER3 (1 << 19) /* Bit 19: Timer 3 Clock Gating Control */ -#define SYSCON_DCGC1_COMP0 (1 << 24) /* Bit 24: Analog Comparator 0 Clock Gating */ -#define SYSCON_DCGC1_COMP1 (1 << 25) /* Bit 25: Analog Comparator 1 Clock Gating */ - -/* Deep Sleep Mode Clock Gating Control Register 2 */ - -#define SYSCON_DCGC2_GPIO(n) (1 << (n)) -#define SYSCON_DCGC2_GPIOA (1 << 0) /* Bit 0: Port A Clock Gating Control */ -#define SYSCON_DCGC2_GPIOB (1 << 1) /* Bit 1: Port B Clock Gating Control */ -#define SYSCON_DCGC2_GPIOC (1 << 2) /* Bit 2: Port C Clock Gating Control */ -#define SYSCON_DCGC2_GPIOD (1 << 3) /* Bit 3: Port D Clock Gating Control */ -#define SYSCON_DCGC2_GPIOE (1 << 4) /* Bit 4: Port E Clock Gating Control */ -#define SYSCON_DCGC2_GPIOF (1 << 5) /* Bit 5: Port F Clock Gating Control */ -#define SYSCON_DCGC2_UDMA (1 << 13) /* Bit 13: Micro-DMA Clock Gating Control */ -#define SYSCON_DCGC2_USB0 (1 << 16) /* Bit 16: PHY0 Clock Gating Control */ - -/* Device Capabilities */ - -#define LM_SYSCON_DC9_ADC0DC0 (1 << 0) /* Bit 0: ADC0 DC0 Present */ -#define LM_SYSCON_DC9_ADC0DC1 (1 << 1) /* Bit 1: ADC0 DC1 Present */ -#define LM_SYSCON_DC9_ADC0DC2 (1 << 2) /* Bit 2: ADC0 DC2 Present */ -#define LM_SYSCON_DC9_ADC0DC3 (1 << 3) /* Bit 3: ADC0 DC3 Present */ -#define LM_SYSCON_DC9_ADC0DC4 (1 << 4) /* Bit 4: ADC0 DC4 Present */ -#define LM_SYSCON_DC9_ADC0DC5 (1 << 5) /* Bit 5: ADC0 DC5 Present */ -#define LM_SYSCON_DC9_ADC0DC6 (1 << 6) /* Bit 6: ADC0 DC6 Present */ -#define LM_SYSCON_DC9_ADC0DC7 (1 << 7) /* Bit 7: ADC0 DC7 Present */ -#define LM_SYSCON_DC9_ADC1DC0 (1 << 16) /* Bit 16: ADC1 DC0 Present */ -#define LM_SYSCON_DC9_ADC1DC1 (1 << 17) /* Bit 17: ADC1 DC1 Present */ -#define LM_SYSCON_DC9_ADC1DC2 (1 << 18) /* Bit 18: ADC1 DC2 Present */ -#define LM_SYSCON_DC9_ADC1DC3 (1 << 19) /* Bit 19: ADC1 DC3 Present */ -#define LM_SYSCON_DC9_ADC1DC4 (1 << 20) /* Bit 20: ADC1 DC4 Present */ -#define LM_SYSCON_DC9_ADC1DC5 (1 << 21) /* Bit 21: ADC1 DC5 Present */ -#define LM_SYSCON_DC9_ADC1DC6 (1 << 22) /* Bit 22: ADC1 DC6 Present */ -#define LM_SYSCON_DC9_ADC1DC7 (1 << 23) /* Bit 23: ADC1 DC7 Present */ - -/* Non-Volatile Memory Information */ - -#define LM_SYSCON_NVMSTAT_FWB (1 << 0) /* Bit 0: 32 Word Flash Write Buffer Available */ - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -/******************************************************************************************** - * Public Data - ********************************************************************************************/ - -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM4F_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm4f_vectors.h b/nuttx/arch/arm/src/lm/chip/lm4f_vectors.h deleted file mode 100644 index c8e69377b..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm4f_vectors.h +++ /dev/null @@ -1,223 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm4f_vectors.S - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Preprocessor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Vectors - ************************************************************************************/ - -/* This file is included by lm_vectors.S. It provides the macro VECTOR that - * supplies ach Stellaris vector in terms of a (lower-case) ISR label and an - * (upper-case) IRQ number as defined in arch/arm/include/lm/lm4f_irq.h. - * lm_vectors.S will define the VECTOR in different ways in order to generate - * the interrupt vectors and handlers in their final form. - */ - -#if defined(CONFIG_ARCH_CHIP_LM4F120) - -/* If the common ARMv7-M vector handling is used, then all it needs is the following - * definition that provides the number of supported vectors. - */ - -# ifdef CONFIG_ARMV7M_CMNVECTOR - -/* Reserve 155 interrupt table entries for I/O interrupts. */ - -ARMV7M_PERIPHERAL_INTERRUPTS 155 - -# else - -VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */ -VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */ -VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */ -VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */ - -VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */ -VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */ -VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */ -VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */ -VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */ -UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */ -UNUSED(LM_RESERVED_26) /* Vector 26: Reserved */ -UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */ -UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */ -UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */ - -VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */ -VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */ -VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */ -VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */ -VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timers 0 and 1 */ -VECTOR(lm_timer0a, LM_IRQ_TIMER0A) /* Vector 35: 16/32-Bit Timer 0 A */ -VECTOR(lm_timer0b, LM_IRQ_TIMER0B) /* Vector 36: 16/32-Bit Timer 0 B */ -VECTOR(lm_timer1a, LM_IRQ_TIMER1A) /* Vector 37: 16/32-Bit Timer 1 A */ -VECTOR(lm_timer1b, LM_IRQ_TIMER1B) /* Vector 38: 16/32-Bit Timer 1 B */ -VECTOR(lm_timer2a, LM_IRQ_TIMER2A) /* Vector 39: 16/32-Bit Timer 2 A */ - -VECTOR(lm_timer2b, LM_IRQ_TIMER2B) /* Vector 40: 16/32-Bit Timer 2 B */ -VECTOR(lm_compare0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */ -VECTOR(lm_compare1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */ -UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */ -VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */ -VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH and EEPROM Control */ -VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */ -UNUSED(LM_RESERVED_47) /* Vector 47: Reserved */ -UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */ -VECTOR(lm_uart2, LM_IRQ_UART2) /* Vector 22: UART 2 */ - -VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: SSI 1 */ -VECTOR(lm_timer3a, LM_IRQ_TIMER3A) /* Vector 51: 16/32-Bit Timer 3 A */ -VECTOR(lm_timer3b, LM_IRQ_TIMER3B) /* Vector 52: 16/32-Bit Timer 3 B */ -VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */ -UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */ -VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */ -UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */ -UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */ -UNUSED(LM_RESERVED_58) /* Vector 58: Reserved */ -VECTOR(lm_hibernate, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */ - -VECTOR(lm_usb, LM_IRQ_USB) /* Vector 60: USB */ -UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */ -VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software */ -VECTOR(lm_udmaerro, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */ -VECTOR(lm_adc1_0, LM_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */ -VECTOR(lm_adc1_1, LM_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */ -VECTOR(lm_adc1_2, LM_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */ -VECTOR(lm_adc1_3, LM_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */ -UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */ -UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */ - -UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */ -UNUSED(LM_RESERVED_71) /* Vector 71: Reserved */ -UNUSED(LM_RESERVED_72) /* Vector 72: Reserved */ -VECTOR(lm_ssi2, LM_IRQ_SSI2) /* Vector 73: SSI 2 */ -VECTOR(lm_ssi3, LM_IRQ_SSI3) /* Vector 74: SSI 3 */ -VECTOR(lm_uart3, LM_IRQ_UART3) /* Vector 75: UART 3 */ -VECTOR(lm_uart4, LM_IRQ_UART4) /* Vector 76: UART 4 */ -VECTOR(lm_uart5, LM_IRQ_UART5) /* Vector 77: UART 5 */ -VECTOR(lm_uart6, LM_IRQ_UART6) /* Vector 78: UART 6 */ -VECTOR(lm_uart7, LM_IRQ_UART7) /* Vector 79: UART 7 */ - -UNUSED(LM_RESERVED_80) /* Vector 80: Reserved */ -UNUSED(LM_RESERVED_81) /* Vector 81: Reserved */ -UNUSED(LM_RESERVED_82) /* Vector 82: Reserved */ -UNUSED(LM_RESERVED_83) /* Vector 83: Reserved */ -VECTOR(lm_i2c2, LM_IRQ_I2C2) /* Vector 84: I2C 2 */ -VECTOR(lm_i2c3, LM_IRQ_I2C3) /* Vector 85: I2C 3 */ -VECTOR(lm_timer4a, LM_IRQ_TIMER4A) /* Vector 86: 16/32-Bit Timer 4 A */ -VECTOR(lm_timer4b, LM_IRQ_TIMER4B) /* Vector 87: 16/32-Bit Timer 4 B */ -UNUSED(LM_RESERVED_88) /* Vector 88: Reserved */ -UNUSED(LM_RESERVED_89) /* Vector 89: Reserved */ - -UNUSED(LM_RESERVED_90) /* Vector 90: Reserved */ -UNUSED(LM_RESERVED_91) /* Vector 91: Reserved */ -UNUSED(LM_RESERVED_92) /* Vector 92: Reserved */ -UNUSED(LM_RESERVED_93) /* Vector 93: Reserved */ -UNUSED(LM_RESERVED_94) /* Vector 94: Reserved */ -UNUSED(LM_RESERVED_95) /* Vector 95: Reserved */ -UNUSED(LM_RESERVED_96) /* Vector 96: Reserved */ -UNUSED(LM_RESERVED_97) /* Vector 97: Reserved */ -UNUSED(LM_RESERVED_98) /* Vector 98: Reserved */ -UNUSED(LM_RESERVED_99) /* Vector 99: Reserved */ - -UNUSED(LM_RESERVED_100) /* Vector 100: Reserved */ -UNUSED(LM_RESERVED_101) /* Vector 101: Reserved */ -UNUSED(LM_RESERVED_102) /* Vector 102: Reserved */ -UNUSED(LM_RESERVED_103) /* Vector 103: Reserved */ -UNUSED(LM_RESERVED_104) /* Vector 104: Reserved */ -UNUSED(LM_RESERVED_105) /* Vector 105: Reserved */ -UNUSED(LM_RESERVED_106) /* Vector 106: Reserved */ -UNUSED(LM_RESERVED_107) /* Vector 107: Reserved */ -VECTOR(lm_timer5a, LM_IRQ_TIMER5A) /* Vector 108: 16/32-Bit Timer 5 A */ -VECTOR(lm_timer5b, LM_IRQ_TIMER5B) /* Vector 109: 16/32-Bit Timer 5 B */ - -VECTOR(lm_wtimer0a, LM_IRQ_WTIMER0A) /* Vector 110: 32/64-Bit Timer 0 A */ -VECTOR(lm_wtimer0b, LM_IRQ_WTIMER0B) /* Vector 111: 32/64-Bit Timer 0 B */ -VECTOR(lm_wtimer1a, LM_IRQ_WTIMER1A) /* Vector 112: 32/64-Bit Timer 1 A */ -VECTOR(lm_wtimer1b, LM_IRQ_WTIMER1B) /* Vector 113: 32/64-Bit Timer 1 B */ -VECTOR(lm_wtimer2a, LM_IRQ_WTIMER2A) /* Vector 114: 32/64-Bit Timer 2 A */ -VECTOR(lm_wtimer2b, LM_IRQ_WTIMER2B) /* Vector 115: 32/64-Bit Timer 2 B */ -VECTOR(lm_wtimer3a, LM_IRQ_WTIMER3A) /* Vector 116: 32/64-Bit Timer 3 A */ -VECTOR(lm_wtimer3b, LM_IRQ_WTIMER3B) /* Vector 117: 32/64-Bit Timer 3 B */ -VECTOR(lm_wtimer4a, LM_IRQ_WTIMER4A) /* Vector 118: 32/64-Bit Timer 4 A */ -VECTOR(lm_WTIMER4B, LM_IRQ_WTIMER4B) /* Vector 119: 32/64-Bit Timer 4 B */ - -VECTOR(lm_wtimer5a, LM_IRQ_WTIMER5A) /* Vector 120: 32/64-Bit Timer 5 A */ -VECTOR(lm_wtimer5b, LM_IRQ_WTIMER5B) /* Vector 121: 32/64-Bit Timer 5 B */ -VECTOR(lm_system, LM_IRQ_SYSTEM) /* Vector 122: System Exception (imprecise) */ -UNUSED(LM_RESERVED_123) /* Vector 123: Reserved */ -UNUSED(LM_RESERVED_124) /* Vector 124: Reserved */ -UNUSED(LM_RESERVED_125) /* Vector 125: Reserved */ -UNUSED(LM_RESERVED_126) /* Vector 126: Reserved */ -UNUSED(LM_RESERVED_127) /* Vector 127: Reserved */ -UNUSED(LM_RESERVED_128) /* Vector 128: Reserved */ -UNUSED(LM_RESERVED_129) /* Vector 129: Reserved */ - -UNUSED(LM_RESERVED_130) /* Vector 130: Reserved */ -UNUSED(LM_RESERVED_131) /* Vector 131: Reserved */ -UNUSED(LM_RESERVED_132) /* Vector 132: Reserved */ -UNUSED(LM_RESERVED_133) /* Vector 133: Reserved */ -UNUSED(LM_RESERVED_134) /* Vector 134: Reserved */ -UNUSED(LM_RESERVED_135) /* Vector 135: Reserved */ -UNUSED(LM_RESERVED_136) /* Vector 136: Reserved */ -UNUSED(LM_RESERVED_137) /* Vector 137: Reserved */ -UNUSED(LM_RESERVED_138) /* Vector 138: Reserved */ -UNUSED(LM_RESERVED_139) /* Vector 139: Reserved */ - -UNUSED(LM_RESERVED_140) /* Vector 140: Reserved */ -UNUSED(LM_RESERVED_141) /* Vector 141: Reserved */ -UNUSED(LM_RESERVED_142) /* Vector 142: Reserved */ -UNUSED(LM_RESERVED_143) /* Vector 143: Reserved */ -UNUSED(LM_RESERVED_144) /* Vector 144: Reserved */ -UNUSED(LM_RESERVED_145) /* Vector 145: Reserved */ -UNUSED(LM_RESERVED_146) /* Vector 146: Reserved */ -UNUSED(LM_RESERVED_147) /* Vector 147: Reserved */ -UNUSED(LM_RESERVED_148) /* Vector 148: Reserved */ -UNUSED(LM_RESERVED_149) /* Vector 149: Reserved */ - -UNUSED(LM_RESERVED_150) /* Vector 150: Reserved */ -UNUSED(LM_RESERVED_151) /* Vector 151: Reserved */ -UNUSED(LM_RESERVED_152) /* Vector 152: Reserved */ -UNUSED(LM_RESERVED_153) /* Vector 153: Reserved */ -UNUSED(LM_RESERVED_154) /* Vector 154: Reserved */ - -# endif /* CONFIG_ARMV7M_CMNVECTOR */ - -#else -# error "Vectors not known for this Stellaris chip" -#endif diff --git a/nuttx/arch/arm/src/lm/chip/lm_epi.h b/nuttx/arch/arm/src/lm/chip/lm_epi.h deleted file mode 100644 index 47d790615..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_epi.h +++ /dev/null @@ -1,113 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_epi.h - * - * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. - * Author: Max Neklyudov <macscomp@gmail.com> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* External Peripheral Interface Register Offsets ***********************************/ - -#define LM_EPI_CFG_OFFSET 0x000 -#define LM_EPI_SDRAMCFG_OFFSET 0x010 -#define LM_EPI_ADDRMAP_OFFSET 0x01C -#define LM_EPI_STAT_OFFSET 0x060 -#define LM_EPI_BAUD_OFFSET 0x004 - -/* External Peripheral Interface Register Addresses *********************************/ - -#define LM_EPI0_CFG (LM_EPI0_BASE + LM_EPI_CFG_OFFSET) -#define LM_EPI0_SDRAMCFG (LM_EPI0_BASE + LM_EPI_SDRAMCFG_OFFSET) -#define LM_EPI0_ADDRMAP (LM_EPI0_BASE + LM_EPI_ADDRMAP_OFFSET) -#define LM_EPI0_STAT (LM_EPI0_BASE + LM_EPI_STAT_OFFSET) -#define LM_EPI0_BAUD (LM_EPI0_BASE + LM_EPI_BAUD_OFFSET) - -/* External Peripheral Interface Register Bit Definitions ***************************/ - -/* EPI Configuration (EPICFG), offset 0x000 */ - -#define EPI_CFG_MODE_SHIFT 0 /* Bits 3-0: Mode Select */ -#define EPI_CFG_MODE_MASK (0x1f << EPI_CFG_MODE_SHIFT) -# define EPI_CFG_MODE_SDRAM (0x11 << EPI_CFG_MODE_SHIFT) /* SDRAM + BLKEN */ - -/* EPI Address Map (EPIADDRMAP), offset 0x01C */ - -#define EPI_ADDRMAP_ERADR_SHIFT 0 /* Bits 1-0: External RAM Address */ -#define EPI_ADDRMAP_ERADR_MASK (0x3 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_6 (0x1 << EPI_ADDRMAP_ERADR_SHIFT) -# define EPI_ADDRMAP_ERADR_8 (0x2 << EPI_ADDRMAP_ERADR_SHIFT) -#define EPI_ADDRMAP_ERSZ_SHIFT 2 /* Bits 3-2: External RAM Size */ -#define EPI_ADDRMAP_ERSZ_MASK (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_256B (0x0 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_64KB (0x1 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_16MB (0x2 << EPI_ADDRMAP_ERSZ_SHIFT) -# define EPI_ADDRMAP_ERSZ_512MB (0x3 << EPI_ADDRMAP_ERSZ_SHIFT) - -/* EPI Status (EPISTAT), offset 0x060 */ - -#define EPI_STAT_INITSEQ_SHIFT 6 /* Bits 6: Initialization Sequence */ -#define EPI_STAT_INITSEQ_MASK (0x1 << EPI_STAT_INITSEQ_SHIFT) - -/* EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 */ - -#define EPI_SDRAMCFG_SIZE_SHIFT 0 /* Bits 1-0: Size of SDRAM */ -#define EPI_SDRAMCFG_SIZE_MASK (3 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_8MB (0x0 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_16MB (0x1 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_32MB (0x2 << EPI_SDRAMCFG_SIZE_SHIFT) -# define EPI_SDRAMCFG_SIZE_64MB (0x3 << EPI_SDRAMCFG_SIZE_SHIFT) -#define EPI_SDRAMCFG_RFSH_SHIFT 16 /* Bits 26-16: Refresh Counter */ -#define EPI_SDRAMCFG_RFSH_MASK (0x7FF << EPI_SDRAMCFG_RFSH_SHIFT) -# define EPI_SDRAMCFG_RFSH(n) ((n) << EPI_SDRAMCFG_RFSH_SHIFT) -#define EPI_SDRAMCFG_FREQ_SHIFT 30 /* EPI Frequency Range */ -#define EPI_SDRAMCFG_FREQ_MASK (3 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_0_15MHZ (0x0 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_15_30MHZ (0x1 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_30_50MHZ (0x2 << EPI_SDRAMCFG_FREQ_SHIFT) -# define EPI_SDRAMCFG_FREQ_50_100MHZ (0x3 << EPI_SDRAMCFG_FREQ_SHIFT) - -/* EPI Main Baud Rate (EPIBAUD), offset 0x004 */ - -#define EPI_BAUD_COUNT0_SHIFT 0 -#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT) -# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h b/nuttx/arch/arm/src/lm/chip/lm_ethernet.h deleted file mode 100644 index 02908d222..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_ethernet.h +++ /dev/null @@ -1,203 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_ethernet.h - * - * Copyright (C) 2009-2010, 2012-2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> -#include <nuttx/net/mii.h> - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Ethernet Controller Register Offsets *********************************************/ - -/* Ethernet MAC Register Offsets */ - -#define LM_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */ -#define LM_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */ -#define LM_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */ -#define LM_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */ -#define LM_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */ -#define LM_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */ -#define LM_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */ -#define LM_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */ -#define LM_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */ -#define LM_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */ -#define LM_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */ -#define LM_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */ -#define LM_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ -#define LM_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ -#define LM_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ -#ifdef LM_ETHTS -# define LM_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ -#endif - -/* MII Management Register Offsets (see include/nuttx/net/mii.h) */ - -/* Ethernet Controller Register Addresses *******************************************/ - -#define LM_MAC_RIS (LM_ETHCON_BASE + LM_MAC_RIS_OFFSET) -#define LM_MAC_IACK (LM_ETHCON_BASE + LM_MAC_IACK_OFFSET) -#define LM_MAC_IM (LM_ETHCON_BASE + LM_MAC_IM_OFFSET) -#define LM_MAC_RCTL (LM_ETHCON_BASE + LM_MAC_RCTL_OFFSET) -#define LM_MAC_TCTL (LM_ETHCON_BASE + LM_MAC_TCTL_OFFSET) -#define LM_MAC_DATA (LM_ETHCON_BASE + LM_MAC_DATA_OFFSET) -#define LM_MAC_IA0 (LM_ETHCON_BASE + LM_MAC_IA0_OFFSET) -#define LM_MAC_IA1 (LM_ETHCON_BASE + LM_MAC_IA1_OFFSET) -#define LM_MAC_THR (LM_ETHCON_BASE + LM_MAC_THR_OFFSET) -#define LM_MAC_MCTL (LM_ETHCON_BASE + LM_MAC_MCTL_OFFSET) -#define LM_MAC_MDV (LM_ETHCON_BASE + LM_MAC_MDV_OFFSET) -#define LM_MAC_MTXD (LM_ETHCON_BASE + LM_MAC_MTXD_OFFSET) -#define LM_MAC_MRXD (LM_ETHCON_BASE + LM_MAC_MRXD_OFFSET) -#define LM_MAC_NP (LM_ETHCON_BASE + LM_MAC_NP_OFFSET) -#define LM_MAC_TR (LM_ETHCON_BASE + LM_MAC_TR_OFFSET) -#ifdef LM_ETHTS -# define LM_MAC_TS (LM_ETHCON_BASE + LM_MAC_TS_OFFSET) -#endif - -/* Memory Mapped MII Management Registers */ - -#define MAC_MII_MCR (LM_ETHCON_BASE + MII_MCR) -#define MAC_MII_MSR (LM_ETHCON_BASE + MII_MSR) -#define MAC_MII_PHYID1 (LM_ETHCON_BASE + MII_PHYID1) -#define MAC_MII_PHYID2 (LM_ETHCON_BASE + MII_PHYID2) -#define MAC_MII_ADVERTISE (LM_ETHCON_BASE + MII_ADVERTISE) -#define MAC_MII_LPA (LM_ETHCON_BASE + MII_LPA) -#define MAC_MII_EXPANSION (LM_ETHCON_BASE + MII_EXPANSION) -#define MAC_MII_VSPECIFIC (LM_ETHCON_BASE + MII_LM_VSPECIFIC) -#define MAC_MII_INTCS (LM_ETHCON_BASE + MII_LM_INTCS) -#define MAC_MII_DIAGNOSTIC (LM_ETHCON_BASE + MII_LM_DIAGNOSTIC) -#define MAC_MII_XCVRCONTROL (LM_ETHCON_BASE + MII_LM_XCVRCONTROL) -#define MAC_MII_LEDCONFIG (LM_ETHCON_BASE + MII_LM_LEDCONFIG) -#define MAC_MII_MDICONTROL (LM_ETHCON_BASE + MII_LM_MDICONTROL) - -/* Ethernet Controller Register Bit Definitions *************************************/ - -/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ - -#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ -#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ -#define MAC_RIS_TXEMP (1 << 2) /* Bit 2: Transmit FIFO Empty */ -#define MAC_RIS_FOV (1 << 3) /* Bit 3: FIFO Overrun */ -#define MAC_RIS_RXER (1 << 4) /* Bit 4: Receive Error */ -#define MAC_RIS_MDINT (1 << 5) /* Bit 5: MII Transaction Complete */ -#define MAC_RIS_PHYINT (1 << 6) /* Bit 6: PHY Interrupt */ - -#define MAC_IACK_RXINT (1 << 0) /* Bit 0: Clear Packet Received */ -#define MAC_IACK_TXER (1 << 1) /* Bit 1: Clear Transmit Error */ -#define MAC_IACK_TXEMP (1 << 2) /* Bit 2: Clear Transmit FIFO Empty */ -#define MAC_IACK_FOV (1 << 3) /* Bit 3: Clear FIFO Overrun */ -#define MAC_IACK_RXER (1 << 4) /* Bit 4: Clear Receive Error */ -#define MAC_IACK_MDINT (1 << 5) /* Bit 5: Clear MII Transaction Complete */ -#define MAC_IACK_PHYINT (1 << 6) /* Bit 6: Clear PHY Interrupt */ - -/* Ethernet MAC Interrupt Mask (MACIM), offset 0x004 */ - -#define MAC_IM_RXINTM (1 << 0) /* Bit 0: Mask Packet Received */ -#define MAC_IM_TXERM (1 << 1) /* Bit 1: Mask Transmit Error */ -#define MAC_IM_TXEMPM (1 << 2) /* Bit 2: Mask Transmit FIFO Empty */ -#define MAC_IM_FOVM (1 << 3) /* Bit 3: Mask FIFO Overrun */ -#define MAC_IM_RXERM (1 << 4) /* Bit 4: Mask Receive Error */ -#define MAC_IM_MDINTM (1 << 5) /* Bit 5: Mask MII Transaction Complete */ -#define MAC_IM_PHYINTM (1 << 6) /* Bit 6: Mask PHY Interrupt */ -#define MAC_IM_ALLINTS 0x7f - -/* Ethernet MAC Receive Control (MACRCTL), offset 0x008 */ - -#define MAC_RCTL_RXEN (1 << 0) /* Bit 0: Enable Receiver */ -#define MAC_RCTL_AMUL (1 << 1) /* Bit 1: Enable Multicast Frames */ -#define MAC_RCTL_PRMS (1 << 2) /* Bit 2: Enable Promiscuous Mode */ -#define MAC_RCTL_BADCRC (1 << 3) /* Bit 3: Enable Reject Bad CRC */ -#define MAC_RCTL_RSTFIFO (1 << 4) /* Bit 4: Clear Receive FIFO */ - -/* Ethernet MAC Transmit Control (MACTCTL), offset 0x00c */ - -#define MAC_TCTL_TXEN (1 << 0) /* Bit 0: Enable Transmitter */ -#define MAC_TCTL_PADEN (1 << 1) /* Bit 1: Enable Packet Padding */ -#define MAC_TCTL_CRC (1 << 2) /* Bit 2: Enable CRC Generation */ -#define MAC_TCTL_DUPLEX (1 << 4) /* Bit 4: Enable Duplex Mode */ - -/* Ethernet MAC Threshold (MACTHR), offset 0x01c */ - -#define MAC_THR_MASK 0x3f /* Bits 5-0: Threshold Value */ - -/* Ethernet MAC Management Control (MACMCTL), offset 0x020 */ - -#define MAC_MCTL_START (1 << 0) /* Bit 0: MII Register Transaction Enable */ -#define MAC_MCTL_WRITE (1 << 1) /* Bit 1: MII Register Transaction Type */ -#define MAC_MCTL_REGADR_SHIFT 3 /* Bits 7-3: MII Register Address */ -#define MAC_MCTL_REGADR_MASK (0x1f << MAC_MCTL_REGADR_SHIFT) - -/* Ethernet MAC Management Divider (MACMDV), offset 0x024 */ - -#define MAC_MDV_MASK 0xff /* Bits 7-0: Clock Divider */ - -/* Ethernet MAC Management Transmit Data (MACTXD), offset 0x02c */ - -#define MAC_MTXD_MASK 0xffff /* Bits 15-0: MII Register Transmit Data */ - -/* Ethernet MAC Management Receive Data (MACRXD), offset 0x030 */ - -#define MAC_MTRD_MASK 0xffff /* Bits 15-0: MII Register Receive Data */ - -/* Ethernet MAC Number of Packets (MACNP), offset 0x034 */ - -#define MAC_NP_MASK 0x3f /* Bits 5-0: Number of Packets in Receive FIFO */ - -/* Ethernet MAC Transmission Request (MACTR), offset 0x038 */ - -#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_flash.h b/nuttx/arch/arm/src/lm/chip/lm_flash.h deleted file mode 100644 index 45b5154bb..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_flash.h +++ /dev/null @@ -1,157 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_flash.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* FLASH dimensions ****************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) -# define LM_FLASH_NPAGES 256 -# define LM_FLASH_PAGESIZE 1024 -#else -# error "No flash dimensions defined for selected chip." -#endif - -#define LM_FLASH_SIZE (LM_FLASH_NPAGES * LM_FLASH_PAGESIZE) - - -/* FLASH register offsets ***********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM_FLASHCON_BASE. - */ - -#define LM_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ -#define LM_FLASH_FMD_OFFSET 0x004 /* Flash memory data */ -#define LM_FLASH_FMC_OFFSET 0x008 /* Flash memory control */ -#define LM_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */ -#define LM_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ -#define LM_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM_SYSCON_BASE - */ - -#define LM_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ -#define LM_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */ -#define LM_FLASH_USECRL_OFFSET 0x140 /* USec Reload */ -#define LM_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */ -#define LM_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */ -#define LM_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */ -#define LM_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */ -#define LM_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */ -#define LM_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */ -#define LM_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */ -#define LM_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */ -#define LM_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */ -#define LM_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ -#define LM_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ - -/* FLASH register addresses *********************************************************/ - -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of LM_FLASHCON_BASE. - */ - -#define LM_FLASH_FMA (LM_FLASHCON_BASE + LM_FLASH_FMA_OFFSET) -#define LM_FLASH_FMD (LM_FLASHCON_BASE + LM_FLASH_FMD_OFFSET) -#define LM_FLASH_FMC (LM_FLASHCON_BASE + LM_FLASH_FMC_OFFSET) -#define LM_FLASH_FCRIS (LM_FLASHCON_BASE + LM_FLASH_FCRIS_OFFSET) -#define LM_FLASH_FCIM (LM_FLASHCON_BASE + LM_FLASH_FCIM_OFFSET) -#define LM_FLASH_FCMISC (LM_FLASHCON_BASE + LM_FLASH_FCMISC_OFFSET) - -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of LM_SYSCON_BASE - */ - -#define LM_FLASH_FMPRE (LM_SYSCON_BASE + LM_FLASH_FMPRE_OFFSET) -#define LM_FLASH_FMPPE (LM_SYSCON_BASE + LM_FLASH_FMPPE_OFFSET) -#define LM_FLASH_USECRL (LM_SYSCON_BASE + LM_FLASH_USECRL_OFFSET) -#define LM_FLASH_USERDBG (LM_SYSCON_BASE + LM_FLASH_USERDBG_OFFSET) -#define LM_FLASH_USERREG0 (LM_SYSCON_BASE + LM_FLASH_USERREG0_OFFSET) -#define LM_FLASH_USERREG1 (LM_SYSCON_BASE + LM_FLASH_USERREG1_OFFSET) -#define LM_FLASH_FMPRE0 (LM_SYSCON_BASE + LM_FLASH_FMPRE0_OFFSET) -#define LM_FLASH_FMPRE1 (LM_SYSCON_BASE + LM_FLASH_FMPRE1_OFFSET) -#define LM_FLASH_FMPRE2 (LM_SYSCON_BASE + LM_FLASH_FMPRE2_OFFSET) -#define LM_FLASH_FMPRE3 (LM_SYSCON_BASE + LM_FLASH_FMPRE3_OFFSET) -#define LM_FLASH_FMPPE0 (LM_SYSCON_BASE + LM_FLASH_FMPPE0_OFFSET) -#define LM_FLASH_FMPPE1 (LM_SYSCON_BASE + LM_FLASH_FMPPE1_OFFSET) -#define LM_FLASH_FMPPE2 (LM_SYSCON_BASE + LM_FLASH_FMPPE2_OFFSET) -#define LM_FLASH_FMPPE3 (LM_SYSCON_BASE + LM_FLASH_FMPPE3_OFFSET) - -/* FLASH register bit defitiions ****************************************************/ - -#define FLASH_FMA_OFFSET_SHIFT 0 /* Bits 17-0: Address Offset */ -#define FLASH_FMA_OFFSET_MASK (0x0003ffff << FLASH_FMA_OFFSET_SHIFT) - -#define FLASH_FMC_WRITE (1 << 0) /* Write a Word into Flash Memory */ -#define FLASH_FMC_ERASE (1 << 1) /* Erase a Page of Flash Memory */ -#define FLASH_FMC_MERASE (1 << 2) /* Mass Erase Flash Memory */ -#define FLASH_FMC_COMT (1 << 3) /* Commit Register Value */ - -/* This field contains a write key, which is used to minimize the incidence - * of accidental flash writes. The value 0xA442 must be written into this - * field for a write to occur. Writes to the FMC register without this WRKEY - * value are ignored. A read of this field returns the value 0 - */ -#define FLASH_FMC_WRKEY_SHIFT 16 /* Bits 16-31: Flash Write Key */ -#define FLASH_FMC_WRKEY_MASK (0xffff << FLASH_FMC_WRKEY_SHIFT) -#define FLASH_FMC_WRKEY (0xa442 << FLASH_FMC_WRKEY_SHIFT) /* Magic write key */ - - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_gpio.h b/nuttx/arch/arm/src/lm/chip/lm_gpio.h deleted file mode 100644 index 3fdf5086f..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_gpio.h +++ /dev/null @@ -1,520 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_gpio.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt <gnutt@nuttx.org> - * Jose Pablo Carballo <jcarballo@nx-engineering.com> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* GPIO Register Offsets ************************************************************/ - -#define LM_GPIO_DATA_OFFSET 0x000 /* GPIO Data */ -#define LM_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */ -#define LM_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */ -#define LM_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */ -#define LM_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */ -#define LM_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */ -#define LM_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */ -#define LM_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */ -#define LM_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */ -#define LM_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */ -#define LM_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */ -#define LM_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */ -#define LM_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */ -#define LM_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */ -#define LM_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */ -#define LM_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */ -#define LM_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */ -#define LM_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */ -#define LM_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */ -#define LM_GPIO_CR_OFFSET 0x524 /* GPIO Commit */ - -#ifdef LM4F -# define LM_GPIO_AMSEL_OFFSET 0x528 /* GPIO Analog Mode Select */ -# define LM_GPIO_PCTL_OFFSET 0x52c /* GPIO Port Control */ -# define LM_GPIO_ADCCTL_OFFSET 0x530 /* GPIO ADC Control */ -# define LM_GPIO_DMACTL_OFFSET 0x534 /* GPIO DMA Control */ -#endif - -#define LM_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */ -#define LM_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */ -#define LM_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */ -#define LM_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */ -#define LM_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */ -#define LM_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */ -#define LM_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */ -#define LM_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */ -#define LM_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */ -#define LM_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */ -#define LM_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */ -#define LM_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/ - -/* GPIO Register Addresses **********************************************************/ - -#if LM_NPORTS > 0 - -# define LM_GPIOA_DATA (LM_GPIOA_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOA_DIR (LM_GPIOA_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOA_IS (LM_GPIOA_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOA_IBE (LM_GPIOA_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOA_IEV (LM_GPIOA_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOA_IM (LM_GPIOA_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOA_RIS (LM_GPIOA_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOA_MIS (LM_GPIOA_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOA_ICR (LM_GPIOA_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOA_AFSEL (LM_GPIOA_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOA_DR2R (LM_GPIOA_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOA_DR4R (LM_GPIOA_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOA_DR8R (LM_GPIOA_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOA_ODR (LM_GPIOA_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOA_PUR (LM_GPIOA_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOA_PDR (LM_GPIOA_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOA_SLR (LM_GPIOA_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOA_DEN (LM_GPIOA_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOA_LOCK (LM_GPIOA_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOA_CR (LM_GPIOA_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOA_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOA_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOA_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOA_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOA_PERIPHID4 (LM_GPIOA_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOA_PERIPHID5 (LM_GPIOA_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOA_PERIPHID6 (LM_GPIOA_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOA_PERIPHID7 (LM_GPIOA_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOA_PERIPHID0 (LM_GPIOA_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOA_PERIPHID1 (LM_GPIOA_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOA_PERIPHID2 (LM_GPIOA_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOA_PERIPHID3 (LM_GPIOA_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOA_PCELLID0 (LM_GPIOA_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOA_PCELLID1 (LM_GPIOA_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOA_PCELLID2 (LM_GPIOA_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOA_PCELLID3 (LM_GPIOA_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 1 - -# define LM_GPIOB_DATA (LM_GPIOB_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOB_DIR (LM_GPIOB_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOB_IS (LM_GPIOB_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOB_IBE (LM_GPIOB_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOB_IEV (LM_GPIOB_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOB_IM (LM_GPIOB_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOB_RIS (LM_GPIOB_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOB_MIS (LM_GPIOB_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOB_ICR (LM_GPIOB_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOB_AFSEL (LM_GPIOB_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOB_DR2R (LM_GPIOB_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOB_DR4R (LM_GPIOB_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOB_DR8R (LM_GPIOB_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOB_ODR (LM_GPIOB_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOB_PUR (LM_GPIOB_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOB_PDR (LM_GPIOB_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOB_SLR (LM_GPIOB_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOB_DEN (LM_GPIOB_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOB_LOCK (LM_GPIOB_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOB_CR (LM_GPIOB_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOB_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOB_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOB_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOB_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOB_PERIPHID4 (LM_GPIOB_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOB_PERIPHID5 (LM_GPIOB_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOB_PERIPHID6 (LM_GPIOB_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOB_PERIPHID7 (LM_GPIOB_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOB_PERIPHID0 (LM_GPIOB_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOB_PERIPHID1 (LM_GPIOB_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOB_PERIPHID2 (LM_GPIOB_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOB_PERIPHID3 (LM_GPIOB_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOB_PCELLID0 (LM_GPIOB_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOB_PCELLID1 (LM_GPIOB_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOB_PCELLID2 (LM_GPIOB_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOB_PCELLID3 (LM_GPIOB_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 2 - -# define LM_GPIOC_DATA (LM_GPIOC_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOC_DIR (LM_GPIOC_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOC_IS (LM_GPIOC_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOC_IBE (LM_GPIOC_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOC_IEV (LM_GPIOC_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOC_IM (LM_GPIOC_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOC_RIS (LM_GPIOC_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOC_MIS (LM_GPIOC_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOC_ICR (LM_GPIOC_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOC_AFSEL (LM_GPIOC_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOC_DR2R (LM_GPIOC_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOC_DR4R (LM_GPIOC_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOC_DR8R (LM_GPIOC_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOC_ODR (LM_GPIOC_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOC_PUR (LM_GPIOC_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOC_PDR (LM_GPIOC_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOC_SLR (LM_GPIOC_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOC_DEN (LM_GPIOC_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOC_LOCK (LM_GPIOC_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOC_CR (LM_GPIOC_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOC_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOC_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOC_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOC_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOC_PERIPHID4 (LM_GPIOC_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOC_PERIPHID5 (LM_GPIOC_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOC_PERIPHID6 (LM_GPIOC_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOC_PERIPHID7 (LM_GPIOC_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOC_PERIPHID0 (LM_GPIOC_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOC_PERIPHID1 (LM_GPIOC_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOC_PERIPHID2 (LM_GPIOC_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOC_PERIPHID3 (LM_GPIOC_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOC_PCELLID0 (LM_GPIOC_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOC_PCELLID1 (LM_GPIOC_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOC_PCELLID2 (LM_GPIOC_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOC_PCELLID3 (LM_GPIOC_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 3 - -# define LM_GPIOD_DATA (LM_GPIOD_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOD_DIR (LM_GPIOD_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOD_IS (LM_GPIOD_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOD_IBE (LM_GPIOD_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOD_IEV (LM_GPIOD_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOD_IM (LM_GPIOD_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOD_RIS (LM_GPIOD_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOD_MIS (LM_GPIOD_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOD_ICR (LM_GPIOD_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOD_AFSEL (LM_GPIOD_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOD_DR2R (LM_GPIOD_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOD_DR4R (LM_GPIOD_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOD_DR8R (LM_GPIOD_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOD_ODR (LM_GPIOD_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOD_PUR (LM_GPIOD_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOD_PDR (LM_GPIOD_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOD_SLR (LM_GPIOD_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOD_DEN (LM_GPIOD_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOD_LOCK (LM_GPIOD_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOD_CR (LM_GPIOD_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOD_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOD_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOD_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOD_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOD_PERIPHID4 (LM_GPIOD_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOD_PERIPHID5 (LM_GPIOD_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOD_PERIPHID6 (LM_GPIOD_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOD_PERIPHID7 (LM_GPIOD_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOD_PERIPHID0 (LM_GPIOD_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOD_PERIPHID1 (LM_GPIOD_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOD_PERIPHID2 (LM_GPIOD_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOD_PERIPHID3 (LM_GPIOD_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOD_PCELLID0 (LM_GPIOD_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOD_PCELLID1 (LM_GPIOD_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOD_PCELLID2 (LM_GPIOD_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOD_PCELLID3 (LM_GPIOD_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 4 - -# define LM_GPIOE_DATA (LM_GPIOE_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOE_DIR (LM_GPIOE_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOE_IS (LM_GPIOE_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOE_IBE (LM_GPIOE_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOE_IEV (LM_GPIOE_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOE_IM (LM_GPIOE_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOE_RIS (LM_GPIOE_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOE_MIS (LM_GPIOE_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOE_ICR (LM_GPIOE_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOE_AFSEL (LM_GPIOE_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOE_DR2R (LM_GPIOE_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOE_DR4R (LM_GPIOE_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOE_DR8R (LM_GPIOE_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOE_ODR (LM_GPIOE_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOE_PUR (LM_GPIOE_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOE_PDR (LM_GPIOE_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOE_SLR (LM_GPIOE_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOE_DEN (LM_GPIOE_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOE_LOCK (LM_GPIOE_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOE_CR (LM_GPIOE_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOE_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOE_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOE_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOE_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOE_PERIPHID4 (LM_GPIOE_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOE_PERIPHID5 (LM_GPIOE_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOE_PERIPHID6 (LM_GPIOE_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOE_PERIPHID7 (LM_GPIOE_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOE_PERIPHID0 (LM_GPIOE_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOE_PERIPHID1 (LM_GPIOE_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOE_PERIPHID2 (LM_GPIOE_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOE_PERIPHID3 (LM_GPIOE_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOE_PCELLID0 (LM_GPIOE_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOE_PCELLID1 (LM_GPIOE_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOE_PCELLID2 (LM_GPIOE_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOE_PCELLID3 (LM_GPIOE_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 5 - -# define LM_GPIOF_DATA (LM_GPIOF_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOF_DIR (LM_GPIOF_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOF_IS (LM_GPIOF_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOF_IBE (LM_GPIOF_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOF_IEV (LM_GPIOF_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOF_IM (LM_GPIOF_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOF_RIS (LM_GPIOF_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOF_MIS (LM_GPIOF_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOF_ICR (LM_GPIOF_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOF_AFSEL (LM_GPIOF_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOF_DR2R (LM_GPIOF_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOF_DR4R (LM_GPIOF_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOF_DR8R (LM_GPIOF_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOF_ODR (LM_GPIOF_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOF_PUR (LM_GPIOF_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOF_PDR (LM_GPIOF_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOF_SLR (LM_GPIOF_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOF_DEN (LM_GPIOF_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOF_LOCK (LM_GPIOF_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOF_CR (LM_GPIOF_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOF_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOF_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOF_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOF_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOF_PERIPHID4 (LM_GPIOF_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOF_PERIPHID5 (LM_GPIOF_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOF_PERIPHID6 (LM_GPIOF_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOF_PERIPHID7 (LM_GPIOF_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOF_PERIPHID0 (LM_GPIOF_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOF_PERIPHID1 (LM_GPIOF_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOF_PERIPHID2 (LM_GPIOF_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOF_PERIPHID3 (LM_GPIOF_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOF_PCELLID0 (LM_GPIOF_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOF_PCELLID1 (LM_GPIOF_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOF_PCELLID2 (LM_GPIOF_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOF_PCELLID3 (LM_GPIOF_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 6 - -# define LM_GPIOG_DATA (LM_GPIOG_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOG_DIR (LM_GPIOG_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOG_IS (LM_GPIOG_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOG_IBE (LM_GPIOG_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOG_IEV (LM_GPIOG_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOG_IM (LM_GPIOG_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOG_RIS (LM_GPIOG_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOG_MIS (LM_GPIOG_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOG_ICR (LM_GPIOG_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOG_AFSEL (LM_GPIOG_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOG_DR2R (LM_GPIOG_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOG_DR4R (LM_GPIOG_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOG_DR8R (LM_GPIOG_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOG_ODR (LM_GPIOG_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOG_PUR (LM_GPIOG_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOG_PDR (LM_GPIOG_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOG_SLR (LM_GPIOG_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOG_DEN (LM_GPIOG_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOG_LOCK (LM_GPIOG_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOG_CR (LM_GPIOG_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOG_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOG_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOG_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOG_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOG_PERIPHID4 (LM_GPIOG_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOG_PERIPHID5 (LM_GPIOG_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOG_PERIPHID6 (LM_GPIOG_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOG_PERIPHID7 (LM_GPIOG_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOG_PERIPHID0 (LM_GPIOG_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOG_PERIPHID1 (LM_GPIOG_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOG_PERIPHID2 (LM_GPIOG_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOG_PERIPHID3 (LM_GPIOG_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOG_PCELLID0 (LM_GPIOG_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOG_PCELLID1 (LM_GPIOG_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOG_PCELLID2 (LM_GPIOG_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOG_PCELLID3 (LM_GPIOG_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 7 - -# define LM_GPIOH_DATA (LM_GPIOH_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOH_DIR (LM_GPIOH_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOH_IS (LM_GPIOH_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOH_IBE (LM_GPIOH_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOH_IEV (LM_GPIOH_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOH_IM (LM_GPIOH_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOH_RIS (LM_GPIOH_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOH_MIS (LM_GPIOH_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOH_ICR (LM_GPIOH_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOH_AFSEL (LM_GPIOH_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOH_DR2R (LM_GPIOH_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOH_DR4R (LM_GPIOH_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOH_DR8R (LM_GPIOH_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOH_ODR (LM_GPIOH_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOH_PUR (LM_GPIOH_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOH_PDR (LM_GPIOH_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOH_SLR (LM_GPIOH_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOH_DEN (LM_GPIOH_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOH_LOCK (LM_GPIOH_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOH_CR (LM_GPIOH_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOH_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOH_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOH_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOH_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOH_PERIPHID4 (LM_GPIOH_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOH_PERIPHID5 (LM_GPIOH_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOH_PERIPHID6 (LM_GPIOH_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOH_PERIPHID7 (LM_GPIOH_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOH_PERIPHID0 (LM_GPIOH_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOH_PERIPHID1 (LM_GPIOH_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOH_PERIPHID2 (LM_GPIOH_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOH_PERIPHID3 (LM_GPIOH_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOH_PCELLID0 (LM_GPIOH_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOH_PCELLID1 (LM_GPIOH_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOH_PCELLID2 (LM_GPIOH_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOH_PCELLID3 (LM_GPIOH_BASE + LM_GPIO_PCELLID3_OFFSET) - -#elif LM_NPORTS > 8 - -# define LM_GPIOJ_DATA (LM_GPIOJ_BASE + LM_GPIO_DATA_OFFSET) -# define LM_GPIOJ_DIR (LM_GPIOJ_BASE + LM_GPIO_DIR_OFFSET) -# define LM_GPIOJ_IS (LM_GPIOJ_BASE + LM_GPIO_IS_OFFSET) -# define LM_GPIOJ_IBE (LM_GPIOJ_BASE + LM_GPIO_IBE_OFFSET) -# define LM_GPIOJ_IEV (LM_GPIOJ_BASE + LM_GPIO_IEV_OFFSET) -# define LM_GPIOJ_IM (LM_GPIOJ_BASE + LM_GPIO_IM_OFFSET) -# define LM_GPIOJ_RIS (LM_GPIOJ_BASE + LM_GPIO_RIS_OFFSET) -# define LM_GPIOJ_MIS (LM_GPIOJ_BASE + LM_GPIO_MIS_OFFSET) -# define LM_GPIOJ_ICR (LM_GPIOJ_BASE + LM_GPIO_ICR_OFFSET) -# define LM_GPIOJ_AFSEL (LM_GPIOJ_BASE + LM_GPIO_AFSEL_OFFSET) -# define LM_GPIOJ_DR2R (LM_GPIOJ_BASE + LM_GPIO_DR2R_OFFSET) -# define LM_GPIOJ_DR4R (LM_GPIOJ_BASE + LM_GPIO_DR4R_OFFSET) -# define LM_GPIOJ_DR8R (LM_GPIOJ_BASE + LM_GPIO_DR8R_OFFSET) -# define LM_GPIOJ_ODR (LM_GPIOJ_BASE + LM_GPIO_ODR_OFFSET) -# define LM_GPIOJ_PUR (LM_GPIOJ_BASE + LM_GPIO_PUR_OFFSET) -# define LM_GPIOJ_PDR (LM_GPIOJ_BASE + LM_GPIO_PDR_OFFSET) -# define LM_GPIOJ_SLR (LM_GPIOJ_BASE + LM_GPIO_SLR_OFFSET) -# define LM_GPIOJ_DEN (LM_GPIOJ_BASE + LM_GPIO_DEN_OFFSET) -# define LM_GPIOJ_LOCK (LM_GPIOJ_BASE + LM_GPIO_LOCK_OFFSET) -# define LM_GPIOJ_CR (LM_GPIOJ_BASE + LM_GPIO_CR_OFFSET) - -# ifdef LM4F -# define LM_GPIOJ_AMSEL (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET) -# define LM_GPIOJ_PCTL (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET) -# define LM_GPIOJ_ADCCTL (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET) -# define LM_GPIOJ_DMACTL (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET) -# endif - -# define LM_GPIOJ_PERIPHID4 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID4_OFFSET) -# define LM_GPIOJ_PERIPHID5 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID5_OFFSET) -# define LM_GPIOJ_PERIPHID6 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID6_OFFSET) -# define LM_GPIOJ_PERIPHID7 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID7_OFFSET) -# define LM_GPIOJ_PERIPHID0 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID0_OFFSET) -# define LM_GPIOJ_PERIPHID1 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID1_OFFSET) -# define LM_GPIOJ_PERIPHID2 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID2_OFFSET) -# define LM_GPIOJ_PERIPHID3 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID3_OFFSET) -# define LM_GPIOJ_PCELLID0 (LM_GPIOJ_BASE + LM_GPIO_PCELLID0_OFFSET) -# define LM_GPIOJ_PCELLID1 (LM_GPIOJ_BASE + LM_GPIO_PCELLID1_OFFSET) -# define LM_GPIOJ_PCELLID2 (LM_GPIOJ_BASE + LM_GPIO_PCELLID2_OFFSET) -# define LM_GPIOJ_PCELLID3 (LM_GPIOJ_BASE + LM_GPIO_PCELLID3_OFFSET) - -#endif /* LM_NPORTS */ - -/* GPIO Register Bitfield Definitions ***********************************************/ - -#ifdef LM4F -# define GPIO_PCTL_PMC_SHIFT(n) ((n) << 2) -# define GPIO_PCTL_PMC_MASK(n) (15 << GPIO_PCTL_PMC_SHIFT(n)) - -# define GPIO_PCTL_PMC0_SHIFT (0) /* Bits 0-3: Port Mux Control 0 */ -# define GPIO_PCTL_PMC0_MASK (15 << GPIO_PCTL_PMC0_SHIFT) -# define GPIO_PCTL_PMC1_SHIFT (4) /* Bits 4-7: Port Mux Control 0 */ -# define GPIO_PCTL_PMC1_MASK (15 << GPIO_PCTL_PMC1_SHIFT) -# define GPIO_PCTL_PMC2_SHIFT (8) /* Bits 8-11: Port Mux Control 0 */ -# define GPIO_PCTL_PMC2_MASK (15 << GPIO_PCTL_PMC2_SHIFT) -# define GPIO_PCTL_PMC3_SHIFT (12) /* Bits 12-15: Port Mux Control 0 */ -# define GPIO_PCTL_PMC3_MASK (15 << GPIO_PCTL_PMC3_SHIFT) -# define GPIO_PCTL_PMC4_SHIFT (16) /* Bits 16-19: Port Mux Control 0 */ -# define GPIO_PCTL_PMC4_MASK (15 << GPIO_PCTL_PMC4_SHIFT) -# define GPIO_PCTL_PMC5_SHIFT (20) /* Bits 20-23: Port Mux Control 0 */ -# define GPIO_PCTL_PMC5_MASK (15 << GPIO_PCTL_PMC5_SHIFT) -# define GPIO_PCTL_PMC6_SHIFT (24) /* Bits 24-27: Port Mux Control 0 */ -# define GPIO_PCTL_PMC6_MASK (15 << GPIO_PCTL_PMC6_SHIFT) -# define GPIO_PCTL_PMC7_SHIFT (28) /* Bits 28-31: Port Mux Control 0 */ -# define GPIO_PCTL_PMC7_MASK (15 << GPIO_PCTL_PMC7_SHIFT) -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_i2c.h b/nuttx/arch/arm/src/lm/chip/lm_i2c.h deleted file mode 100644 index 88ce31b77..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_i2c.h +++ /dev/null @@ -1,247 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_i2c.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* I2C Register Offsets *************************************************************/ - -/* I2C Master */ - -#define LM_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */ -#define LM_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */ -#define LM_I2CM_DR_OFFSET 0x008 /* I2C Master Data */ -#define LM_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */ -#define LM_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */ -#define LM_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */ -#define LM_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */ -#define LM_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */ -#define LM_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */ - -/* I2C Slave */ - -#define LM_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */ -#define LM_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */ -#define LM_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */ -#define LM_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */ -#define LM_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */ -#define LM_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */ -#define LM_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */ - -/* I2C Register Addresses ***********************************************************/ - -#if LM_NI2C > 0 - -/* I2C Master */ - -#define LM_I2CM_BASE(n) (LM_I2CM0_BASE + (n)*0x1000) -#define LM_I2CM_SA(n) (LM_I2CM_BASE(n) + LM_I2CM_SA_OFFSET) -#define LM_I2CM_CS(n) (LM_I2CM_BASE(n) + LM_I2CM_CS_OFFSET) -#define LM_I2CM_DR(n) (LM_I2CM_BASE(n) + LM_I2CM_DR_OFFSET) -#define LM_I2CM_TPR(n) (LM_I2CM_BASE(n) + LM_I2CM_TPR_OFFSET) -#define LM_I2CM_IMR(n) (LM_I2CM_BASE(n) + LM_I2CM_IMR_OFFSET) -#define LM_I2CM_RIS(n) (LM_I2CM_BASE(n) + LM_I2CM_RIS_OFFSET) -#define LM_I2CM_MIS(n) (LM_I2CM_BASE(n) + LM_I2CM_MIS_OFFSET) -#define LM_I2CM_ICR(n) (LM_I2CM_BASE(n) + LM_I2CM_ICR_OFFSET) -#define LM_I2CM_CR(n) (LM_I2CM_BASE(n) + LM_I2CM_CR_OFFSET) - -/* I2C Slave */ - -#define LM_I2CS_BASE(n) (LM_I2CS0_BASE + (n)*0x1000) -#define LM_I2CS_OAR(n) (LM_I2CS_BASE(n) + LM_I2CS_OAR_OFFSET) -#define LM_I2CS_CSR(n) (LM_I2CS_BASE(n) + LM_I2CS_CSR_OFFSET) -#define LM_I2CS_DR(n) (LM_I2CS_BASE(n) + LM_I2CS_DR_OFFSET) -#define LM_I2CS_IMR(n) (LM_I2CS_BASE(n) + LM_I2CS_IMR_OFFSET) -#define LM_I2CS_RIS(n) (LM_I2CS_BASE(n) + LM_I2CS_RIS_OFFSET) -#define LM_I2CS_MIS(n) (LM_I2CS_BASE(n) + LM_I2CS_MIS_OFFSET) -#define LM_I2CS_ICR(n) (LM_I2CS_BASE(n) + LM_I2CS_ICR_OFFSET) - -/* I2C0 Master */ - -#define LM_I2CM0_SA (LM_I2CM0_BASE + LM_I2CM_SA_OFFSET) -#define LM_I2CM0_CS (LM_I2CM0_BASE + LM_I2CM_CS_OFFSET) -#define LM_I2CM0_DR (LM_I2CM0_BASE + LM_I2CM_DR_OFFSET) -#define LM_I2CM0_TPR (LM_I2CM0_BASE + LM_I2CM_TPR_OFFSET) -#define LM_I2CM0_IMR (LM_I2CM0_BASE + LM_I2CM_IMR_OFFSET) -#define LM_I2CM0_RIS (LM_I2CM0_BASE + LM_I2CM_RIS_OFFSET) -#define LM_I2CM0_MIS (LM_I2CM0_BASE + LM_I2CM_MIS_OFFSET) -#define LM_I2CM0_ICR (LM_I2CM0_BASE + LM_I2CM_ICR_OFFSET) -#define LM_I2CM0_CR (LM_I2CM0_BASE + LM_I2CM_CR_OFFSET) - -/* I2C0 Slave */ - -#define LM_I2CS0_OAR (LM_I2CS0_BASE + LM_I2CS_OAR_OFFSET) -#define LM_I2CS0_CSR (LM_I2CS0_BASE + LM_I2CS_CSR_OFFSET) -#define LM_I2CS0_DR (LM_I2CS0_BASE + LM_I2CS_DR_OFFSET) -#define LM_I2CS0_IMR (LM_I2CS0_BASE + LM_I2CS_IMR_OFFSET) -#define LM_I2CS0_RIS (LM_I2CS0_BASE + LM_I2CS_RIS_OFFSET) -#define LM_I2CS0_MIS (LM_I2CS0_BASE + LM_I2CS_MIS_OFFSET) -#define LM_I2CS0_ICR (LM_I2CS0_BASE + LM_I2CS_ICR_OFFSET) - -#if LM_NI2C > 1 - -/* I2C1 Master */ - -#define LM_I2CM1_SA (LM_I2CM1_BASE + LM_I2CM_SA_OFFSET) -#define LM_I2CM1_CS (LM_I2CM1_BASE + LM_I2CM_CS_OFFSET) -#define LM_I2CM1_DR (LM_I2CM1_BASE + LM_I2CM_DR_OFFSET) -#define LM_I2CM1_TPR (LM_I2CM1_BASE + LM_I2CM_TPR_OFFSET) -#define LM_I2CM1_IMR (LM_I2CM1_BASE + LM_I2CM_IMR_OFFSET) -#define LM_I2CM1_RIS (LM_I2CM1_BASE + LM_I2CM_RIS_OFFSET) -#define LM_I2CM1_MIS (LM_I2CM1_BASE + LM_I2CM_MIS_OFFSET) -#define LM_I2CM1_ICR (LM_I2CM1_BASE + LM_I2CM_ICR_OFFSET) -#define LM_I2CM1_CR (LM_I2CM1_BASE + LM_I2CM_CR_OFFSET) - -/* I2C1 Slave */ - -#define LM_I2CS1_OAR (LM_I2CS1_BASE + LM_I2CS_OAR_OFFSET) -#define LM_I2CS1_CSR (LM_I2CS1_BASE + LM_I2CS_CSR_OFFSET) -#define LM_I2CS1_DR (LM_I2CS1_BASE + LM_I2CS_DR_OFFSET) -#define LM_I2CS1_IMR (LM_I2CS1_BASE + LM_I2CS_IMR_OFFSET) -#define LM_I2CS1_RIS (LM_I2CS1_BASE + LM_I2CS_RIS_OFFSET) -#define LM_I2CS1_MIS (LM_I2CS1_BASE + LM_I2CS_MIS_OFFSET) -#define LM_I2CS1_ICR (LM_I2CS1_BASE + LM_I2CS_ICR_OFFSET) - -#endif -#endif - -/* I2C_Register Bit Definitions *****************************************************/ - -/* I2C Master Slave Address (I2CM_SA), offset 0x000 */ - -#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */ -#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */ -#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT) - -/* I2C Master Control/Status (I2CM_CS), offset 0x004 */ - -#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */ -#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */ -#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */ -#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */ -#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */ -#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */ -#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */ - -#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */ -#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */ -#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */ -#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */ - -/* I2C Master Data (I2CM_DR), offset 0x008 */ - -#define I2CM_DR_MASK 0xff /* Bits 7-0: Data transferred */ - -/* I2C Master Timer Period (I2CM_TPR), offset 0x00c */ - -#define I2CM_TPR_MASK 0xff /* Bits 7-0: SCL Clock Period */ - -/* I2C Master Interrupt Mask (I2CM_IMR), offset 0x010 */ - -#define I2CM_IMR_IM (1 << 0) /* Bit 0: Interrupt Mask */ - -/* I2C Master Raw Interrupt Status (I2CM_RIS), offset 0x014 */ - -#define I2CM_RIS_RIS (1 << 0) /* Bit 0: Raw Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_MIS), offset 0x018 */ - -#define I2CM_MIS_MIS (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Masked Interrupt Status (I2CM_ICR), offset 0x01c */ - -#define I2CM_ICR_IC (1 << 0) /* Bit 0: Masked Interrupt Status */ - -/* I2C Master Configuration (I2CM_CR), offset 0x020 */ - -#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */ -#define I2CM_CR_MFE (1 << 4 ) /* Bit 4: I2C Master Function Enable */ -#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */ - -/* I2C Slave Own Address (I2CS_OAR), offset 0x000 */ - -#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */ - -/* I2C Slave Control/Status (I2CS_CSR), offset 0x004 */ - -#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */ -#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */ -#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */ - -#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */ - -/* I2C Slave Data (I2CS_DR), offset 0x008 */ - -#define I2CS_DR_MASK 0xff /* Bits 7-0: Data for Transfer */ - -/* I2C Slave Interrupt Mask (I2CS_IMR), offset 0x00c */ - -#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */ - -/* I2C Slave Raw Interrupt Status (I2CS_RIS), offset 0x010 */ - -#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */ - -/* I2C Slave Masked Interrupt Status (I2CS_MIS), offset 0x014 */ - -#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */ - -/* I2C Slave Interrupt Clear (I2CS_ICR), offset 0x018 */ - -#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h b/nuttx/arch/arm/src/lm/chip/lm_memorymap.h deleted file mode 100644 index d8257fc02..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_memorymap.h +++ /dev/null @@ -1,71 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_memorymap.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/* Include the memory map file for the specific Stellaris chip */ - -#if defined(CONFIG_ARCH_CHIP_LM3S) -# include "chip/lm3s_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_LM4F) -# include "chip/lm4f_memorymap.h" -#else -# error "Unsupported Stellaris memory map" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_MEMORYMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h b/nuttx/arch/arm/src/lm/chip/lm_pinmap.h deleted file mode 100644 index 00b42e73b..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_pinmap.h +++ /dev/null @@ -1,71 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_pinmap.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/* Include the pin mapping file for the specific Stellaris chip */ - -#if defined(CONFIG_ARCH_CHIP_LM3S) -# include "chip/lm3s_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_LM4F) -# include "chip/lm4f_pinmap.h" -#else -# error "Unsupported Stellaris PIN mapping" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_PINMAP_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_ssi.h b/nuttx/arch/arm/src/lm/chip/lm_ssi.h deleted file mode 100644 index 5243bf112..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_ssi.h +++ /dev/null @@ -1,235 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_ssi.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> -#include <sys/types.h> - -#if LM_NSSI > 0 - -/************************************************************************************ - * Definitions - ************************************************************************************/ - -/* SSI register offsets *************************************************************/ - -#define LM_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ -#define LM_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ -#define LM_SSI_DR_OFFSET 0x008 /* SSI Data */ -#define LM_SSI_SR_OFFSET 0x00c /* SSI Status */ -#define LM_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */ -#define LM_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */ -#define LM_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */ -#define LM_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */ -#define LM_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ -#define LM_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ -#define LM_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ -#define LM_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */ -#define LM_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */ -#define LM_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */ -#define LM_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */ -#define LM_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */ -#define LM_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */ -#define LM_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */ -#define LM_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */ -#define LM_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */ -#define LM_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ - -/* SSI register addresses ***********************************************************/ - -#define LM_SSI0_CR0 (LM_SSI0_BASE + LM_SSI_CR0_OFFSET) -#define LM_SSI0_CR1 (LM_SSI0_BASE + LM_SSI_CR1_OFFSET) -#define LM_SSI0_DR (LM_SSI0_BASE + LM_SSI_DR_OFFSET) -#define LM_SSI0_SR (LM_SSI0_BASE + LM_SSI_SR_OFFSET) -#define LM_SSI0_CPSR (LM_SSI0_BASE + LM_SSI_CPSR_OFFSET) -#define LM_SSI0_IM (LM_SSI0_BASE + LM_SSI_IM_OFFSET) -#define LM_SSI0_RIS (LM_SSI0_BASE + LM_SSI_RIS_OFFSET) -#define LM_SSI0_MIS (LM_SSI0_BASE + LM_SSI_MIS_OFFSET) -#define LM_SSI0_ICR (LM_SSI0_BASE + LM_SSI_ICR_OFFSET) -#define LM_SSI0_PERIPHID4 (LM_SSI0_BASE + LM_SSI_PERIPHID4_OFFSET) -#define LM_SSI0_PERIPHID5 (LM_SSI0_BASE + LM_SSI_PERIPHID5_OFFSET) -#define LM_SSI0_PERIPHID6 (LM_SSI0_BASE + LM_SSI_PERIPHID6_OFFSET) -#define LM_SSI0_PERIPHID7 (LM_SSI0_BASE + LM_SSI_PERIPHID7_OFFSET) -#define LM_SSI0_PERIPHID0 (LM_SSI0_BASE + LM_SSI_PERIPHID0_OFFSET) -#define LM_SSI0_PERIPHID1 (LM_SSI0_BASE + LM_SSI_PERIPHID1_OFFSET) -#define LM_SSI0_PERIPHID2 (LM_SSI0_BASE + LM_SSI_PERIPHID2_OFFSET) -#define LM_SSI0_PERIPHID3 (LM_SSI0_BASE + LM_SSI_PERIPHID3_OFFSET) -#define LM_SSI0_PCELLID0 (LM_SSI0_BASE + LM_SSI_PCELLID0_OFFSET) -#define LM_SSI0_PCELLID1 (LM_SSI0_BASE + LM_SSI_PCELLID1_OFFSET) -#define LM_SSI0_PCELLID2 (LM_SSI0_BASE + LM_SSI_PCELLID2_OFFSET) -#define LM_SSI0_PCELLID3 (LM_SSI0_BASE + LM_SSI_PCELLID3_OFFSET) - -#if LM_NSSI > 1 -#define LM_SSI1_CR0 (LM_SSI1_BASE + LM_SSI_CR0_OFFSET) -#define LM_SSI1_CR1 (LM_SSI1_BASE + LM_SSI_CR1_OFFSET) -#define LM_SSI1_DR (LM_SSI1_BASE + LM_SSI_DR_OFFSET) -#define LM_SSI1_SR (LM_SSI1_BASE + LM_SSI_SR_OFFSET) -#define LM_SSI1_CPSR (LM_SSI1_BASE + LM_SSI_CPSR_OFFSET) -#define LM_SSI1_IM (LM_SSI1_BASE + LM_SSI_IM_OFFSET) -#define LM_SSI1_RIS (LM_SSI1_BASE + LM_SSI_RIS_OFFSET) -#define LM_SSI1_MIS (LM_SSI1_BASE + LM_SSI_MIS_OFFSET) -#define LM_SSI1_ICR (LM_SSI1_BASE + LM_SSI_ICR_OFFSET) -#define LM_SSI1_PERIPHID4 (LM_SSI1_BASE + LM_SSI_PERIPHID4_OFFSET) -#define LM_SSI1_PERIPHID5 (LM_SSI1_BASE + LM_SSI_PERIPHID5_OFFSET) -#define LM_SSI1_PERIPHID6 (LM_SSI1_BASE + LM_SSI_PERIPHID6_OFFSET) -#define LM_SSI1_PERIPHID7 (LM_SSI1_BASE + LM_SSI_PERIPHID7_OFFSET) -#define LM_SSI1_PERIPHID0 (LM_SSI1_BASE + LM_SSI_PERIPHID0_OFFSET) -#define LM_SSI1_PERIPHID1 (LM_SSI1_BASE + LM_SSI_PERIPHID1_OFFSET) -#define LM_SSI1_PERIPHID2 (LM_SSI1_BASE + LM_SSI_PERIPHID2_OFFSET) -#define LM_SSI1_PERIPHID3 (LM_SSI1_BASE + LM_SSI_PERIPHID3_OFFSET) -#define LM_SSI1_PCELLID0 (LM_SSI1_BASE + LM_SSI_PCELLID0_OFFSET) -#define LM_SSI1_PCELLID1 (LM_SSI1_BASE + LM_SSI_PCELLID1_OFFSET) -#define LM_SSI1_PCELLID2 (LM_SSI1_BASE + LM_SSI_PCELLID2_OFFSET) -#define LM_SSI1_PCELLID3 (LM_SSI1_BASE + LM_SSI_PCELLID3_OFFSET) - -#define LM_SSI_BASE(n) (LM_SSI0_BASE + (n)*0x01000) - -#define LM_SSI_CR0(n) (LM_SSI_BASE(n) + LM_SSI_CR0_OFFSET) -#define LM_SSI_CR1(n) (LM_SSI_BASE(n) + LM_SSI_CR1_OFFSET) -#define LM_SSI_DR(n) (LM_SSI_BASE(n) + LM_SSI_DR_OFFSET) -#define LM_SSI_SR(n) (LM_SSI_BASE(n) + LM_SSI_SR_OFFSET) -#define LM_SSI_CPSR(n) (LM_SSI_BASE(n) + LM_SSI_CPSR_OFFSET) -#define LM_SSI_IM(n) (LM_SSI_BASE(n) + LM_SSI_IM_OFFSET) -#define LM_SSI_RIS(n) (LM_SSI_BASE(n) + LM_SSI_RIS_OFFSET) -#define LM_SSI_MIS(n) (LM_SSI_BASE(n) + LM_SSI_MIS_OFFSET) -#define LM_SSI_ICR(n) (LM_SSI_BASE(n) + LM_SSI_ICR_OFFSET) -#define LM_SSI_PERIPHID4(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID4_OFFSET) -#define LM_SSI_PERIPHID5(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID5_OFFSET) -#define LM_SSI_PERIPHID6(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID6_OFFSET) -#define LM_SSI_PERIPHID7(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID7_OFFSET) -#define LM_SSI_PERIPHID0(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID0_OFFSET) -#define LM_SSI_PERIPHID1(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID1_OFFSET) -#define LM_SSI_PERIPHID2(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID2_OFFSET) -#define LM_SSI_PERIPHID3(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID3_OFFSET) -#define LM_SSI_PCELLID0(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID0_OFFSET) -#define LM_SSI_PCELLID1(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID1_OFFSET) -#define LM_SSI_PCELLID2(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID2_OFFSET) -#define LM_SSI_PCELLID3(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID3_OFFSET) -#endif /* LM_NSSI > 1 */ - -/* SSI register bit defitiions ******************************************************/ - -/* SSI Control 0 (SSICR0), offset 0x000 */ - -#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ -#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) -#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ -#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ -#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) -#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ -#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ -#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ -#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ -#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */ -#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */ -#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT) - -/* SSI Control 1 (SSICR1), offset 0x004 */ - -#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */ -#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */ -#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */ -#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */ - -/* SSI Data (SSIDR), offset 0x008 */ - -#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */ - -/* SSI Status (SSISR), offset 0x00c */ - -#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */ -#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */ -#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */ -#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */ -#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */ - -/* SSI Clock Prescale (SSICPSR), offset 0x010 */ - -#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */ - -/* SSI Interrupt Mask (SSIIM), offset 0x014 */ - -#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ -#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ -#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ -#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ - -/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ - -#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ -#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ -#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ -#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ - -/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ - -#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ -#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ -#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ -#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ - -/* SSI Interrupt Clear (SSIICR), offset 0x020 */ - -#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ -#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ - -/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ - -#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ - -/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ - -#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#endif /* LM_NSSI > 0 */ -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h b/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h deleted file mode 100644 index 008fa2d34..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_syscontrol.h +++ /dev/null @@ -1,72 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_syscontrol.h - * - * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> -#include <arch/lm/chip.h> - -/* Include the system control header file for the specific Stellaris chip */ - -#if defined(CONFIG_ARCH_CHIP_LM3S) -# include "chip/lm3s_syscontrol.h" -#elif defined(CONFIG_ARCH_CHIP_LM4F) -# include "chip/lm4f_syscontrol.h" -#else -# error "Unsupported Stellaris memory map" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_timer.h b/nuttx/arch/arm/src/lm/chip/lm_timer.h deleted file mode 100644 index 5ed68f13a..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_timer.h +++ /dev/null @@ -1,125 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_timer.h - * - * Copyright (C) 2012 Max Nekludov. All rights reserved. - * Author: Max Nekludov <macscomp@gmail.com> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Timer register offsets ***********************************************************/ - -#define LM_TIMER_GPTMCFG_OFFSET 0x000 -#define LM_TIMER_GPTMTAMR_OFFSET 0x004 -#define LM_TIMER_GPTMCTL_OFFSET 0x00c -#define LM_TIMER_GPTMIMR_OFFSET 0x018 -#define LM_TIMER_GPTMRIS_OFFSET 0x01c -#define LM_TIMER_GPTMICR_OFFSET 0x024 -#define LM_TIMER_GPTMTAILR_OFFSET 0x028 -#define LM_TIMER_GPTMTAR_OFFSET 0x048 - -/* SSI register addresses ***********************************************************/ - -#define LM_TIMER_BASE(n) (LM_TIMER0_BASE + (n)*0x01000) - -#define LM_TIMER_GPTMCFG(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET) -#define LM_TIMER_GPTMTAMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET) -#define LM_TIMER_GPTMCTL(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET) -#define LM_TIMER_GPTMIMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET) -#define LM_TIMER_GPTMRIS(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET) -#define LM_TIMER_GPTMICR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET) -#define LM_TIMER_GPTMTAILR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET) -#define LM_TIMER_GPTMTAR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET) - -/* SSI register bit defitiions ******************************************************/ - -/* GPTM Configuration (GPTMCFG), offset 0x000 */ - -#define TIMER_GPTMCFG_CFG_SHIFT 0 /* Bits 2-0: GPTM Configuration */ -#define TIMER_GPTM_CFG_MASK (0x07 << TIMER_GPTMCFG_CFG_SHIFT) -#define TIMER_GPTMCFG_CFG_32 (0 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit timer configuration */ -#define TIMER_GPTMCFG_CFG_RTC (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */ -#define TIMER_GPTMCFG_CFG_16 (1 << TIMER_GPTMCFG_CFG_SHIFT) /* 16-bit timer configuration */ - -/* GPTM Timer A Mode (GPTMTAMR), offset 0x004 */ - -#define TIMER_GPTMTAMR_TAMR_SHIFT 0 /* Bits 1-0: GPTM Timer A Mode */ -#define TIMER_GPTMTAMR_TAMR_MASK (0x03 << TIMER_GPTMTAMR_TAMR_SHIFT) -#define TIMER_GPTMTAMR_TAMR_ONESHOT (1 << TIMER_GPTMTAMR_TAMR_SHIFT) /* One-Shot Timer mode */ -#define TIMER_GPTMTAMR_TAMR_PERIODIC (2 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Periodic Timer mode */ -#define TIMER_GPTMTAMR_TAMR_CAPTURE (3 << TIMER_GPTMTAMR_TAMR_SHIFT) /* Capture mode */ -#define TIMER_GPTMTAMR_TACMR_SHIFT 2 /* Bits 2: GPTM Timer A Capture Mode */ -#define TIMER_GPTMTAMR_TACMR_MASK (0x01 << TIMER_GPTMTAMR_TACMR_SHIFT) -#define TIMER_GPTMTAMR_TACMR_EDGECOUNT (0 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Count mode */ -#define TIMER_GPTMTAMR_TACMR_EDGETIME (1 << TIMER_GPTMTAMR_TACMR_SHIFT) /* Edge-Time mode */ -#define TIMER_GPTMTAMR_TAAMS_SHIFT 3 /* Bits 3: GPTM Timer A Alternate Mode Select */ -#define TIMER_GPTMTAMR_TAAMS_MASK (0x01 << TIMER_GPTMTAMR_TAAMS_SHIFT) -#define TIMER_GPTMTAMR_TAAMS_CAPTURE (0 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* Capture mode is enabled */ -#define TIMER_GPTMTAMR_TAAMS_PWM (1 << TIMER_GPTMTAMR_TAAMS_SHIFT) /* PWM mode is enabled */ -#define TIMER_GPTMTAMR_TACDIR_SHIFT 4 /* Bits 4: GPTM Timer A Count Direction */ -#define TIMER_GPTMTAMR_TACDIR_MASK (0x01 << TIMER_GPTMTAMR_TACDIR_SHIFT) -#define TIMER_GPTMTAMR_TACDIR_DOWN (0 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* The timer counts down */ -#define TIMER_GPTMTAMR_TACDIR_UP (1 << TIMER_GPTMTAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */ -#define TIMER_GPTMTAMR_TAMIE_SHIFT 5 /* Bits 5: GPTM Timer A Match Interrupt Enable */ -#define TIMER_GPTMTAMR_TAMIE_MASK (0x01 << TIMER_GPTMTAMR_TAMIE_SHIFT) - -/* GPTM Control (GPTMCTL), offset 0x00C */ - -#define TIMER_GPTMCTL_TAEN_SHIFT 0 /* Bits 0: GPTM Timer A Enable */ -#define TIMER_GPTMCTL_TAEN_MASK (0x01 << TIMER_GPTMCTL_TAEN_SHIFT) -#define TIMER_GPTMCTL_TASTALL_SHIFT 1 /* Bits 1: GPTM Timer A Stall Enable */ -#define TIMER_GPTMCTL_TASTALL_MASK (0x01 << TIMER_GPTMCTL_TASTALL_SHIFT) - -/* GPTM Interrupt Mask (GPTMIMR), offset 0x018 */ - -#define TIMER_GPTMIMR_TATOIM_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Interrupt Mask */ -#define TIMER_GPTMIMR_TATOIM_MASK (0x01 << TIMER_GPTMIMR_TATOIM_SHIFT) - -/* GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C */ - -#define TIMER_GPTMRIS_TATORIS_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt */ -#define TIMER_GPTMRIS_TATORIS_MASK (0x01 << TIMER_GPTMRIS_TATORIS_SHIFT) - -/* GPTM Interrupt Clear (GPTMICR), offset 0x024 */ - -#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/ -#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT) - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_uart.h b/nuttx/arch/arm/src/lm/chip/lm_uart.h deleted file mode 100644 index 2ad065294..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_uart.h +++ /dev/null @@ -1,347 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_uart.h - * - * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_UART_H -#define __ARCH_ARM_SRC_LM_CHIP_LM_UART_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include <nuttx/config.h> - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* UART register offsets ************************************************************/ - -#define LM_UART_DR_OFFSET 0x000 /* UART Data */ -#define LM_UART_RSR_OFFSET 0x004 /* UART Receive Status */ -#define LM_UART_ECR_OFFSET 0x004 /* UART Error Clear */ -#define LM_UART_FR_OFFSET 0x018 /* UART Flag */ -#define LM_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */ -#define LM_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/ -#define LM_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */ -#define LM_UART_LCRH_OFFSET 0x02c /* UART Line Control */ -#define LM_UART_CTL_OFFSET 0x030 /* UART Control */ -#define LM_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */ -#define LM_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */ -#define LM_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */ -#define LM_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */ -#define LM_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */ -#define LM_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */ -#define LM_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */ -#define LM_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */ -#define LM_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */ -#define LM_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */ -#define LM_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */ -#define LM_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */ -#define LM_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */ -#define LM_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */ -#define LM_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */ -#define LM_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */ -#define LM_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */ - -/* UART register addresses **********************************************************/ - -#define LM_UART_BASE(n) (LM_UART0_BASE + (n)*0x01000) - -#define LM_UART_DR(n) (LM_UART_BASE(n) + LM_UART_DR_OFFSET) -#define LM_UART_RSR(n) (LM_UART_BASE(n) + LM_UART_RSR_OFFSET) -#define LM_UART_ECR(n) (LM_UART_BASE(n) + LM_UART_ECR_OFFSET) -#define LM_UART_FR(n) (LM_UART_BASE(n) + LM_UART_FR_OFFSET) -#define LM_UART_ILPR(n) (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET) -#define LM_UART_IBRD(n) (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET) -#define LM_UART_FBRD(n) (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET) -#define LM_UART_LCRH(n) (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET) -#define LM_UART_CTL(n) (LM_UART_BASE(n) + LM_UART_CTL_OFFSET) -#define LM_UART_IFLS(n) (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET) -#define LM_UART_IM(n) (LM_UART_BASE(n) + LM_UART_IM_OFFSET) -#define LM_UART_RIS(n) (LM_UART_BASE(n) + LM_UART_RIS_OFFSET) -#define LM_UART_MIS(n) (LM_UART_BASE(n) + LM_UART_MIS_OFFSET) -#define LM_UART_ICR(n) (LM_UART_BASE(n) + LM_UART_ICR_OFFSET) -#define LM_UART_PERIPHID4(n) (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET) -#define LM_UART_PERIPHID5(n) (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET) -#define LM_UART_PERIPHID6(n) (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET) -#define LM_UART_PERIPHID7(n) (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET) -#define LM_UART_PERIPHID0(n) (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET) -#define LM_UART_PERIPHID1(n) (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET) -#define LM_UART_PERIPHID2(n) (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET) -#define LM_UART_PERIPHID3(n) (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET) -#define LM_UART_PCELLID0(n) (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET) -#define LM_UART_PCELLID1(n) (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET) -#define LM_UART_PCELLID2(n) (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET) -#define LM_UART_PCELLID3(n) (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET) - -#define LM_UART0_DR (LM_UART0_BASE + LM_UART_TDR_OFFSET) -#define LM_UART0_RSR (LM_UART0_BASE + LM_UART_RSR_OFFSET) -#define LM_UART0_ECR (LM_UART0_BASE + LM_UART_ECR_OFFSET) -#define LM_UART0_FR (LM_UART0_BASE + LM_UART_FR_OFFSET) -#define LM_UART0_ILPR (LM_UART0_BASE + LM_UART_ILPR_OFFSET) -#define LM_UART0_IBRD (LM_UART0_BASE + LM_UART_IBRD_OFFSET) -#define LM_UART0_FBRD (LM_UART0_BASE + LM_UART_FBRD_OFFSET) -#define LM_UART0_LCRH (LM_UART0_BASE + LM_UART_LCRH_OFFSET) -#define LM_UART0_CTL (LM_UART0_BASE + LM_UART_CTL_OFFSET) -#define LM_UART0_IFLS (LM_UART0_BASE + LM_UART_IFLS_OFFSET) -#define LM_UART0_IM (LM_UART0_BASE + LM_UART_IM_OFFSET) -#define LM_UART0_RIS (LM_UART0_BASE + LM_UART_RIS_OFFSET) -#define LM_UART0_MIS (LM_UART0_BASE + LM_UART_MIS_OFFSET) -#define LM_UART0_ICR (LM_UART0_BASE + LM_UART_ICR_OFFSET) -#define LM_UART0_PERIPHID4 (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET) -#define LM_UART0_PERIPHID5 (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET) -#define LM_UART0_PERIPHID6 (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET) -#define LM_UART0_PERIPHID7 (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET) -#define LM_UART0_PERIPHID0 (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET) -#define LM_UART0_PERIPHID1 (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET) -#define LM_UART0_PERIPHID2 (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET) -#define LM_UART0_PERIPHID3 (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET) -#define LM_UART0_PCELLID0 (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET) -#define LM_UART0_PCELLID1 (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET) -#define LM_UART0_PCELLID2 (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET) -#define LM_UART0_PCELLID3 (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET) - -#define LM_UART1_DR (LM_UART1_BASE + LM_UART_DR_OFFSET) -#define LM_UART1_RSR (LM_UART1_BASE + LM_UART_RSR_OFFSET) -#define LM_UART1_ECR (LM_UART1_BASE + LM_UART_ECR_OFFSET) -#define LM_UART1_FR (LM_UART1_BASE + LM_UART_FR_OFFSET) -#define LM_UART1_ILPR (LM_UART1_BASE + LM_UART_ILPR_OFFSET) -#define LM_UART1_IBRD (LM_UART1_BASE + LM_UART_IBRD_OFFSET) -#define LM_UART1_FBRD (LM_UART1_BASE + LM_UART_FBRD_OFFSET) -#define LM_UART1_LCRH (LM_UART1_BASE + LM_UART_LCRH_OFFSET) -#define LM_UART1_CTL (LM_UART1_BASE + LM_UART_CTL_OFFSET) -#define LM_UART1_IFLS (LM_UART1_BASE + LM_UART_IFLS_OFFSET) -#define LM_UART1_IM (LM_UART1_BASE + LM_UART_IM_OFFSET) -#define LM_UART1_RIS (LM_UART1_BASE + LM_UART_RIS_OFFSET) -#define LM_UART1_MIS (LM_UART1_BASE + LM_UART_MIS_OFFSET) -#define LM_UART1_ICR (LM_UART1_BASE + LM_UART_ICR_OFFSET) -#define LM_UART1_PERIPHID4 (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET) -#define LM_UART1_PERIPHID5 (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET) -#define LM_UART1_PERIPHID6 (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET) -#define LM_UART1_PERIPHID7 (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET) -#define LM_UART1_PERIPHID0 (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET) -#define LM_UART1_PERIPHID1 (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET) -#define LM_UART1_PERIPHID2 (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET) -#define LM_UART1_PERIPHID3 (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET) -#define LM_UART1_PCELLID0 (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET) -#define LM_UART1_PCELLID1 (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET) -#define LM_UART1_PCELLID2 (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET) -#define LM_UART1_PCELLID3 (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET) - -/* UART register bit settings *******************************************************/ - -/* UART Data (DR), offset 0x000 */ - -#define UART_DR_DATA_SHIFT 0 /* Bits 7-0: Data Transmitted or Received */ -#define UART_DR_DATA_MASK (0xff << UART_DR_DATA_SHIFT) -#define UART_DR_FE (1 << 8) /* Bit 8: UART Framing Error */ -#define UART_DR_PE (1 << 9) /* Bit 9: UART Parity Error */ -#define UART_DR_BE (1 << 10) /* Bit 10: UART Break Error */ -#define UART_DR_OE (1 << 11) /* Bit 11: UART Overrun Error */ - -/* UART Receive Status (RSR), offset 0x004 */ - -#define UART_RSR_FE (1 << 0) /* Bit 0: UART Framing Error */ -#define UART_RSR_PE (1 << 1) /* Bit 1: UART Parity Error */ -#define UART_RSR_BE (1 << 2) /* Bit 2: UART Break Error */ -#define UART_RSR_OE (1 << 3) /* Bit 3: UART Overrun Error */ - -/* UART Error Clear (ECR), offset 0x004 */ -/* Writing any value to this register clears pending error indications */ - -/* UART Flag (FR), offset 0x018 */ - -#define UART_FR_BUSY (1 << 3) /* Bit 3: UART Busy */ -#define UART_FR_RXFE (1 << 4) /* Bit 4: UART Receive FIFO Empty */ -#define UART_FR_TXFF (1 << 5) /* Bit 5: UART Transmit FIFO Full */ -#define UART_FR_RXFF (1 << 6) /* Bit 6: UART Receive FIFO Full */ -#define UART_FR_TXFE (1 << 7) /* Bit 7: UART Transmit FIFO Empty */ - -/* UART IrDA Low-Power Register (ILPR), offset 0x020 */ - -#define UART_ILPR_DVSR_MASK (0xff) /* Bits 7-0: IrDA Low-Power Divisor */ - -/* UART Integer Baud-Rate Divisor (IBRD), offset 0x024 */ - -#define UART_IBRD_DIVINT_MASK (0xffff) /* Bits 15-0: Integer Baud-Rate Divisor */ - -/* UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 */ - -#define UART_FBRD_DIVFRAC_MASK (0x3f) /* Bits 5-0: Fractional Baud-Rate Divisor */ - -/* Register 7: UART Line Control (LCRH), offset 0x02C */ - -#define UART_LCRH_BRK (1 << 0) /* Bit 0: UART Send Break */ -#define UART_LCRH_PEN (1 << 1) /* Bit 1: UART Parity Enable */ -#define UART_LCRH_EPS (1 << 2) /* Bit 2: UART Even Parity Select */ -#define UART_LCRH_STP2 (1 << 3) /* Bit 3: UART Two Stop Bits Select */ -#define UART_LCRH_FEN (1 << 4) /* Bit 4: UART Enable FIFOs */ -#define UART_LCRH_WLEN_SHIFT 5 /* Bits 6-5: UART Word Length */ -#define UART_LCRH_WLEN_MASK (3 << UART_LCRH_WLEN_SHIFT) -# define UART_LCRH_WLEN_5BITS (0 << UART_LCRH_WLEN_SHIFT) /* 5-bits (reset) */ -# define UART_LCRH_WLEN_6BITS (1 << UART_LCRH_WLEN_SHIFT) /* 6-bits */ -# define UART_LCRH_WLEN_7BITS (2 << UART_LCRH_WLEN_SHIFT) /* 7-bits */ -# define UART_LCRH_WLEN_8BITS (3 << UART_LCRH_WLEN_SHIFT) /* 8-bits */ -#define UART_LCRH_SPS (1 << 7) /* Bit 7: UART Stick Parity Select */ - -/* UART Control (CTL), offset 0x030 */ - -#define UART_CTL_UARTEN (1 << 0) /* Bit 0: UART Enable */ -#define UART_CTL_SIREN (1 << 1) /* Bit 1: UART SIR Enable */ -#define UART_CTL_SIRLP (1 << 2) /* Bit 2: UART SIR Low Power Mode */ -#define UART_CTL_LBE (1 << 7) /* Bit 7: UART Loop Back Enable */ -#define UART_CTL_TXE (1 << 8) /* Bit 8: UART Transmit Enable */ -#define UART_CTL_RXE (1 << 9) /* Bit 9: UART Receive Enable */ - -/* UART Interrupt FIFO Level Select (IFLS), offset 0x034 */ - -#define UART_IFLS_TXIFLSEL_SHIFT 0 /* Bits 2-0: UART Transmit Interrupt FIFO Level Select */ -#define UART_IFLS_TXIFLSEL_MASK (7 << UART_IFLS_TXIFLSEL_SHIFT) -# define UART_IFLS_TXIFLSEL_18th (0 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_TXIFLSEL_14th (1 << UART_IFLS_TXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_TXIFLSEL_half (2 << UART_IFLS_TXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_TXIFLSEL_34th (3 << UART_IFLS_TXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_TXIFLSEL_78th (4 << UART_IFLS_TXIFLSEL_SHIFT) /* 7/8th full */ -#define UART_IFLS_RXIFLSEL_SHIFT 3 /* Bits 5-3: UART Receive Interrupt FIFO Level Select */ -#define UART_IFLS_RXIFLSEL_MASK (7 << UART_IFLS_RXIFLSEL_SHIFT) -# define UART_IFLS_RXIFLSEL_18th (0 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/8th full */ -# define UART_IFLS_RXIFLSEL_14th (1 << UART_IFLS_RXIFLSEL_SHIFT) /* 1/4th full */ -# define UART_IFLS_RXIFLSEL_half (2 << UART_IFLS_RXIFLSEL_SHIFT) /* half full */ -# define UART_IFLS_RXIFLSEL_34th (3 << UART_IFLS_RXIFLSEL_SHIFT) /* 3/4th full */ -# define UART_IFLS_RXIFLSEL_78th (4 << UART_IFLS_RXIFLSEL_SHIFT) /* 7/8th full */ - -/* UART Interrupt Mask (IM), offset 0x038 */ - -#define UART_IM_RXIM (1 << 4) /* Bit 4: UART Receive Interrupt Mask */ -#define UART_IM_TXIM (1 << 5) /* Bit 5: UART Transmit Interrupt Mask */ -#define UART_IM_RTIM (1 << 6) /* Bit 6: UART Receive Time-Out Interrupt Mask */ -#define UART_IM_FEIM (1 << 7) /* Bit 7: UART Framing Error Interrupt Mask */ -#define UART_IM_PEIM (1 << 8) /* Bit 8: UART Parity Error Interrupt Mask */ -#define UART_IM_BEIM (1 << 9) /* Bit 9: UART Break Error Interrupt Mask */ -#define UART_IM_OEIM (1 << 10) /* Bit 10: UART Overrun Error Interrupt Mask */ - - -/* UART Raw Interrupt Status (RIS), offset 0x03c */ - -#define UART_RIS_RXRIS (1 << 4) /* Bit 4: UART Receive Raw Interrupt Status */ -#define UART_RIS_TXRIS (1 << 5) /* Bit 5: UART Transmit Raw Interrupt Status */ -#define UART_RIS_RTRIS (1 << 6) /* Bit 6: UART Receive Time-Out Raw Interrupt Status */ -#define UART_RIS_FERIS (1 << 7) /* Bit 7: UART Framing Error Raw Interrupt Status */ -#define UART_RIS_PERIS (1 << 8) /* Bit 8: UART Parity Error Raw Interrupt Status */ -#define UART_RIS_BERIS (1 << 9) /* Bit 9: UART Break Error Raw Interrupt Status */ -#define UART_RIS_OERIS (1 << 10) /* Bit 10: UART Overrun Error Raw Interrupt Status */ - -/* UART Masked Interrupt Status (MIS), offset 0x040 */ - -#define UART_MIS_RXMIS (1 << 4) /* Bit 4: UART Receive Masked Interrupt Status */ -#define UART_MIS_TXMIS (1 << 5) /* Bit 5: UART Transmit Masked Interrupt Status */ -#define UART_MIS_RTMIS (1 << 6) /* Bit 6: UART Receive Time-Out Masked Interrupt Status */ -#define UART_MIS_FEMIS (1 << 7) /* Bit 7: UART Framing Error Masked Interrupt Status */ -#define UART_MIS_PEMIS (1 << 8) /* Bit 8: UART Parity Error Masked Interrupt Status */ -#define UART_MIS_BEMIS (1 << 9) /* Bit 9: UART Break Error Masked Interrupt Status */ -#define UART_MIS_OEMIS (1 << 10) /* Bit 10: UART Overrun Error Masked Interrupt Status */ - -/* UART Interrupt Clear (ICR), offset 0x044 */ - -#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */ -#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */ -#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */ -#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */ -#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */ -#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */ -#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear - */ - -/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */ - -#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */ - -#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */ - -#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */ - -#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */ - -#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */ - -/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */ - -#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */ - -/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */ - -#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */ - -/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */ - -#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */ - -/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */ - -#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */ - -/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */ - -#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */ - -/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */ - -#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */ - -/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */ - -#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_UART_H */ diff --git a/nuttx/arch/arm/src/lm/chip/lm_vectors.h b/nuttx/arch/arm/src/lm/chip/lm_vectors.h deleted file mode 100644 index 97227bf29..000000000 --- a/nuttx/arch/arm/src/lm/chip/lm_vectors.h +++ /dev/null @@ -1,64 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lm/chip/lm_vectors.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -/* Include the vector file for the specific Stellaris chip */ - -#if defined(CONFIG_ARCH_CHIP_LM3S) -# include "chip/lm3s_vectors.h" -#elif defined(CONFIG_ARCH_CHIP_LM4F) -# include "chip/lm4f_vectors.h" -#else -# error "Unsupported Stellaris vector file" -#endif - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ |