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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-05-23 14:26:22 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-05-23 14:26:22 +0000 |
| commit | 3b9ec2b7dd4cf15048d5196b3a4c2e5f4683634d (patch) | |
| tree | 316c1d9d389dcf684a9a02d4cc9c8ff701b30581 /nuttx/arch/arm/src/lm3s/lm3s_ssi.h | |
| parent | 39b40937f83f939a221978a92c3a239d1ce53c32 (diff) | |
| download | px4-nuttx-3b9ec2b7dd4cf15048d5196b3a4c2e5f4683634d.tar.gz px4-nuttx-3b9ec2b7dd4cf15048d5196b3a4c2e5f4683634d.tar.bz2 px4-nuttx-3b9ec2b7dd4cf15048d5196b3a4c2e5f4683634d.zip | |
Add LM3S SSI driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1818 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lm3s/lm3s_ssi.h')
| -rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_ssi.h | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h b/nuttx/arch/arm/src/lm3s/lm3s_ssi.h index 8ffdc9a44..10832dda1 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_ssi.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_ssi.h @@ -43,7 +43,7 @@ #include <nuttx/config.h> #include <sys/types.h> -#if LMS_NSSI > 0 +#if LM3S_NSSI > 0 /************************************************************************************ * Definitions @@ -97,7 +97,7 @@ #define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET) #define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET) -#if LMS_NSSI > 1 +#if LM3S_NSSI > 1 #define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET) #define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET) #define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET) @@ -143,18 +143,18 @@ #define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET) #define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET) #define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET) -#endif /* LMS_NSSI > 1 */ +#endif /* LM3S_NSSI > 1 */ /* SSI register bit defitiions ******************************************************/ /* SSI Control 0 (SSICR0), offset 0x000 */ -#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select +#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */ #define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT) #define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */ #define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */ #define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT) -#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */e +#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */ #define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */ #define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */ #define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */ @@ -187,37 +187,37 @@ /* SSI Interrupt Mask (SSIIM), offset 0x014 */ -#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ -#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ -#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ -#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ +#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */ +#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */ +#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */ +#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */ /* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */ -#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ -#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ -#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ -#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ +#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */ +#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */ +#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */ +#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */ /* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */ -#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ -#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ -#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ -#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ +#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */ +#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */ +#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */ +#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */ /* SSI Interrupt Clear (SSIICR), offset 0x020 */ -#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ -#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ +#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */ +#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */ /* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */ -#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ +#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */ /* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */ -#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ +#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ /************************************************************************************ * Public Types @@ -231,5 +231,5 @@ * Public Function Prototypes ************************************************************************************/ -#endif /* LMS_NSSI > 0 */ +#endif /* LM3S_NSSI > 0 */ #endif /* __ARCH_ARM_SRC_LM3S_LM3S_SSI_H */ |