diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-08-12 01:49:25 +0000 |
---|---|---|
committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-08-12 01:49:25 +0000 |
commit | 1a5be88b91218994ccd12cf8bd2f2f676812f174 (patch) | |
tree | fe5106398d76d0e36b52bc563b8ea6c337652cf9 /nuttx/arch/arm/src/lm3s | |
parent | a7f03d85cf63e824cdb0a4bc928c4a13eb69a3fd (diff) | |
download | px4-nuttx-1a5be88b91218994ccd12cf8bd2f2f676812f174.tar.gz px4-nuttx-1a5be88b91218994ccd12cf8bd2f2f676812f174.tar.bz2 px4-nuttx-1a5be88b91218994ccd12cf8bd2f2f676812f174.zip |
Add changes for LM3S9B96
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2841 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lm3s')
-rw-r--r-- | nuttx/arch/arm/src/lm3s/chip.h | 14 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_ethernet.c | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_ethernet.h | 6 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_gpio.c | 11 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_gpio.h | 35 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c | 10 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_internal.h | 57 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_memorymap.h | 89 | ||||
-rw-r--r-- | nuttx/arch/arm/src/lm3s/lm3s_vectors.S | 111 |
9 files changed, 329 insertions, 6 deletions
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h index 1fe701c71..071d35ca7 100644 --- a/nuttx/arch/arm/src/lm3s/chip.h +++ b/nuttx/arch/arm/src/lm3s/chip.h @@ -51,6 +51,7 @@ #if defined(CONFIG_ARCH_CHIP_LM3S6918) # define LM3S_NTIMERS 4 /* Four general purpose timers */ # define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ # define LM3S_NSSI 2 /* Two SSI modules */ # define LM3S_NUARTS 2 /* Two UART modules */ # define LM3S_NI2C 2 /* Two I2C modules */ @@ -61,6 +62,7 @@ #elif defined(CONFIG_ARCH_CHIP_LM3S6965) # define LM3S_NTIMERS 4 /* Four general purpose timers */ # define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ # define LM3S_NSSI 1 /* One SSI module */ # define LM3S_NUARTS 3 /* Three UART modules */ # define LM3S_NI2C 2 /* Two I2C modules */ @@ -68,6 +70,18 @@ # define LM2S_NPWM 3 /* Three PWM generator modules */ # define LM3S_NQEI 2 /* Two quadrature encoders */ # define LC3S_NGPIOS 42 /* 0-42 GPIOs */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_NTIMERS 4 /* Four general purpose timers */ +# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */ +# undef LM3S_ETHTS /* No timestamp register */ +# define LM3S_NSSI 2 /* Two SSI modules */ +# define LM3S_NUARTS 3 /* Three UART modules */ +# define LM3S_NI2C 2 /* Two I2C modules */ +# define LM3S_NADC 2 /* Two ADC module */ +# define LM3S_CAN 2 /* Two CAN module */ +# define LM3S_NPWM 4 /* Four PWM generator modules */ +# define LM3S_NQEI 2 /* Two quadrature encoders */ +# define LC3S_NGPIOS 65 /* 0-65 GPIOs */ #else # error "Capabilities not specified for this LM3S chip" #endif diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c index 1dee89e79..feb3b9a90 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.c @@ -1072,7 +1072,7 @@ static int lm3s_ifup(struct uip_driver_s *dev) /* Setup the time stamp configuration register */ -#if !defined(CONFIG_ARCH_CHIP_LM3S6918) && !defined(CONFIG_ARCH_CHIP_LM3S6965) +#ifdef LM3S_ETHTS regval = lm3s_ethin(priv, LM3S_MAC_TS_OFFSET); #ifdef CONFIG_LM3S_TIMESTAMP regval |= MAC_TS_EN; diff --git a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h index d1852db7f..ea98c8b07 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_ethernet.h @@ -43,6 +43,8 @@ #include <nuttx/config.h> #include <nuttx/mii.h> +#include "chip.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -66,7 +68,7 @@ #define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */ #define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */ #define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */ -#if !defined(CONFIG_ARCH_CHIP_LM3S6918) && !defined(CONFIG_ARCH_CHIP_LM3S6965) +#ifdef LM3S_ETHTS # define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */ #endif @@ -89,7 +91,7 @@ #define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET) #define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET) #define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET) -#if !defined(CONFIG_ARCH_CHIP_LM3S6918) && !defined(CONFIG_ARCH_CHIP_LM3S6965) +#ifdef LM3S_ETHTS # define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET) #endif diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c index cc1f77c35..5614b54f9 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.c @@ -56,6 +56,17 @@ * Pre-processor Definitions ****************************************************************************/ +/* This current implementation can only support, at most, 8 GPIO ports. Some + * newer chips (such as the LM3S9B96) have 9 GPIO ports. It will require + * some restructuring of the definitions in lm3s_internal.h and to the size + * of the g_gpiobase[] table and the lm3s_gpiobaseaddress() function in this + * file to access GPIOs in ports above GPIOH. + */ + +#if LC3S_NGPIOS > 64 +# warning "This design must be extended to access ports above GPIOH" +#endif + /* These definitions are part of the implementation of the GPIO pad * configuration of Table 9-1 in the LM3S6918 data sheet. */ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h b/nuttx/arch/arm/src/lm3s/lm3s_gpio.h index 410ecb1e0..4b0456913 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpio.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpio.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/lm3s/lm3s_gpio.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <spudmonkey@racsa.co.cr> * * Redistribution and use in source and binary forms, with or without @@ -347,6 +347,39 @@ #define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET) #define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET) +#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET) +#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET) +#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET) +#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET) +#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET) +#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET) +#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET) +#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET) +#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET) +#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET) +#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET) +#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET) +#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET) +#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET) +#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET) +#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET) +#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET) +#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET) +#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET) +#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET) +#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET) +#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET) +#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET) +#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET) +#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET) +#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET) +#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET) +#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET) +#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET) +#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET) +#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET) +#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET) + /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c index 2879a6667..e0fa531a9 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c +++ b/nuttx/arch/arm/src/lm3s/lm3s_gpioirq.c @@ -110,7 +110,11 @@ static const uint32_t g_gpiobase[] = #else 0, #endif +#if !defined(CONFIG_LM3S_DISABLE_GPIOJ_IRQS) && defined(LM3S_GPIOJ_BASE) + LM3S_GPIOJ_BASE, +#endif }; +#define GPIO_NPORTS (sizeof(g_gpiobase)/sizeof(uint32_t)) /**************************************************************************** * Public Data @@ -131,7 +135,11 @@ static const uint32_t g_gpiobase[] = static inline uint32_t lm3s_gpiobaseaddress(unsigned int port) { - return g_gpiobase[port >> 3]; + if (port < GPIO_NPORTS) + { + return g_gpiobase[port >> 3]; + } + return 0; } /**************************************************************************** diff --git a/nuttx/arch/arm/src/lm3s/lm3s_internal.h b/nuttx/arch/arm/src/lm3s/lm3s_internal.h index 5fef7dd66..32671c586 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_internal.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_internal.h @@ -129,6 +129,11 @@ /* This identifies the GPIO port * nnnn nnnn nnnn nnnn nnnn nnnn nnPP Pnnn + * + * NOTE: Because this field is limited to 3 bits, it can only support 8 ports. + * Newer chips (such as the LM3S9B96) have 9 GPIO ports. It will require + * some restructuring of these definitions (and the logic in lm3s_gpio.c) + * to access GPIOs in ports above GPIOH. */ #define GPIO_PORT_SHIFT 3 /* Bit 3-5: Port number */ @@ -242,11 +247,61 @@ # define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ # define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ # define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */ +# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */ +# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */ +# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */ +# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */ +# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */ +# define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 7) /* PA6: I2C1 clock (I2C1SCL) */ +# define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */ +# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */ +# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */ +# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */ +# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */ +# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */ +# define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */ +# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */ +# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */ +# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */ +# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */ +# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */ +# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */ +# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */ +# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */ +# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */ +# define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */ +# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */ +# define GPIO_TMR3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */ +# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 7) /* PC7: QEI module 0 phase B. */ +# define GPIO_QEI0_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 1) /* PD0: QEI module 0 index. ) */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: PWM Generator 0, PWM1 */ +# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */ +# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */ +# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PC4: Capture/Compare/PWM0 (CCP0) */ +# define GPIO_TMR2_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 5) /* PC5: Capture/Compare/PWM2 (CCP2) */ +# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PC5: PWM Fault */ +# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC5: Capture/Compare/TMR1 (CCP1) */ +# define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */ +# define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */ +# define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */ +# define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */ +# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */ +# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */ +# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */ +# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */ +# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PE4: PWM Generator 0, PWM0 */ +# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PD0: QEI module 1 index. ) */ +# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ +# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ +# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */ +# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */ #else # error "Unknown LM3S chip" #endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h index fe1c3845b..67f5e758f 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h +++ b/nuttx/arch/arm/src/lm3s/lm3s_memorymap.h @@ -67,6 +67,26 @@ /* -0xe003ffff: Reserved */ # define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ /* -0xffffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ + /* -0x1fffffff: Reserved */ +# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */ + /* -0x21ffffff: Reserved */ +# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */ + /* -0x3fffffff: Reserved */ +# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */ + /* -0x41ffffff: Peripherals */ +# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */ + /* -0x5fffffff: Reserved */ +# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */ +# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ +# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ +# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ + /* -0xe000dfff: Reserved */ +# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ + /* -0xe003ffff: Reserved */ +# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ + /* -0xffffffff: Reserved */ #else # error "Memory map not specified for this LM3S chip" #endif @@ -166,6 +186,75 @@ # define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ # define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ /* -0x1ffffff: Reserved */ +#elif defined(CONFIG_ARCH_CHIP_LM3S9B96) +/* FiRM Peripheral Base Addresses */ + +# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */ + /* -0x03fff: Reserved */ +# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */ +# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */ +# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */ +# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */ +# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */ +# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */ + /* -0x0bfff: Reserved */ +# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ +# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ +# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ + /* -0x1ffff: Reserved */ +/* Peripheral Base Addresses */ + +# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */ +# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */ +# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */ +# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */ + /* -0x23fff: Reserved */ +# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */ +# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */ +# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */ +# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */ + +# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */ + /* -0x2bfff: Reserved */ +# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */ +# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */ + /* -0x2ffff: Reserved */ +# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */ +# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */ +# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */ +# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */ + /* -0x37fff: Reserved */ +# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */ +# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */ + /* -0x3bfff: Reserved */ +# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */ +# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */ + /* -0x3ffff: Reserved */ +# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */ +# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */ + /* -0x47fff: Reserved */ +# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */ + /* -0x49fff: Reserved */ +# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */ + /* -0x53fff: Reserved */ +# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */ + /* -0x57fff: Reserved */ +# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */ +# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */ +# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */ +# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */ +# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */ +# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */ +# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */ +# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */ +# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */ + /* -0xcffff: Reserved */ +# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */ + /* -0xfcfff: Reserved */ +# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */ +# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */ +# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */ + /* -0x1ffffff: Reserved */ #else # error "Peripheral base addresses not specified for this LM3S chip" #endif diff --git a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S index d760c13f7..e1f2919a4 100644 --- a/nuttx/arch/arm/src/lm3s/lm3s_vectors.S +++ b/nuttx/arch/arm/src/lm3s/lm3s_vectors.S @@ -239,6 +239,63 @@ lm3s_vectors: .word lm3s_reserved /* Vector 68: Reserved */
.word lm3s_reserved /* Vector 69: Reserved */
.word lm3s_reserved /* Vector 70: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+ .word lm3s_gpioa /* Vector 16: GPIO Port A */
+ .word lm3s_gpiob /* Vector 17: GPIO Port B */
+ .word lm3s_gpioc /* Vector 18: GPIO Port C */
+ .word lm3s_gpiod /* Vector 19: GPIO Port D */
+ .word lm3s_gpioe /* Vector 20: GPIO Port E */
+ .word lm3s_uart0 /* Vector 21: UART 0 */
+ .word lm3s_uart1 /* Vector 22: UART 1 */
+ .word lm3s_ssi0 /* Vector 23: SSI 0 */
+ .word lm3s_i2c0 /* Vector 24: I2C 0 */
+ .word lm3s_pwmfault /* Vector 25: PWM Fault */
+ .word lm3s_pwm0 /* Vector 26: PWM Generator 0 */
+ .word lm3s_pwm1 /* Vector 27: PWM Generator 1 */
+ .word lm3s_pwm2 /* Vector 28: PWM Generator 2 */
+ .word lm3s_qei0 /* Vector 29: QEI0 */
+ .word lm3s_adc0 /* Vector 30: ADC Sequence 0 */
+ .word lm3s_adc1 /* Vector 31: ADC Sequence 1 */
+ .word lm3s_adc2 /* Vector 32: ADC Sequence 2 */
+ .word lm3s_adc3 /* Vector 33: ADC Sequence 3 */
+ .word lm3s_wdog /* Vector 34: Watchdog Timer */
+ .word lm3s_tmr0a /* Vector 35: Timer 0 A */
+ .word lm3s_tmr0b /* Vector 36: Timer 0 B */
+ .word lm3s_tmr1a /* Vector 37: Timer 1 A */
+ .word lm3s_tmr1b /* Vector 38: Timer 1 B */
+ .word lm3s_tmr2a /* Vector 39: Timer 2 A */
+ .word lm3s_tmr2b /* Vector 40: Timer 3 B */
+ .word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */
+ .word lm3s_cmp1 /* Vector 42: Analog Comparator 1 */
+ .word lm3s_cmp2 /* Vector 43: Reserved */
+ .word lm3s_syscon /* Vector 44: System Control */
+ .word lm3s_flashcon /* Vector 45: FLASH Control */
+ .word lm3s_gpiof /* Vector 46: GPIO Port F */
+ .word lm3s_gpiog /* Vector 47: GPIO Port G */
+ .word lm3s_gpioh /* Vector 48: GPIO Port H */
+ .word lm3s_uart2 /* Vector 49: UART 2 */
+ .word lm3s_ssi1 /* Vector 50: SSI 1 */
+ .word lm3s_tmr3a /* Vector 51: Timer 3 A */
+ .word lm3s_tmr3b /* Vector 52: Timer 3 B */
+ .word lm3s_i2c1 /* Vector 53: I2C 1 */
+ .word lm3s_qei1 /* Vector 54: QEI1 */
+ .word lm3s_can0 /* Vector 55: CAN 0 */
+ .word lm3s_can1 /* Vector 56: CAN 1 */
+ .word lm3s_reserved /* Vector 57: Reserved */
+ .word lm3s_eth /* Vector 58: Ethernet Controller */
+ .word lm3s_reserved /* Vector 59: Reserved */
+ .word lm3s_usb /* Vector 60: USB */
+ .word lm3s_pwm3 /* Vector 61: PWM 3 */
+ .word lm3s_udmasoft /* Vector 62: uDMA Software */
+ .word lm3s_udmaerror /* Vector 63: uDMA Error */
+ .word lm3s_adc1_0 /* Vector 64: ADC1 Sequence 0 */
+ .word lm3s_adc1_1 /* Vector 65: ADC1 Sequence 1 */
+ .word lm3s_adc1_2 /* Vector 66: ADC1 Sequence 2 */
+ .word lm3s_adc1_3 /* Vector 67: ADC1 Sequence 3 */
+ .word lm3s_i2s0 /* Vector 68: I2S 0 */
+ .word lm3s_epi /* Vector 69: Reserved */
+ .word lm3s_gpioj /* Vector 70: GPIO J */
+ .word lm3s_reserved /* Vector 71: Reserved */
#else
# error "Vectors not specified for this LM3S chip"
#endif
@@ -336,6 +393,60 @@ handlers: HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
+#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
+ HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
+ HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
+ HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
+ HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
+ HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
+ HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
+ HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
+ HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
+ HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
+ HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
+ HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
+ HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
+ HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
+ HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
+ HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
+ HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
+ HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
+ HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
+ HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
+ HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
+ HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
+ HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
+ HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
+ HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
+ HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
+ HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
+ HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
+ HANDLER lm3s_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */
+ HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
+ HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
+ HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
+ HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
+ HANDLER lm3s_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */
+ HANDLER lm3s_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */
+ HANDLER lm3s_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */
+ HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
+ HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
+ HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
+ HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
+ HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */
+ HANDLER lm3s_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */
+ HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
+ HANDLER lm3s_usb, LM3S_IRQ_USB /* Vector 60: USB */
+ HANDLER lm3s_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */
+ HANDLER lm3s_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */
+ HANDLER lm3s_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */
+ HANDLER lm3s_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */
+ HANDLER lm3s_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */
+ HANDLER lm3s_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */
+ HANDLER lm3s_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */
+ HANDLER lm3s_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */
+ HANDLER lm3s_epi, LM3S_IRQ_EPI /* Vector 69: EPI */
+ HANDLER lm3s_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */
#else
# error "Vectors not specified for this LM3S chip"
#endif
|