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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2008-10-11 19:37:25 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2008-10-11 19:37:25 +0000 |
commit | 3b2030d6a688297d67c8a994502b9f692466e509 (patch) | |
tree | e5d5fd5ed184ac7d15b577643fefa66e5b089874 /nuttx/arch/arm/src/lpc214x/chip.h | |
parent | 9ab9aa14f35208b190a72ce0c7909f29dd1cf00a (diff) | |
download | px4-nuttx-3b2030d6a688297d67c8a994502b9f692466e509.tar.gz px4-nuttx-3b2030d6a688297d67c8a994502b9f692466e509.tar.bz2 px4-nuttx-3b2030d6a688297d67c8a994502b9f692466e509.zip |
Add header files for PINSEL and SPI
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1031 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm/src/lpc214x/chip.h')
-rw-r--r-- | nuttx/arch/arm/src/lpc214x/chip.h | 36 |
1 files changed, 19 insertions, 17 deletions
diff --git a/nuttx/arch/arm/src/lpc214x/chip.h b/nuttx/arch/arm/src/lpc214x/chip.h index 74e976dfb..6a4803b17 100644 --- a/nuttx/arch/arm/src/lpc214x/chip.h +++ b/nuttx/arch/arm/src/lpc214x/chip.h @@ -181,23 +181,25 @@ #define LPC214X_AD_ADDR7_OFFSET 0x2c /* A/D Chanel 0 Data Register */ #define LPC214X_AD_ADSTAT_OFFSET 0x30 /* A/D Status Register */ -/* Pin function select registers (these are normally referenced as offsets) */ - -#define LPC214X_PINSEL0 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET) -#define LPC214X_PINSEL1 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET) -#define LPC214X_PINSEL2 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET) - -/* SPI register offsets */ - -#define LPC214X_SPI_CR0_OFFSET 0x00 /* Control Register 0 */ -#define LPC214X_SPI_CR1_OFFSET 0x04 /* Control Register 1 */ -#define LPC214X_SPI_DR_OFFSET 0x08 /* Data Register */ -#define LPC214X_SPI_SR_OFFSET 0x0c /* Status Register */ -#define LPC214X_SPI_CPSR_OFFSET 0x10 /* Clock Pre-Scale Regisrer */ -#define LPC214X_SPI_IMSC_OFFSET 0x14 /* Interrupt Mask Set and Clear Register */ -#define LPC214X_SPI_RIS_OFFSET 0x18 /* Raw Interrupt Status Register */ -#define LPC214X_SPI_MIS_OFFSET 0x1c /* Masked Interrupt Status Register */ -#define LPC214X_SPI_ICR_OFFSET 0x20 /* Interrupt Clear Register */ +/* SPI0 register offsets */ + +#define LPC214X_SPI0_CR_OFFSET 0x00 /* Control Register 0 */ +#define LPC214X_SPI0_SR_OFFSET 0x04 /* Control Register 1 */ +#define LPC214X_SPI0_DR_OFFSET 0x08 /* Data Register */ +#define LPC214X_SPI0_CCR_OFFSET 0x0c /* Status Register */ +#define LPC214X_SPI0_INT_OFFSET 0x1c /* Clock Pre-Scale Regisrer */ + +/* SPI1 register offsets */ + +#define LPC214X_SPI1_CR0_OFFSET 0x00 /* Control Register 0 */ +#define LPC214X_SPI1_CR1_OFFSET 0x04 /* Control Register 1 */ +#define LPC214X_SPI1_DR_OFFSET 0x08 /* Data Register */ +#define LPC214X_SPI1_SR_OFFSET 0x0c /* Status Register */ +#define LPC214X_SPI1_CPSR_OFFSET 0x10 /* Clock Pre-Scale Regisrer */ +#define LPC214X_SPI1_IMSC_OFFSET 0x14 /* Interrupt Mask Set and Clear Register */ +#define LPC214X_SPI1_RIS_OFFSET 0x18 /* Raw Interrupt Status Register */ +#define LPC214X_SPI1_MIS_OFFSET 0x1c /* Masked Interrupt Status Register */ +#define LPC214X_SPI1_ICR_OFFSET 0x20 /* Interrupt Clear Register */ /* RTC register offsets */ |