Add clock initialization

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2463 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 338 insertions, 13 deletions

diff --git a/nuttx/arch/arm/src/lpc313x/Make.defs b/nuttx/arch/arm/src/lpc313x/Make.defs
index 3b5d975ff..63f681b9a 100755
--- a/nuttx/arch/arm/src/lpc313x/Make.defs
+++ b/nuttx/arch/arm/src/lpc313x/Make.defs
@@ -47,9 +47,10 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 
 CGU_ASRCS	= 
 CGU_CSRCS	= lpc313x_bcrndx.c lpc313x_clkdomain.c lpc313x_clkexten.c \
-		  lpc313x_clkfreq.c lpc313x_defclk.c lpc313x_esrndx.c \
-		  lpc313x_fdcndx.c lpc313x_freqin.c lpc313x_pllconfig.c \
-		  lpc313x_resetclks.c lpc313x_setfreqin.c lpc313x_softreset.c
+		  lpc313x_clkfreq.c lpc313x_clkinit.c lpc313x_defclk.c \
+		  lpc313x_esrndx.c lpc313x_fdcndx.c lpc313x_freqin.c \
+		  lpc313x_pllconfig.c lpc313x_resetclks.c lpc313x_setfreqin.c \
+		  lpc313x_softreset.c
 
 CHIP_ASRCS	= $(CGU_ASRCS)
 CHIP_CSRCS	= lpc313x_allocateheap.c lpc313x_boot.c lpc313x_irq.c \
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h
index ee744b95e..fc488b8d2 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h
@@ -1176,21 +1176,22 @@
 /* Enable Select register ESR0 to ESR88, addresses 0x130043a0 to 0x13004500 */
 /* The ESR_SEL varies according to the selected clock */
 
+#define CGU_ESR_ESRSEL_SHIFT             (1)       /* Bits 1-n: Common shift value */
 #define CGU_ESR0_29_ESRSEL_SHIFT         (1)       /* Bits 1-3: Selection of fractional dividers */
-#define CGU_ESR0_29_ESRSEL_MASK          (7 << CGU_ESR_SHIFT)
-#  define CGU_ESR0_29_ESRSEL_FDC0        (0 << CGU_ESR_SHIFT) /* Selects FDC0 */
-#  define CGU_ESR0_29_ESRSEL_FDC1        (1 << CGU_ESR_SHIFT) /* Selects FDC1 */
-#  define CGU_ESR0_29_ESRSEL_FDC2        (2 << CGU_ESR_SHIFT) /* Selects FDC2 */
-#  define CGU_ESR0_29_ESRSEL_FDC3        (3 << CGU_ESR_SHIFT) /* Selects FDC3 */
-#  define CGU_ESR0_29_ESRSEL_FDC4        (4 << CGU_ESR_SHIFT) /* Selects FDC4 */
-#  define CGU_ESR0_29_ESRSEL_FDC5        (5 << CGU_ESR_SHIFT) /* Selects FDC5 */
-#  define CGU_ESR0_29_ESRSEL_FDC6        (6 << CGU_ESR_SHIFT) /* Selects FDC6 */
+#define CGU_ESR0_29_ESRSEL_MASK          (7 << CGU_ESR0_29_ESRSEL_SHIFT)
+#  define CGU_ESR0_29_ESRSEL_FDC0        (0 << CGU_ESR0_29_ESRSEL_SHIFT) /* Selects FDC0 */
+#  define CGU_ESR0_29_ESRSEL_FDC1        (1 << CGU_ESR0_29_ESRSEL_SHIFT) /* Selects FDC1 */
+#  define CGU_ESR0_29_ESRSEL_FDC2        (2 << CGU_ESR0_29_ESRSEL_SHIFT) /* Selects FDC2 */
+#  define CGU_ESR0_29_ESRSEL_FDC3        (3 << CGU_ESR0_29_ESRSEL_SHIFT) /* Selects FDC3 */
+#  define CGU_ESR0_29_ESRSEL_FDC4        (4 << CGU_ESR0_29_ESRSEL_SHIFT) /* Selects FDC4 */
+#  define CGU_ESR0_29_ESRSEL_FDC5        (5 << CGU_ESR0_29_ESRSEL_SHIFT) /* Selects FDC5 */
+#  define CGU_ESR0_29_ESRSEL_FDC6        (6 << CGU_ESR0_29_ESRSEL_SHIFT) /* Selects FDC6 */
 
 #define CGU_ESR30_39_ESRSEL_FDC7         (0)       /* Bit 1=0 selects FDC7 */
-#define CGU_ESR30_39_ESRSEL_FDC8         (1 << 1)  /* Bit 1=01selects FDC8 */
+#define CGU_ESR30_39_ESRSEL_FDC8         (1 << 1)  /* Bit 1=1 selects FDC8 */
 
 #define CGU_ESR40_49_ESRSEL_FDC9         (0)       /* Bit 1=0 selects FDC9 */
-#define CGU_ESR40_49_ESRSEL_FDC10        (1 << 1)  /* Bit 1=01selects FDC10 */
+#define CGU_ESR40_49_ESRSEL_FDC10        (1 << 1)  /* Bit 1=1 selects FDC10 */
 
 #define CGU_ESR50_57_ESRSEL_SHIFT        (1)       /* Bits 1-3: Selection of fractional dividers */
 #define CGU_ESR50_57_ESRSEL_MASK         (3 << CGU_ESR50_57_ESRSEL_SHIFT)
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h b/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h
index 8d1609656..25088b94f 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h
@@ -497,11 +497,13 @@ struct lpc313x_clkinit_s
     uint8_t finsel;
   } domain11;
 
+#if 0 /* Dynamic fractional divider initialization not implemented */
   struct
   {
     uint16_t  sel;
     struct lpc313x_fdivconfig_s cfg;
   } dynfdiv[CGU_NDYNFRACDIV];
+#endif
 };
 
 /* This structure is used to pass PLL configuration data to
@@ -619,6 +621,29 @@ EXTERN bool lpc313x_defclk(enum lpc313x_clockid_e clkid);
 
 EXTERN void lpc313x_resetclks(void);
 
+/************************************************************************
+ * Name: lpc313x_clkinit
+ *
+ * Description:
+ *   Initialize all clock domains based on board-specific clock
+ *   configuration data
+ *
+ ************************************************************************/
+
+EXTERN void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg);
+
+/************************************************************************
+ * Name: lpc313x_fdivinit
+ *
+ * Description:
+ *   Enable and configure (or disable) a fractional divider.
+ *
+ ************************************************************************/
+
+EXTERN uint32_t lpc313x_fdivinit(int fdcndx,
+                                 const struct lpc313x_fdivconfig_s *fdiv,
+                                 bool enable);
+
 /****************************************************************************
  * Name: lpc313x_pllconfig
  *
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_clkinit.c b/nuttx/arch/arm/src/lpc313x/lpc313x_clkinit.c
new file mode 100755
index 000000000..779fc3a05
--- /dev/null
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_clkinit.c
@@ -0,0 +1,298 @@
+/************************************************************************************
+ * arch/arm/src/lpc313x/lpc313x_clkinit.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "lpc313x_cgu.h"
+#include "lpc313x_cgudrvr.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/* This structure describes the configuration of one domain */
+
+struct lpc313x_domainconfig_s
+{
+  enum lpc313x_domainid_e dmnid; /* Domain ID */
+  uint32_t finsel;               /* Frequency input selection */
+  uint32_t clk1;                 /* ID of first clock in the domain */
+  uint32_t nclks;                /* Number of clocks in the domain */
+  uint32_t fdiv1;                /* First frequency divider in the domain */
+  uint32_t nfdiv;                /* Number of frequency dividers in the domain */
+  const struct lpc313x_subdomainconfig_s* sub; /* Sub=domain array */
+};
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: lpc313x_domaininit
+ *
+ * Description:
+ *   Initialize one clock domain based on board-specific clock  configuration data
+ *
+ ************************************************************************************/
+
+static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
+{
+  const struct lpc313x_subdomainconfig_s * sub = dmn->sub;
+  uint32_t fdivcfg;
+  uint32_t regaddr;
+  uint32_t regval;
+  int fdndx;
+  int clkndx;
+  int bcrndx = lp313x_bcrndx(dmn->dmnid);
+  int esrndx;
+
+  if (bcrndx != BCRNDX_INVALID)
+    {
+      /* Disable BCR for domain */
+
+      regaddr = LPC313X_CGU_BCR(bcrndx);
+      putreg32(0, regaddr);
+    }
+
+  /* Configure the fractional dividers in this domain */
+ 
+  for (fdndx = 0; fdndx < dmn->nfdiv; fdndx++, sub++)
+    {
+      /* Set fractional divider confiruation but don't enable it yet */
+
+      fdivcfg = lpc313x_fdivinit(fdndx + dmn->fdiv1, &sub->fdiv, false);
+
+      /* Enable frac divider only if it has valid settings */
+
+      if (fdivcfg != 0)
+        {
+          /* Select the fractional dividir for each clock in this
+           * sub domain.
+           */
+
+          for (clkndx = 0; clkndx <= dmn->nclks; clkndx++)
+            {
+              /* Does this clock have an ESR register? */
+ 
+              esrndx = lp313x_esrndx((enum lpc313x_clockid_e)(clkndx + dmn->clk1));
+              if (esrndx != ESRNDX_INVALID)
+                {
+                  /* Yes.. Check if this clock belongs to this sub-domain */
+
+                  if (sub->clkset & (1 << clkndx))
+                    {
+                      /* Yes.. configure the clock to use this fractional divider */
+
+                      regaddr = LPC313X_CGU_ESR(esrndx);
+                      putreg32((fdndx << CGU_ESR_ESRSEL_SHIFT) | CGU_ESR_ESREN, regaddr);
+                    }
+                 }
+             }
+
+          /* Enable the fractional divider */
+
+          regaddr = LPC313X_CGU_FDC(fdndx + dmn->fdiv1);
+          regval  = getreg32(regaddr);
+          regval |= CGU_FDC_RUN;
+          putreg32(regval, regaddr);
+        }
+    }
+
+  if (bcrndx != BCRNDX_INVALID)
+    {
+      /* Enable the BCR for domain */
+
+      regaddr = LPC313X_CGU_BCR(bcrndx);
+      putreg32(CGU_BCR_FDRUN, regaddr);
+    }
+
+   /* Select input base clock for domain*/
+
+  lpc313x_selectfreqin(dmn->dmnid, dmn->finsel);
+}
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: lpc313x_clkinit
+ *
+ * Description:
+ *   Initialize all clock domains based on board-specific clock configuration data
+ *
+ ************************************************************************************/
+
+void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
+{
+  struct lpc313x_domainconfig_s domain;
+
+  /* Reset all clocks and connect them to FFAST */
+
+  lpc313x_resetclks();
+
+  /* Initialize Domain0 = SYS_BASE clocks */
+
+  domain.dmnid  = DOMAINID_SYS;
+  domain.finsel = cfg->domain0.finsel;
+  domain.clk1   = CLKID_SYSBASE_FIRST;
+  domain.nclks  = (CLKID_SYSBASE_LAST - CLKID_SYSBASE_FIRST) + 1;
+  domain.fdiv1  = FRACDIV_BASE0_LOW;
+  domain.nfdiv  = FRACDIV_BASE0_CNT;
+  domain.sub    = cfg->domain0.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain1 = AHB0APB0_BASE clocks */
+
+  domain.dmnid  = DOMAINID_AHB0APB0;
+  domain.finsel = cfg->domain1.finsel;
+  domain.clk1   = CLKID_AHB0APB0_FIRST;
+  domain.nclks  = (CLKID_AHB0APB0_LAST - CLKID_AHB0APB0_FIRST) + 1;
+  domain.fdiv1  = FRACDIV_BASE1_LOW;
+  domain.nfdiv  = FRACDIV_BASE1_CNT;
+  domain.sub    = cfg->domain1.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain2 = AHB0APB1_BASE clocks */
+
+  domain.dmnid  = DOMAINID_AHB0APB1;
+  domain.finsel = cfg->domain2.finsel;
+  domain.clk1   = CLKID_AHB0APB1_FIRST;
+  domain.nclks  = (CLKID_AHB0APB1_LAST - CLKID_AHB0APB1_FIRST) + 1;
+  domain.fdiv1  = FRACDIV_BASE2_LOW;
+  domain.nfdiv  = FRACDIV_BASE2_CNT;
+  domain.sub    = cfg->domain2.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain3 = AHB0APB2_BASE clocks */
+
+  domain.dmnid  = DOMAINID_AHB0APB2;
+  domain.finsel = cfg->domain3.finsel;
+  domain.clk1   = CLKID_AHB0APB2_FIRST;
+  domain.nclks  = (CLKID_AHB0APB2_LAST - CLKID_AHB0APB2_FIRST) + 1;
+  domain.fdiv1  = FRACDIV_BASE3_LOW;
+  domain.nfdiv  = FRACDIV_BASE3_CNT;
+  domain.sub    = cfg->domain3.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain4 = AHB0APB3_BASE clocks */
+
+  domain.dmnid  = DOMAINID_AHB0APB3;
+  domain.finsel = cfg->domain4.finsel;
+  domain.clk1   = CLKID_AHB0APB3_FIRST;
+  domain.nclks  = (CLKID_AHB0APB3_LAST - CLKID_AHB0APB3_FIRST) + 1;
+  domain.fdiv1  = FRACDIV_BASE4_LOW;
+  domain.nfdiv  = FRACDIV_BASE4_CNT;
+  domain.sub    = cfg->domain4.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain5 = PCM_BASE clocks */
+
+  domain.dmnid  = DOMAINID_PCM;
+  domain.finsel = cfg->domain5.finsel;
+  domain.clk1   = CLKID_PCM_FIRST;
+  domain.nclks  = 1;
+  domain.fdiv1  = FRACDIV_BASE5_LOW;
+  domain.nfdiv  = FRACDIV_BASE5_CNT;
+  domain.sub    = cfg->domain5.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain6 = UART_BASE clocks */
+
+  domain.dmnid  = DOMAINID_UART;
+  domain.finsel = cfg->domain6.finsel;
+  domain.clk1   = CLKID_UART_FIRST;
+  domain.nclks  = 1;
+  domain.fdiv1  = FRACDIV_BASE6_LOW;
+  domain.nfdiv  = FRACDIV_BASE6_CNT;
+  domain.sub    = cfg->domain6.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain7 = CLK1024FS_BASE clocks */
+
+  domain.dmnid  = DOMAINID_CLK1024FS;
+  domain.finsel = cfg->domain7.finsel;
+  domain.clk1   = CLKID_CLK1024FS_FIRST;
+  domain.nclks  = (CLKID_CLK1024FS_LAST - CLKID_CLK1024FS_FIRST) + 1;
+  domain.fdiv1  = FRACDIV_BASE7_LOW;
+  domain.nfdiv  = FRACDIV_BASE7_CNT;
+  domain.sub    = cfg->domain7.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain8 = I2SRX_BCK0_BASE clocks */
+
+  lpc313x_selectfreqin(DOMAINID_BCK0, cfg->domain8.finsel);
+
+  /* Initialize Domain9 = I2SRX_BCK1_BASE clocks */
+
+  lpc313x_selectfreqin(DOMAINID_BCK1, cfg->domain9.finsel);
+
+  /* Initialize Domain10 = SPI_BASE clocks */
+
+  domain.dmnid  = DOMAINID_SPI;
+  domain.finsel = cfg->domain10.finsel;
+  domain.clk1   = CLKID_SPI_FIRST;
+  domain.nclks  = (CLKID_SPI_LAST - CLKID_SPI_FIRST) + 1;
+  domain.fdiv1  = FRACDIV_BASE10_LOW;
+  domain.nfdiv  = FRACDIV_BASE10_CNT;
+  domain.sub    = cfg->domain10.sub;
+  lpc313x_domaininit(&domain);
+
+  /* Initialize Domain11 = SYSCLK_O_BASE clocks */
+
+  lpc313x_selectfreqin(DOMAINID_SYSCLKO, cfg->domain11.finsel);
+
+  /* Initialize Dynamic fractional dividers -- to be provided */
+}