diff options
author | Gregory Nutt <gnutt@nuttx.org> | 2013-06-08 13:50:42 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-06-08 13:50:42 -0600 |
commit | deddc0a6ad28790f320f350ec6f05469383aaa61 (patch) | |
tree | 85dcbe9bb8673cb87ccbd8f8bc708bd9ddf498ce /nuttx/arch/arm/src/sam34 | |
parent | 34883eb13062a89212ad44e9cb2245b89ab80087 (diff) | |
download | px4-nuttx-deddc0a6ad28790f320f350ec6f05469383aaa61.tar.gz px4-nuttx-deddc0a6ad28790f320f350ec6f05469383aaa61.tar.bz2 px4-nuttx-deddc0a6ad28790f320f350ec6f05469383aaa61.zip |
SAM3U/4L changes to hide differences by clocking in those MCUs
Diffstat (limited to 'nuttx/arch/arm/src/sam34')
-rw-r--r-- | nuttx/arch/arm/src/sam34/Kconfig | 9 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h (renamed from nuttx/arch/arm/src/sam34/chip/sam_pmc.h) | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_uart.h | 8 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam4l_usart.h | 14 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_clockconfig.c | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_periphclks.h | 149 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam4l_periphclks.c | 12 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam4l_periphclks.h | 6 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_dmac.c | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_gpioirq.c | 13 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_hsmci.c | 6 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_lowputc.c | 68 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_serial.c | 21 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_spi.c | 33 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_timerisr.c | 18 |
15 files changed, 299 insertions, 72 deletions
diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index 26e8bb017..7c7d75ba4 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -362,6 +362,15 @@ config SAM34_HSMCI endmenu +config SAM32_RESET_PERIPHCLKS + bool "Enable all peripheral clocks on reset" + default n + depends on ARCH_CHIP_SAM4L + ---help--- + By default, only a few necessary peripheral clocks are enabled at + reset. If this setting is enabled, then all clocking will be enabled + to all of the selected peripherals on reset. + comment "AT91SAM3/4 USART Configuration" config USART0_ISUART diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h index f6a98e3ee..762110081 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_pmc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -1,5 +1,5 @@ /**************************************************************************************** - * arch/arm/src/sam34/chip/sam_pmc.h + * arch/arm/src/sam34/chip/sam3u_pmc.h * * Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -33,8 +33,8 @@ * ****************************************************************************************/ -#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H -#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H +#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H +#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H /**************************************************************************************** * Included Files @@ -312,4 +312,4 @@ * Public Functions ****************************************************************************************/ -#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H */ +#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h b/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h index 2278fa656..bd2dc23c2 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_uart.h @@ -107,7 +107,7 @@ #define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET) #define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET) #define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) #define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) @@ -126,7 +126,7 @@ #define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET) #define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET) #define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) #define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) @@ -145,7 +145,7 @@ #define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET) #define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET) #define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) #define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) @@ -164,7 +164,7 @@ #define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET) #define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET) #define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) #define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) diff --git a/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h b/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h index 42e1c02b6..f7fb7e357 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4l_usart.h @@ -103,7 +103,7 @@ #define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET) #define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET) #define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET) #define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET) @@ -125,7 +125,7 @@ #define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET) #define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET) #define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET) #define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET) @@ -147,7 +147,7 @@ #define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET) #define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET) #define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET) #define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET) @@ -169,7 +169,7 @@ #define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET) #define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET) -#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET) +#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET) #define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET) #define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET) #define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET) @@ -231,9 +231,9 @@ # define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */ #define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */ #define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT) -# define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */ -# define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */ -# define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */ +# define UART_MR_USCLKS_USART (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART */ +# define UART_MR_USCLKS_USARTDIV (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART/DIV(1) */ +# define UART_MR_USCLKS_CLK (0 << UART_MR_USCLKS_SHIFT) /* CLK */ #define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */ #define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT) # define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */ diff --git a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c index 4f8ff273d..9470c3aa0 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c +++ b/nuttx/arch/arm/src/sam34/sam3u_clockconfig.c @@ -49,7 +49,7 @@ #include "up_internal.h" #include "sam_clockconfig.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam3u_eefc.h" #include "chip/sam3u_wdt.h" #include "chip/sam3u_supc.h" diff --git a/nuttx/arch/arm/src/sam34/sam3u_periphclks.h b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h new file mode 100644 index 000000000..0facf690a --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h @@ -0,0 +1,149 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam3u_periphclks.h + * + * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <arch/irq.h> +#include "chip/sam3u_pmc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helper macros */ + +#define sam_enableperipheral(s) putreg32((1 << (s)), SAM_PMC_PCER) +#define sam_disableperipheral(s) putreg32((1 << (s)), SAM_PMC_PDER) + +#define sam_supc_enableclk() sam_enableperipheral(SAM_PID_SUPC) +#define sam_rstc_enableclk() sam_enableperipheral(SAM_PID_RSTC) +#define sam_rtc_enableclk() sam_enableperipheral(SAM_PID_RTC) +#define sam_rtt_enableclk() sam_enableperipheral(SAM_PID_RTT) +#define sam_wdt_enableclk() sam_enableperipheral(SAM_PID_WDT) +#define sam_pmc_enableclk() sam_enableperipheral(SAM_PID_PMC) +#define sam_eefc0_enableclk() sam_enableperipheral(SAM_PID_EEFC0) +#define sam_eefc1_enableclk() sam_enableperipheral(SAM_PID_EEFC1) +#define sam_uart_enableclk() sam_enableperipheral(SAM_PID_UART) +#define sam_smc_enableclk() sam_enableperipheral(SAM_PID_SMC) +#define sam_pioa_enableclk() sam_enableperipheral(SAM_PID_PIOA) +#define sam_piob_enableclk() sam_enableperipheral(SAM_PID_PIOB) +#define sam_pioc_enableclk() sam_enableperipheral(SAM_PID_PIOC) +#define sam_usart0_enableclk() sam_enableperipheral(SAM_PID_USART0) +#define sam_usart1_enableclk() sam_enableperipheral(SAM_PID_USART1) +#define sam_usart2_enableclk() sam_enableperipheral(SAM_PID_USART2) +#define sam_usart3_enableclk() sam_enableperipheral(SAM_PID_USART3) +#define sam_hsmci_enableclk() sam_enableperipheral(SAM_PID_HSMCI) +#define sam_twi0_enableclk() sam_enableperipheral(SAM_PID_TWI0) +#define sam_twi1_enableclk() sam_enableperipheral(SAM_PID_TWI1) +#define sam_spi_enableclk() sam_enableperipheral(SAM_PID_SPI) +#define sam_ssc_enableclk() sam_enableperipheral(SAM_PID_SSC) +#define sam_tc0_enableclk() sam_enableperipheral(SAM_PID_TC0) +#define sam_tc1_enableclk() sam_enableperipheral(SAM_PID_TC1) +#define sam_tc2_enableclk() sam_enableperipheral(SAM_PID_TC2) +#define sam_pwm_enableclk() sam_enableperipheral(SAM_PID_PWM) +#define sam_adc12b_enableclk() sam_enableperipheral(SAM_PID_ADC12B) +#define sam_dmac_enableclk() sam_enableperipheral(SAM_PID_DMAC) +#define sam_udphs_enableclk() sam_enableperipheral(SAM_PID_UDPHS) + +#define sam_supc_disableclk() sam_disableperipheral(SAM_PID_SUPC) +#define sam_rstc_disableclk() sam_disableperipheral(SAM_PID_RSTC) +#define sam_rtc_disableclk() sam_disableperipheral(SAM_PID_RTC) +#define sam_rtt_disableclk() sam_disableperipheral(SAM_PID_RTT) +#define sam_wdt_disableclk() sam_disableperipheral(SAM_PID_WDT) +#define sam_pmc_disableclk() sam_disableperipheral(SAM_PID_PMC) +#define sam_eefc0_disableclk() sam_disableperipheral(SAM_PID_EEFC0) +#define sam_eefc1_disableclk() sam_disableperipheral(SAM_PID_EEFC1) +#define sam_uart_disableclk() sam_disableperipheral(SAM_PID_UART) +#define sam_smc_disableclk() sam_disableperipheral(SAM_PID_SMC) +#define sam_pioa_disableclk() sam_disableperipheral(SAM_PID_PIOA) +#define sam_piob_disableclk() sam_disableperipheral(SAM_PID_PIOB) +#define sam_pioc_disableclk() sam_disableperipheral(SAM_PID_PIOC) +#define sam_usart0_disableclk() sam_disableperipheral(SAM_PID_USART0) +#define sam_usart1_disableclk() sam_disableperipheral(SAM_PID_USART1) +#define sam_usart2_disableclk() sam_disableperipheral(SAM_PID_USART2) +#define sam_usart3_disableclk() sam_disableperipheral(SAM_PID_USART3) +#define sam_hsmci_disableclk() sam_disableperipheral(SAM_PID_HSMCI) +#define sam_twi0_disableclk() sam_disableperipheral(SAM_PID_TWI0) +#define sam_twi1_disableclk() sam_disableperipheral(SAM_PID_TWI1) +#define sam_spi_disableclk() sam_disableperipheral(SAM_PID_SPI) +#define sam_ssc_disableclk() sam_disableperipheral(SAM_PID_SSC) +#define sam_tc0_disableclk() sam_disableperipheral(SAM_PID_TC0) +#define sam_tc1_disableclk() sam_disableperipheral(SAM_PID_TC1) +#define sam_tc2_disableclk() sam_disableperipheral(SAM_PID_TC2) +#define sam_pwm_disableclk() sam_disableperipheral(SAM_PID_PWM) +#define sam_adc12b_disableclk() sam_disableperipheral(SAM_PID_ADC12B) +#define sam_dmac_disableclk() sam_disableperipheral(SAM_PID_DMAC) +#define sam_udphs_disableclk() sam_disableperipheral(SAM_PID_UDPHS) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c index a346a233d..2c55ab6b0 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.c +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.c @@ -105,9 +105,11 @@ static inline void sam_init_cpumask(void) /* OR in the user selected peripherals */ +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS #ifdef CONFIG_SAM34_OCD mask |= PM_CPUMASK_OCD; /* On-Chip Debug */ #endif +#endif /* Save the new CPU mask */ @@ -134,6 +136,7 @@ static inline void sam_init_hsbmask(void) /* OR in the user selected peripherals */ +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS #ifdef CONFIG_SAM34_PDCA mask |= PM_HSBMASK_PDCA; /* PDCA */ #endif @@ -152,6 +155,7 @@ static inline void sam_init_hsbmask(void) #ifdef CONFIG_SAM34_AESA mask |= PM_HSBMASK_AESA; /* AESA */ #endif +#endif /* Save the new HSB mask */ @@ -178,6 +182,7 @@ static inline void sam_init_pbamask(void) /* OR in the user selected peripherals */ +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS #ifdef CONFIG_SAM34_IISC mask |= PM_PBAMASK_IISC; /* IISC */ #endif @@ -253,6 +258,7 @@ static inline void sam_init_pbamask(void) #ifdef CONFIG_SAM34_LCDCA mask |= PM_PBAMASK_LCDCA; /* LCDCA*/ #endif +#endif /* Save the new PBA mask */ @@ -284,6 +290,7 @@ static inline void sam_init_pbbmask(void) /* OR in the user selected peripherals */ +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS #ifdef CONFIG_SAM34_HRAMC1 mask |= PM_PBBMASK_HRAMC1; /* HRAMC1 */ #endif @@ -302,6 +309,7 @@ static inline void sam_init_pbbmask(void) #ifdef CONFIG_SAM34_PEVC mask |= PM_PBBMASK_PEVC; /* PEVC */ #endif +#endif /* Save the new PBB mask */ @@ -327,12 +335,14 @@ static inline void sam_init_pbcmask(void) /* OR in the user selected peripherals */ +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS #ifdef CONFIG_SAM34_CHIPID mask |= PM_PBCMASK_CHIPID; /* CHIPID */ #endif #ifdef CONFIG_SAM34_FREQM mask |= PM_PBCMASK_FREQM; /* FREQM */ #endif +#endif /* Save the new PBC mask */ @@ -358,6 +368,7 @@ static inline void sam_init_pbdmask(void) /* OR in the user selected peripherals */ +#ifdef CONFIG_SAM32_RESET_PERIPHCLKS #ifdef CONFIG_SAM34_AST mask |= PM_PBDMASK_AST; /* AST */ #endif @@ -370,6 +381,7 @@ static inline void sam_init_pbdmask(void) #ifdef CONFIG_SAM34_PICOUART mask |= PM_PBDMASK_PICOUART; /* PICOUART */ #endif +#endif /* Save the new PBD mask */ diff --git a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h index 620942940..f7509e278 100644 --- a/nuttx/arch/arm/src/sam34/sam4l_periphclks.h +++ b/nuttx/arch/arm/src/sam34/sam4l_periphclks.h @@ -42,6 +42,8 @@ #include <nuttx/config.h> +#include "chip/sam4l_pm.h" + #ifdef CONFIG_ARCH_CHIP_SAM4L /************************************************************************************ @@ -92,13 +94,13 @@ #define sam_usart0_enableclk() \ do { \ sam_pba_enableperipheral(PM_PBAMASK_USART0); \ - sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \ + sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \ } while (0) #define sam_usart1_enableclk() \ do { \ sam_pba_enableperipheral(PM_PBAMASK_USART1); \ - sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \ + sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \ } while (0) #define sam_usart2_enableclk() \ diff --git a/nuttx/arch/arm/src/sam34/sam_dmac.c b/nuttx/arch/arm/src/sam34/sam_dmac.c index b11199fb1..4f6ede437 100644 --- a/nuttx/arch/arm/src/sam34/sam_dmac.c +++ b/nuttx/arch/arm/src/sam34/sam_dmac.c @@ -56,7 +56,7 @@ #include "chip.h" #include "sam_dmac.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_dmac.h" /**************************************************************************** @@ -1160,7 +1160,7 @@ void weak_function up_dmainitialize(void) { /* Enable peripheral clock */ - putreg32((1 << SAM_PID_DMAC), SAM_PMC_PCER); + sam_dmac_enableclk(); /* Disable all DMA interrupts */ diff --git a/nuttx/arch/arm/src/sam34/sam_gpioirq.c b/nuttx/arch/arm/src/sam34/sam_gpioirq.c index c9fcc0ca8..395578bfd 100644 --- a/nuttx/arch/arm/src/sam34/sam_gpioirq.c +++ b/nuttx/arch/arm/src/sam34/sam_gpioirq.c @@ -55,7 +55,7 @@ #include "sam_gpio.h" #include "chip/sam3u_pio.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #ifdef CONFIG_GPIO_IRQ @@ -209,15 +209,12 @@ static int up_gpiocinterrupt(int irq, void *context) void sam_gpioirqinitialize(void) { - uint32_t pcer; - /* Configure GPIOA interrupts */ #ifdef CONFIG_GPIOA_IRQ /* Enable GPIOA clocking */ - pcer |= (1 << SAM_PID_PIOA); - putreg32(pcer, SAM_PMC_PCER); + sam_pioa_enableclk(); /* Clear and disable all GPIOA interrupts */ @@ -235,8 +232,7 @@ void sam_gpioirqinitialize(void) #ifdef CONFIG_GPIOB_IRQ /* Enable GPIOB clocking */ - pcer |= (1 << SAM_PID_PIOB); - putreg32(pcer, SAM_PMC_PCER); + sam_piob_enableclk(); /* Clear and disable all GPIOB interrupts */ @@ -254,8 +250,7 @@ void sam_gpioirqinitialize(void) #ifdef CONFIG_GPIOC_IRQ /* Enable GPIOC clocking */ - pcer |= (1 << SAM_PID_PIOC); - putreg32(pcer, SAM_PMC_PCER); + sam_pioc_enableclk(); /* Clear and disable all GPIOC interrupts */ diff --git a/nuttx/arch/arm/src/sam34/sam_hsmci.c b/nuttx/arch/arm/src/sam34/sam_hsmci.c index f9ee665a8..6df8610cb 100644 --- a/nuttx/arch/arm/src/sam34/sam_hsmci.c +++ b/nuttx/arch/arm/src/sam34/sam_hsmci.c @@ -64,7 +64,7 @@ #include "sam_dmac.h" #include "sam_hsmci.h" #include "chip/sam_dmac.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_hsmci.h" #include "chip/sam_pinmap.h" @@ -667,7 +667,7 @@ static inline void sam_enable(void) { /* Enable the MCI peripheral clock */ - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER); + sam_hsmci_enableclk(); /* Enable the MCI and the Power Saving */ @@ -1223,7 +1223,7 @@ static void sam_reset(FAR struct sdio_dev_s *dev) /* Enable the MCI clock */ flags = irqsave(); - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER); + sam_hsmci_enableclk(); fdbg("PCSR: %08x\n", getreg32(SAM_PMC_PCSR)); /* Reset the MCI */ diff --git a/nuttx/arch/arm/src/sam34/sam_lowputc.c b/nuttx/arch/arm/src/sam34/sam_lowputc.c index 76a76bd00..b09e18e2b 100644 --- a/nuttx/arch/arm/src/sam34/sam_lowputc.c +++ b/nuttx/arch/arm/src/sam34/sam_lowputc.c @@ -49,12 +49,13 @@ #include "sam_gpio.h" #include "sam_lowputc.h" -#include "chip/sam_pmc.h" #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_uart.h" +# include "sam3u_periphclks.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_usart.h" +# include "sam4l_periphclks.h" #else # error Unknown UART #endif @@ -125,6 +126,23 @@ # undef HAVE_CONSOLE #endif +/* Select MCU-specific settings + * + * For the SAM3U, the USARTs are driven by the main clock. + * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is + * selected by the PBADIVMASK register. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +# define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */ +# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */ +#else +# error Unrecognized SAM architecture +#endif + /* Select USART parameters for the selected console */ #if defined(CONFIG_UART_SERIAL_CONSOLE) @@ -191,7 +209,7 @@ # define MR_NBSTOP_VALUE UART_MR_NBSTOP_1 #endif -#define MR_VALUE (UART_MR_MODE_NORMAL | UART_MR_USCLKS_MCK | \ +#define MR_VALUE (UART_MR_MODE_NORMAL | SAM_MR_USCLKS | \ MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE) /************************************************************************** @@ -249,27 +267,23 @@ void up_lowputc(char ch) void sam_lowsetup(void) { - uint32_t regval; - /* Enable clocking for all selected UART/USARTs */ - regval = 0; #ifdef CONFIG_SAM34_UART - regval |= (1 << SAM_PID_UART); + sam_uart_enableclk(); #endif #ifdef CONFIG_SAM34_USART0 - regval |= (1 << SAM_PID_USART0); + sam_usart0_enableclk(); #endif #ifdef CONFIG_SAM34_USART1 - regval |= (1 << SAM_PID_USART1); + sam_usart1_enableclk(); #endif #ifdef CONFIG_SAM34_USART2 - regval |= (1 << SAM_PID_USART2); + sam_usart2_enableclk(); #endif #ifdef CONFIG_SAM34_USART3 - regval |= (1 << SAM_PID_USART3); + sam_usart3_enableclk(); #endif - putreg32(regval, SAM_PMC_PCER); /* Configure UART pins for all selected UART/USARTs */ @@ -277,41 +291,49 @@ void sam_lowsetup(void) (void)sam_configgpio(GPIO_UART_RXD); (void)sam_configgpio(GPIO_UART_TXD); #endif + #ifdef CONFIG_SAM34_USART0 (void)sam_configgpio(GPIO_USART0_RXD); (void)sam_configgpio(GPIO_USART0_TXD); +#ifdef CONFIG_USART0_OFLOWCONTROL (void)sam_configgpio(GPIO_USART0_CTS); +#endif +#ifdef CONFIG_USART0_IFLOWCONTROL (void)sam_configgpio(GPIO_USART0_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART1 (void)sam_configgpio(GPIO_USART1_RXD); (void)sam_configgpio(GPIO_USART1_TXD); +#ifdef CONFIG_USART1_OFLOWCONTROL (void)sam_configgpio(GPIO_USART1_CTS); +#endif +#ifdef CONFIG_USART1_IFLOWCONTROL (void)sam_configgpio(GPIO_USART1_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART2 (void)sam_configgpio(GPIO_USART2_RXD); (void)sam_configgpio(GPIO_USART2_TXD); +#ifdef CONFIG_USART2_OFLOWCONTROL (void)sam_configgpio(GPIO_USART2_CTS); +#endif +#ifdef CONFIG_USART2_IFLOWCONTROL (void)sam_configgpio(GPIO_USART2_RTS); #endif +#endif + #ifdef CONFIG_SAM34_USART3 (void)sam_configgpio(GPIO_USART3_RXD); (void)sam_configgpio(GPIO_USART3_TXD); +#ifdef CONFIG_USART3_OFLOWCONTROL (void)sam_configgpio(GPIO_USART3_CTS); - (void)sam_configgpio(GPIO_USART3_RTS); -#endif - -#ifdef GPIO_CONSOLE_RXD -#endif -#ifdef GPIO_CONSOLE_TXD - (void)sam_configgpio(GPIO_CONSOLE_TXD); #endif -#ifdef GPIO_CONSOLE_CTS - (void)sam_configgpio(GPIO_CONSOLE_CTS); +#ifdef CONFIG_USART3_IFLOWCONTROL + (void)sam_configgpio(GPIO_USART3_RTS); #endif -#ifdef GPIO_CONSOLE_RTS - (void)sam_configgpio(GPIO_CONSOLE_RTS); #endif /* Configure the console (only) */ @@ -331,7 +353,7 @@ void sam_lowsetup(void) /* Configure the console baud */ - putreg32(((SAM_MCK_FREQUENCY + (SAM_CONSOLE_BAUD << 3))/(SAM_CONSOLE_BAUD << 4)), + putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)), SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET); /* Enable receiver & transmitter */ diff --git a/nuttx/arch/arm/src/sam34/sam_serial.c b/nuttx/arch/arm/src/sam34/sam_serial.c index cbe5ea039..72ee144d1 100644 --- a/nuttx/arch/arm/src/sam34/sam_serial.c +++ b/nuttx/arch/arm/src/sam34/sam_serial.c @@ -551,6 +551,23 @@ # endif #endif +/* Select MCU-specific settings + * + * For the SAM3U, the USARTs are driven by the main clock. + * For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is + * selected by the PBADIVMASK register. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ +# define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */ +# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */ +#else +# error Unrecognized SAM architecture +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -879,7 +896,7 @@ static int up_setup(struct uart_dev_s *dev) * as the timing source */ - regval = (UART_MR_MODE_NORMAL | UART_MR_USCLKS_MCK); + regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS); /* OR in settings for the selected number of bits */ @@ -944,7 +961,7 @@ static int up_setup(struct uart_dev_s *dev) /* Configure the console baud */ - regval = (SAM_MCK_FREQUENCY + (priv->baud << 3))/(priv->baud << 4); + regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4); up_serialout(priv, SAM_UART_BRGR_OFFSET, regval); /* Enable receiver & transmitter */ diff --git a/nuttx/arch/arm/src/sam34/sam_spi.c b/nuttx/arch/arm/src/sam34/sam_spi.c index 10395ec90..b1dae4e34 100644 --- a/nuttx/arch/arm/src/sam34/sam_spi.c +++ b/nuttx/arch/arm/src/sam34/sam_spi.c @@ -57,7 +57,7 @@ #include "chip.h" #include "sam_gpio.h" #include "sam_spi.h" -#include "chip/sam_pmc.h" +#include "chip/sam3u_pmc.h" #include "chip/sam_spi.h" #include "chip/sam_pinmap.h" @@ -66,6 +66,19 @@ /**************************************************************************** * Definitions ****************************************************************************/ +/* Select MCU-specific settings + * + * For the SAM3U, SPI is driven by the main clock. + * For the SAM4L, SPI driven by CLK_SPI which is the PBB clock. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SPI_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_SPI_CLOCK BOARD_PBB_FREQUENCY /* PBA frequency */ +#else +# error Unrecognized SAM architecture +#endif /* Check if SPI debut is enabled (non-standard.. no support in * include/debug.h @@ -461,7 +474,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * SPCK frequency = MCK / SCBR, or SCBR = MCK / frequency */ - scbr = SAM_MCK_FREQUENCY / frequency; + scbr = SAM_SPI_CLOCK / frequency; if (scbr < 8) { @@ -493,7 +506,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * DLYBS = MCK * 0.000002 = MCK / 500000 */ - dlybs = SAM_MCK_FREQUENCY / 500000; + dlybs = SAM_SPI_CLOCK / 500000; regval |= dlybs << SPI_CSR_DLYBS_SHIFT; /* DLYBCT: Delay Between Consecutive Transfers. This field defines the delay @@ -508,13 +521,13 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) * DLYBCT = MCK * 0.000005 / 32 = MCK / 200000 / 32 */ - dlybct = SAM_MCK_FREQUENCY / 200000 / 32; + dlybct = SAM_SPI_CLOCK / 200000 / 32; regval |= dlybct << SPI_CSR_DLYBCT_SHIFT; putreg32(regval, regaddr); /* Calculate the new actual frequency */ - actual = SAM_MCK_FREQUENCY / scbr; + actual = SAM_SPI_CLOCK / scbr; spivdbg("csr[%08x]=%08x actual=%d\n", regaddr, regval, actual); /* Save the frequency setting */ @@ -897,15 +910,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port) priv->cs = 0xff; - /* Apply power to the SPI block */ + /* Enable clocking to the SPI block */ - flags = irqsave(); - regval = getreg32(SAM_PMC_PCER); - regval |= (1 << SAM_PID_SPI); -#ifdef CONFIG_SAM34_SPIINTERRUPT - regval |= (1 << SAM_IRQ_SPI); -#endif - putreg32(regval, SAM_PMC_PCER); + sam_spi_enableclk(); /* Configure multiplexed pins as connected on the board. Chip select pins * must be configured by board-specific logic. diff --git a/nuttx/arch/arm/src/sam34/sam_timerisr.c b/nuttx/arch/arm/src/sam34/sam_timerisr.c index e1879d5cc..2a1d0558c 100644 --- a/nuttx/arch/arm/src/sam34/sam_timerisr.c +++ b/nuttx/arch/arm/src/sam34/sam_timerisr.c @@ -55,6 +55,20 @@ /**************************************************************************** * Definitions ****************************************************************************/ +/* Select MCU-specific settings + * + * For the SAM3U, Systick is driven by the main clock. + * For the SAM4L, Systick is driven by the CPU clock which is just the main + * clock divided down. + */ + +#if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SYSTICK_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* PBA frequency is undivided */ +#else +# error Unrecognized SAM architecture +#endif /* The desired timer interrupt frequency is provided by the definition * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of @@ -69,9 +83,9 @@ #undef CONFIG_SAM34_SYSTICK_HCLKd8 /* Power up default is MCK, not MCK/8 */ #if CONFIG_SAM34_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value |