diff options
author | Gregory Nutt <gnutt@nuttx.org> | 2013-06-11 15:42:30 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-06-11 15:42:30 -0600 |
commit | a02c2a71d8b694921bbcd506508a9f7dbaa1e89f (patch) | |
tree | 9fc87ea5638417d4db1d3ecd0ae20c0dd8d8b570 /nuttx/arch/arm | |
parent | 190ecc0e601b476d93280bbb5550e9588dff3011 (diff) | |
download | px4-nuttx-a02c2a71d8b694921bbcd506508a9f7dbaa1e89f.tar.gz px4-nuttx-a02c2a71d8b694921bbcd506508a9f7dbaa1e89f.tar.bz2 px4-nuttx-a02c2a71d8b694921bbcd506508a9f7dbaa1e89f.zip |
SAM4S: Add macros to manage peripheral clocks
Diffstat (limited to 'nuttx/arch/arm')
-rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h | 20 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_periphclks.h | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam4s_periphclks.h | 157 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_hsmci.c | 3 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_lowputc.c | 2 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_serial.c | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/sam34/sam_timerisr.c | 4 |
7 files changed, 180 insertions, 12 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h index 4f26b83d9..1eebd7df5 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -56,9 +56,15 @@ #define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */ #define SAM_PMC_SCSR_OFFSET 0x0008 /* System Clock Status Register */ /* 0x000c: Reserved */ -#define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ -#define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ -#define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER0_OFFSET 0x0010 /* Peripheral Clock Enable Register 0 */ +# define SAM_PMC_PCDR0_OFFSET 0x0014 /* Peripheral Clock Disable Register 0 */ +# define SAM_PMC_PCSR0_OFFSET 0x0018 /* Peripheral Clock Status Register 0 */ +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_PCER_OFFSET 0x0010 /* Peripheral Clock Enable Register */ +# define SAM_PMC_PCDR_OFFSET 0x0014 /* Peripheral Clock Disable Register */ +# define SAM_PMC_PCSR_OFFSET 0x0018 /* Peripheral Clock Status Register */ +#endif #if defined(CONFIG_ARCH_CHIP_SAM3U) # define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */ @@ -111,7 +117,13 @@ #define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET) #define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET) #define SAM_PMC_SCSR (SAM_PMC_BASE+SAM_PMC_SCSR_OFFSET) -#define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) + +#if defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_PMC_PCER0 (SAM_PMC_BASE+SAM_PMC_PCER0_OFFSET) +#elif defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_PMC_PCER (SAM_PMC_BASE+SAM_PMC_PCER_OFFSET) +#endif + #define SAM_PMC_PCDR (SAM_PMC_BASE+SAM_PMC_PCDR_OFFSET) #define SAM_PMC_PCSR (SAM_PMC_BASE+SAM_PMC_PCSR_OFFSET) diff --git a/nuttx/arch/arm/src/sam34/sam3u_periphclks.h b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h index 0b0466f8c..09c1abb4d 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_periphclks.h +++ b/nuttx/arch/arm/src/sam34/sam3u_periphclks.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sam34/sam3u_periphclks.h * - * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * Redistribution and use in source and binary forms, with or without diff --git a/nuttx/arch/arm/src/sam34/sam4s_periphclks.h b/nuttx/arch/arm/src/sam34/sam4s_periphclks.h new file mode 100644 index 000000000..d3e7be326 --- /dev/null +++ b/nuttx/arch/arm/src/sam34/sam4s_periphclks.h @@ -0,0 +1,157 @@ +/************************************************************************************ + * arch/arm/src/sam34/sam4s_periphclks.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H +#define __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> +#include <stdint.h> +#include <arch/irq.h> +#include "chip/sam4s_pmc.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helper macros */ + +#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) +#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) +#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0) +#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1) + +#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC) +#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC) +#define sam_rtc_enableclk() sam_enableperiph0(SAM_PID_RTC) +#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT) +#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT) +#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC) +#define sam_eefc0_enableclk() sam_enableperiph0(SAM_PID_EEFC0) +#define sam_eefc1_enableclk() sam_enableperiph0(SAM_PID_EEFC1) +#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0) +#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1) +#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC) +#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA) +#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB) +#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC) +#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0) +#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1) +#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI) +#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0) +#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1) +#define sam_ssc_enableclk() sam_enableperiph0(SAM_PID_SSC) +#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0) +#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1) +#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2) +#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3) +#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4) +#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5) +#define sam_adc12b_enableclk() sam_enableperiph0(SAM_PID_ADC12B) +#define sam_dacc_enableclk() sam_enableperiph0(SAM_PID_DACC) +#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM) +#define sam_crccu_enableclk() sam_enableperiph1(SAM_PID_CRCCU) +#define sam_acc_enableclk() sam_enableperiph1(SAM_PID_ACC) +#define sam_udp_enableclk() sam_enableperiph1(SAM_PID_UDP) + +#define sam_supc_disableclk() sam_disableperiph0(SAM_PID_SUPC) +#define sam_rstc_disableclk() sam_disableperiph0(SAM_PID_RSTC) +#define sam_rtc_disableclk() sam_disableperiph0(SAM_PID_RTC) +#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT) +#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT) +#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC) +#define sam_eefc0_disableclk() sam_disableperiph0(SAM_PID_EEFC0) +#define sam_eefc1_disableclk() sam_disableperiph0(SAM_PID_EEFC1) +#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0) +#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1) +#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC) +#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA) +#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB) +#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC) +#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0) +#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1) +#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI) +#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0) +#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1) +#define sam_ssc_disableclk() sam_disableperiph0(SAM_PID_SSC) +#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0) +#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1) +#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2) +#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3) +#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4) +#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5) +#define sam_adc12b_disableclk() sam_disableperiph0(SAM_PID_ADC) +#define sam_dacc_disableclk() sam_disableperiph0(SAM_PID_DACC) +#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM) +#define sam_crccu_disableclk() sam_disableperiph1(SAM_PID_CRCCU) +#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC) +#define sam_udp_disableclk() sam_disableperiph1(SAM_PID_UDP) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H */ diff --git a/nuttx/arch/arm/src/sam34/sam_hsmci.c b/nuttx/arch/arm/src/sam34/sam_hsmci.c index 6df8610cb..f44d9fbba 100644 --- a/nuttx/arch/arm/src/sam34/sam_hsmci.c +++ b/nuttx/arch/arm/src/sam34/sam_hsmci.c @@ -644,7 +644,7 @@ static inline void sam_disable(void) { /* Disable the MCI peripheral clock */ - putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCDR); + sam_hsmci_disableclk(); /* Disable the MCI */ @@ -1224,7 +1224,6 @@ static void sam_reset(FAR struct sdio_dev_s *dev) flags = irqsave(); sam_hsmci_enableclk(); - fdbg("PCSR: %08x\n", getreg32(SAM_PMC_PCSR)); /* Reset the MCI */ diff --git a/nuttx/arch/arm/src/sam34/sam_lowputc.c b/nuttx/arch/arm/src/sam34/sam_lowputc.c index 0ed02235a..b206a2d94 100644 --- a/nuttx/arch/arm/src/sam34/sam_lowputc.c +++ b/nuttx/arch/arm/src/sam34/sam_lowputc.c @@ -150,7 +150,7 @@ * selected by the PBADIVMASK register. */ -#if defined(CONFIG_ARCH_CHIP_SAM3U) +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) # define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ # define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */ #elif defined(CONFIG_ARCH_CHIP_SAM4L) diff --git a/nuttx/arch/arm/src/sam34/sam_serial.c b/nuttx/arch/arm/src/sam34/sam_serial.c index dcc81ab0f..03a90006f 100644 --- a/nuttx/arch/arm/src/sam34/sam_serial.c +++ b/nuttx/arch/arm/src/sam34/sam_serial.c @@ -60,7 +60,7 @@ #include "os_internal.h" #include "chip.h" -#if defined(CONFIG_ARCH_CHIP_SAM3U) +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) # include "chip/sam3u_uart.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "chip/sam4l_usart.h" @@ -314,7 +314,7 @@ * selected by the PBADIVMASK register. */ -#if defined(CONFIG_ARCH_CHIP_SAM3U) +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) # define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */ # define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */ #elif defined(CONFIG_ARCH_CHIP_SAM4L) diff --git a/nuttx/arch/arm/src/sam34/sam_timerisr.c b/nuttx/arch/arm/src/sam34/sam_timerisr.c index 2a1d0558c..06466eed7 100644 --- a/nuttx/arch/arm/src/sam34/sam_timerisr.c +++ b/nuttx/arch/arm/src/sam34/sam_timerisr.c @@ -64,8 +64,8 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # define SAM_SYSTICK_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */ -#elif defined(CONFIG_ARCH_CHIP_SAM4L) -# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* PBA frequency is undivided */ +#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S) +# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* CPU frequency */ #else # error Unrecognized SAM architecture #endif |