Add mpmc initialization

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2459 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 141 insertions, 141 deletions

diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h b/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
index c2b8e12a1..ffd2899d2 100755
--- a/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
+++ b/nuttx/arch/arm/src/lpc313x/lpc313x_syscreg.h
@@ -213,157 +213,157 @@
 /* SYSCREG register (virtual) addresses *****************************************************************/
 /* Miscellaneous system configuration registers, part1 */
 
-define LPC313X_SYSCREG_EBIMPMCPRIO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIMPMCPRIO_OFFSET)
-define LPC313X_SYSCREG_EBNANDCPRIO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBNANDCPRIO_OFFSET)
-define LPC313X_SYSCREG_EBIUNUSEDPRIO             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIUNUSEDPRIO_OFFSET)
-define LPC313X_SYSCREG_RINGOSCCFG                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_RINGOSCCFG_OFFSET)
-define LPC313X_SYSCREG_ADCPDADC10BITS            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ADCPDADC10BITS_OFFSET)
-define LPC313X_SYSCREG_ABCCFG                    (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ABCCFG_OFFSET)
-define LPC313X_SYSCREG_SDMMCCFG                  (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_SDMMCCFG_OFFSET)
-define LPC313X_SYSCREG_MCIDELAYMODES             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MCIDELAYMODES_OFFSET)
+#define LPC313X_SYSCREG_EBIMPMCPRIO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIMPMCPRIO_OFFSET)
+#define LPC313X_SYSCREG_EBNANDCPRIO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBNANDCPRIO_OFFSET)
+#define LPC313X_SYSCREG_EBIUNUSEDPRIO            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_EBIUNUSEDPRIO_OFFSET)
+#define LPC313X_SYSCREG_RINGOSCCFG               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_RINGOSCCFG_OFFSET)
+#define LPC313X_SYSCREG_ADCPDADC10BITS           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ADCPDADC10BITS_OFFSET)
+#define LPC313X_SYSCREG_ABCCFG                   (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ABCCFG_OFFSET)
+#define LPC313X_SYSCREG_SDMMCCFG                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_SDMMCCFG_OFFSET)
+#define LPC313X_SYSCREG_MCIDELAYMODES            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MCIDELAYMODES_OFFSET)
 
 /* USB configuration registers */
 
-define LPC313X_SYSCREG_USB_ATXPLLPDREG           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_ATXPLLPDREG_OFFSET)
-define LPC313X_SYSCREG_USB_OTGCFG                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGCFG_OFFSET)
-define LPC313X_SYSCREG_USB_OTGPORTINDCTL         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGPORTINDCTL_OFFSET)
-define LPC313X_SYSCREG_USB_PLLNDEC               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLNDEC_OFFSET)
-define LPC313X_SYSCREG_USB_PLLMDEC               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLMDEC_OFFSET)
-define LPC313X_SYSCREG_USB_PLLPDEC               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLPDEC_OFFSET)
-define LPC313X_SYSCREG_USB_PLLSELR               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELR_OFFSET)
-define LPC313X_SYSCREG_USB_PLLSELI               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELI_OFFSET)
-define LPC313X_SYSCREG_USB_PLLSELP               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELP_OFFSET)
+#define LPC313X_SYSCREG_USB_ATXPLLPDREG          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_ATXPLLPDREG_OFFSET)
+#define LPC313X_SYSCREG_USB_OTGCFG               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGCFG_OFFSET)
+#define LPC313X_SYSCREG_USB_OTGPORTINDCTL        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_OTGPORTINDCTL_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLNDEC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLNDEC_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLMDEC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLMDEC_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLPDEC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLPDEC_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLSELR              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELR_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLSELI              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELI_OFFSET)
+#define LPC313X_SYSCREG_USB_PLLSELP              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_USB_PLLSELP_OFFSET)
 
 /* ISRAM/ISROM configuration registers */
 
-define LPC313X_SYSCREG_ISRAM0_LATENCYCFG         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM0_LATENCYCFG_OFFSET)
-define LPC313X_SYSCREG_ISRAM1_LATENCYCFG         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM1_LATENCYCFG_OFFSET)
-define LPC313X_SYSCREG_ISROM_LATENCYCFG          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISROM_LATENCYCFG_OFFSET)
+#define LPC313X_SYSCREG_ISRAM0_LATENCYCFG        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM0_LATENCYCFG_OFFSET)
+#define LPC313X_SYSCREG_ISRAM1_LATENCYCFG        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISRAM1_LATENCYCFG_OFFSET)
+#define LPC313X_SYSCREG_ISROM_LATENCYCFG         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ISROM_LATENCYCFG_OFFSET)
 
 /* MPMC configuration registers */
 
-define LPC313X_SYSCREG_MPMC_AHBMISC              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_AHBMISC_OFFSET)
-define LPC313X_SYSCREG_MPMC_DELAYMODES           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_DELAYMODES_OFFSET)
-define LPC313X_SYSCREG_MPMC_WAITRD0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD0_OFFSET)
-define LPC313X_SYSCREG_MPMC_WAITRD1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD1_OFFSET)
-define LPC313X_SYSCREG_MPMC_WIREEBIMSZ           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WIREEBIMSZ_OFFSET)
-define LPC313X_SYSCREG_MPMC_TESTMODE0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE0_OFFSET)
-define LPC313X_SYSCREG_MPMC_TESTMODE1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE1_OFFSET)
+#define LPC313X_SYSCREG_MPMC_AHBMISC             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_AHBMISC_OFFSET)
+#define LPC313X_SYSCREG_MPMC_DELAYMODES          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_DELAYMODES_OFFSET)
+#define LPC313X_SYSCREG_MPMC_WAITRD0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD0_OFFSET)
+#define LPC313X_SYSCREG_MPMC_WAITRD1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WAITRD1_OFFSET)
+#define LPC313X_SYSCREG_MPMC_WIREEBIMSZ          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_WIREEBIMSZ_OFFSET)
+#define LPC313X_SYSCREG_MPMC_TESTMODE0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE0_OFFSET)
+#define LPC313X_SYSCREG_MPMC_TESTMODE1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MPMC_TESTMODE1_OFFSET)
 
 /* Miscellaneous system configuration registers, part 2 */
 
-define LPC313X_SYSCREG_AHB0EXTPRIO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_AHB0EXTPRIO_OFFSET)
-define LPC313X_SYSCREG_ARM926SHADOWPTR           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ARM926SHADOWPTR_OFFSET)
+#define LPC313X_SYSCREG_AHB0EXTPRIO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_AHB0EXTPRIO_OFFSET)
+#define LPC313X_SYSCREG_ARM926SHADOWPTR          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_ARM926SHADOWPTR_OFFSET)
 
 /* Pin multiplexing control registers */
 
-define LPC313X_SYSCREG_MUX_LCDEBISEL             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_LCDEBISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_GPIOMCISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_GPIOMCISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_NANDMCISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_NANDMCISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_UARTSPISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_UARTSPISEL_OFFSET)
-define LPC313X_SYSCREG_MUX_I2STXPCMSEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_I2STXPCMSEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_LCDEBISEL            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_LCDEBISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_GPIOMCISEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_GPIOMCISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_NANDMCISEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_NANDMCISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_UARTSPISEL           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_UARTSPISEL_OFFSET)
+#define LPC313X_SYSCREG_MUX_I2STXPCMSEL          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_MUX_I2STXPCMSEL_OFFSET)
 
 /* Pad configuration registers */
 
-define LPC313X_SYSCREG_PAD_EBID9                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID9_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID10                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID10_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID11                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID11_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID12                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID12_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID13                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID13_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID14                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID14_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXBCK0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK0_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO9                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO9_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO6                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO6_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB7               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB7_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB4               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB4_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB2               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB2_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN0_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO1                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO1_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID4                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID4_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXCLK0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXCLK0_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXBCK0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXBCK0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBIA1CLE              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA1CLE_OFFSET)
-define LPC313X_SYSCREG_PAD_EBINCASBLOUT0         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINCASBLOUT0_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS3              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS3_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB0               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBIDQM0NOE            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIDQM0NOE_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID0                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID1                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID1_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID2                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID2_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID3                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID3_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID5                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID5_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID6                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID6_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID7                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID7_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID8                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID8_OFFSET)
-define LPC313X_SYSCREG_PAD_EBID15                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID15_OFFSET)
-define LPC313X_SYSCREG_PAD_I2STXDATA1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXDATA1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2STXBCK1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXBCK1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2STXWS1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXWS1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXDATA0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA0_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXWS0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS0_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXDATA1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXBCK1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2SRXWS1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS1_OFFSET)
-define LPC313X_SYSCREG_PAD_SYSCLKO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SYSCLKO_OFFSET)
-define LPC313X_SYSCREG_PAD_PWMDATA               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_PWMDATA_OFFSET)
-define LPC313X_SYSCREG_PAD_UARTRXD               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTRXD_OFFSET)
-define LPC313X_SYSCREG_PAD_UARTTXD               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTTXD_OFFSET)
-define LPC313X_SYSCREG_PAD_I2CSDA1               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSDA1_OFFSET)
-define LPC313X_SYSCREG_PAD_I2CSCL1               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSCL1_OFFSET)
-define LPC313X_SYSCREG_PAD_CLK256FSO             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_CLK256FSO_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO0                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO0_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO2                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO2_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO3                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO3_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO4                 (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO4_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO11                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO11_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO12                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO12_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO13                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO13_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO14                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO14_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO15                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO15_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO16                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO16_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO17                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO17_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO18                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO18_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO19                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO19_OFFSET)
-define LPC313X_SYSCREG_PAD_GPIO20                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO20_OFFSET)
-define LPC313X_SYSCREG_PAD_SPIMISO               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMISO_OFFSET)
-define LPC313X_SYSCREG_PAD_SPIMOSI               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMOSI_OFFSET)
-define LPC313X_SYSCREG_PAD_SPICSIN               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSIN_OFFSET)
-define LPC313X_SYSCREG_PAD_SPISCK                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPISCK_OFFSET)
-define LPC313X_SYSCREG_PAD_SPICSOUT0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSOUT0_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS0_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS1_OFFSET)
-define LPC313X_SYSCREG_PAD_NANDNCS2              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS2_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDCSB               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDCSB_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB1               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB1_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDERD               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDERD_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDRS                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRS_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDRWWR              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRWWR_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB3               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB3_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB5               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB5_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB6               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB6_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB8               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB8_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB9               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB9_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB10              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB10_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB11              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB11_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB12              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB12_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB13              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB13_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB14              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB14_OFFSET)
-define LPC313X_SYSCREG_PAD_MLCDDB15              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB15_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO5                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO5_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO7                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO7_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO8                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO8_OFFSET)
-define LPC313X_SYSCREG_PAD_MGPIO10               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO10_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN1_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN2            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN2_OFFSET)
-define LPC313X_SYSCREG_PAD_MNANDRYBN3            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN3_OFFSET)
-define LPC313X_SYSCREG_PAD_MUARTCTSN             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MUARTCTSN_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXDATA0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXDATA0_OFFSET)
-define LPC313X_SYSCREG_PAD_MI2STXWS0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXWS0_OFFSET)
-define LPC313X_SYSCREG_PAD_EBINRASBLOUT1         (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINRASBLOUT1_OFFSET)
-define LPC313X_SYSCREG_PAD_EBIA0ALE              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA0ALE_OFFSET)
-define LPC313X_SYSCREG_PAD_EBINWE                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINWE_OFFSET)
-define LPC313X_SYSCREG_PAD_ESHCTRLSUP4           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP4_OFFSET)
-define LPC313X_SYSCREG_PAD_ESHCTRLSUP8           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP8_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID9                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID9_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID10               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID10_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID11               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID11_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID12               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID12_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID13               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID13_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID14               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID14_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXBCK0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK0_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO9               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO9_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO6               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO6_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB7              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB7_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB4              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB4_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB2              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB2_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN0_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO1                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO1_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID4                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID4_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXCLK0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXCLK0_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXBCK0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXBCK0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBIA1CLE             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA1CLE_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBINCASBLOUT0        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINCASBLOUT0_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS3             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS3_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB0              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBIDQM0NOE           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIDQM0NOE_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID0                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID1                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID1_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID2                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID2_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID3                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID3_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID5                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID5_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID6                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID6_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID7                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID7_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID8                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID8_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBID15               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBID15_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2STXDATA1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXDATA1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2STXBCK1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXBCK1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2STXWS1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2STXWS1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXDATA0           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA0_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXWS0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS0_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXDATA1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXDATA1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXBCK1            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXBCK1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2SRXWS1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2SRXWS1_OFFSET)
+#define LPC313X_SYSCREG_PAD_SYSCLKO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SYSCLKO_OFFSET)
+#define LPC313X_SYSCREG_PAD_PWMDATA              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_PWMDATA_OFFSET)
+#define LPC313X_SYSCREG_PAD_UARTRXD              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTRXD_OFFSET)
+#define LPC313X_SYSCREG_PAD_UARTTXD              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_UARTTXD_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2CSDA1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSDA1_OFFSET)
+#define LPC313X_SYSCREG_PAD_I2CSCL1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_I2CSCL1_OFFSET)
+#define LPC313X_SYSCREG_PAD_CLK256FSO            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_CLK256FSO_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO0                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO0_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO2                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO2_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO3                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO3_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO4                (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO4_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO11               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO11_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO12               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO12_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO13               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO13_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO14               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO14_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO15               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO15_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO16               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO16_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO17               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO17_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO18               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO18_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO19               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO19_OFFSET)
+#define LPC313X_SYSCREG_PAD_GPIO20               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_GPIO20_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPIMISO              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMISO_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPIMOSI              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPIMOSI_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPICSIN              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSIN_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPISCK               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPISCK_OFFSET)
+#define LPC313X_SYSCREG_PAD_SPICSOUT0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_SPICSOUT0_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS0             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS0_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS1             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS1_OFFSET)
+#define LPC313X_SYSCREG_PAD_NANDNCS2             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_NANDNCS2_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDCSB              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDCSB_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB1              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB1_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDERD              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDERD_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDRS               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRS_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDRWWR             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDRWWR_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB3              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB3_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB5              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB5_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB6              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB6_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB8              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB8_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB9              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB9_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB10             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB10_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB11             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB11_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB12             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB12_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB13             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB13_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB14             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB14_OFFSET)
+#define LPC313X_SYSCREG_PAD_MLCDDB15             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MLCDDB15_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO5               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO5_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO7               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO7_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO8               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO8_OFFSET)
+#define LPC313X_SYSCREG_PAD_MGPIO10              (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MGPIO10_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN1           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN1_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN2           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN2_OFFSET)
+#define LPC313X_SYSCREG_PAD_MNANDRYBN3           (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MNANDRYBN3_OFFSET)
+#define LPC313X_SYSCREG_PAD_MUARTCTSN            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MUARTCTSN_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXDATA0          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXDATA0_OFFSET)
+#define LPC313X_SYSCREG_PAD_MI2STXWS0            (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_MI2STXWS0_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBINRASBLOUT1        (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINRASBLOUT1_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBIA0ALE             (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBIA0ALE_OFFSET)
+#define LPC313X_SYSCREG_PAD_EBINWE               (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_EBINWE_OFFSET)
+#define LPC313X_SYSCREG_PAD_ESHCTRLSUP4          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP4_OFFSET)
+#define LPC313X_SYSCREG_PAD_ESHCTRLSUP8          (LPC313X_SYSCREG_VBASE+LPC313X_SYSCREG_PAD_ESHCTRLSUP8_OFFSET)
 
 /* SYSCREG register bit definitions *********************************************************************/
 /* Miscellaneous system configuration registers, part1 */
@@ -409,14 +409,14 @@ define LPC313X_SYSCREG_PAD_ESHCTRLSUP8           (LPC313X_SYSCREG_VBASE+LPC313X_
 #  define SYSCREG_ABCCFG_ARM926EJSI_EXT32        (7 << SYSCREG_ABCCFG_ARM926EJSI_SHIFT) /* extend to 32-beat */
 #define SYSCREG_ABCCFG_ARM926EJSD_SHIFT          (3)       /* Bits 3-5: ARM926EJS data AHB bus bandwidth control */
 #define SYSCREG_ABCCFG_ARM926EJSD_MASK           (7 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT)
-#  define SYSCREG_ABCCFG_ARM926EJSI_NORMAL       (0 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Normal mode */
-#  define SYSCREG_ABCCFG_ARM926EJSI_NONSEQ       (1 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Make non-sequential */
-#  define SYSCREG_ABCCFG_ARM926EJSI_SPLIT4       (2 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_SPLIT8       (3 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 8-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_EXT8         (4 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 8-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_EXT16        (5 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 16-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_SPLIT4W      (6 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
-#  define SYSCREG_ABCCFG_ARM926EJSI_EXT32        (7 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* extend to 32-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_NORMAL       (0 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Normal mode */
+#  define SYSCREG_ABCCFG_ARM926EJSD_NONSEQ       (1 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Make non-sequential */
+#  define SYSCREG_ABCCFG_ARM926EJSD_SPLIT4       (2 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_SPLIT8       (3 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 8-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_EXT8         (4 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 8-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_EXT16        (5 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Extend to 16-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_SPLIT4W      (6 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* Split to 4-beat */
+#  define SYSCREG_ABCCFG_ARM926EJSD_EXT32        (7 << SYSCREG_ABCCFG_ARM926EJSD_SHIFT) /* extend to 32-beat */
 #define SYSCREG_ABCCFG_DMA_SHIFT                 (0)       /* Bits 0-2: 2:0 DMA AHB bus bandwidth control */
 #define SYSCREG_ABCCFG_DMA_MASK                  (7 << SYSCREG_ABCCFG_DMA_SHIFT)
 #  define SYSCREG_ABCCFG_DMA_NORMAL              (0 << SYSCREG_ABCCFG_DMA_SHIFT)        /* Normal mode */