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author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-12-30 14:43:48 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2009-12-30 14:43:48 +0000 |
commit | 8c4a58a7675b213eceec58d357315858afd81578 (patch) | |
tree | 505e379ee5bc2673a76136772d6f17d5581eed25 /nuttx/arch/arm | |
parent | ad197aab796450a7d27cee6dec2476c037a01bcc (diff) | |
download | px4-nuttx-8c4a58a7675b213eceec58d357315858afd81578.tar.gz px4-nuttx-8c4a58a7675b213eceec58d357315858afd81578.tar.bz2 px4-nuttx-8c4a58a7675b213eceec58d357315858afd81578.zip |
Add clock initializatin structure
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2462 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/arm')
-rwxr-xr-x | nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h | 1 | ||||
-rwxr-xr-x | nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h | 108 |
2 files changed, 105 insertions, 4 deletions
diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h index 4c48b4b48..ee744b95e 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_cgu.h @@ -1259,6 +1259,7 @@ #define CGU_DYNSEL_ARM926LPITRANS (1 << 2) /* Bit 2: ARM926 instr transfers can enable high-speed */ #define CGU_DYNSEL_DMAREADY (1 << 1) /* Bit 1: dma last transfers can enable high-speed */ #define CGU_DYNSEL_DMATRANS (1 << 0) /* Bit 0: dma transfers can enable high-speed */ +#define CGU_DYNSEL_ALLBITS (0x1ff) /* CGU configuration register bit definitions ***************************************************/ /* Power and oscillator control registers */ diff --git a/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h b/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h index 82f26a0be..8d1609656 100755 --- a/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h +++ b/nuttx/arch/arm/src/lpc313x/lpc313x_cgudrvr.h @@ -67,15 +67,15 @@ #define CLKID_SYSBASE_LAST CLKID_INTCCLK #define _D0B(id) _RBIT(id,CLKID_SYSBASE_FIRST) -#define CLKID_AHB0APB0_FIRST CLKID_AHB2APB0ASYNCPCLK /* Domain 1: AHB0APB0_BASE */ +#define CLKID_AHB0APB0_FIRST CLKID_AHB2APB0PCLK /* Domain 1: AHB0APB0_BASE */ #define CLKID_AHB0APB0_LAST CLKID_RNGPCLK #define _D1B(id) _RBIT(id,CLKID_AHB0APB0_FIRST) -#define CLKID_AHB0APB1_FIRST CLKID_AHB2APB1ASYNCPCLK /* Domain 2: AHB0APB1_BASE */ +#define CLKID_AHB0APB1_FIRST CLKID_AHB2APB1PCLK /* Domain 2: AHB0APB1_BASE */ #define CLKID_AHB0APB1_LAST CLKID_I2C1PCLK #define _D2B(id) _RBIT(id,CLKID_AHB0APB1_FIRST) -#define CLKID_AHB0APB2_FIRST CLKID_AHB2APB2ASYNCPCLK /* Domain 3: AHB0APB2_BASE */ +#define CLKID_AHB0APB2_FIRST CLKID_AHB2APB2PCLK /* Domain 3: AHB0APB2_BASE */ #define CLKID_AHB0APB2_LAST CLKID_SPIPCLKGATED #define _D3B(id) _RBIT(id,CLKID_AHB0APB2_FIRST) @@ -174,7 +174,8 @@ #define FRACDIV_BASE11_CNT 0 /* No fractional divider available */ -#define CGU_NFRACDIV 24 /* Number of fractional dividers */ +#define CGU_NFRACDIV 24 /* Number of fractional dividers: 0-23 */ +#define CGU_NDYNFRACDIV 7 /* Number of dynamic fractional dividers: 0-6 */ #define FDCNDX_INVALID -1 /* Indicates an invalid fractional * divider index */ @@ -404,6 +405,105 @@ enum lpc313x_resetid_e RESETID_INTCRST, /* 55 Interrupt Controller */ }; +/* This structure describes one CGU fractional divider configuration */ + +struct lpc313x_fdivconfig_s +{ + uint8_t stretch; /* Fractional divider stretch enable. */ + uint8_t n; /* Fractional divider nominal nominator */ + uint16_t m; /* Fractional divider nominal denominator */ +}; + +/* The structure describes the configuration of one CGU sub-domain */ + +struct lpc313x_subdomainconfig_s +{ + struct lpc313x_fdivconfig_s fdiv; /* Fractional divider settings */ + uint32_t clkset; /* Bitset of all clocks in the sub-domain */ +}; + +/* CGU clock initilization structure. Describes the platform-specific + * configuration of every clock domain. + */ + +struct lpc313x_clkinit_s +{ + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE0_CNT]; + } domain0; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE1_CNT]; + } domain1; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE2_CNT]; + } domain2; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE3_CNT]; + } domain3; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE4_CNT]; + } domain4; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE5_CNT]; + } domain5; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE6_CNT]; + } domain6; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE7_CNT]; + } domain7; + + struct + { + uint8_t finsel; + } domain8; + + struct + { + uint8_t finsel; + } domain9; + + struct + { + uint8_t finsel; + struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE10_CNT]; + } domain10; + + struct + { + uint8_t finsel; + } domain11; + + struct + { + uint16_t sel; + struct lpc313x_fdivconfig_s cfg; + } dynfdiv[CGU_NDYNFRACDIV]; +}; + /* This structure is used to pass PLL configuration data to * lpc313x_pllconfig() */ |