First step at porting to MoteinoMEGA. LED shows assert failure at boot. Appears to be short double blink, short off (~1sec), followed by 250ms toggle cycles. Most of it derived from amber board.

5 files changed, 39 insertions, 1 deletions

diff --git a/nuttx/arch/avr/src/atmega/Kconfig b/nuttx/arch/avr/src/atmega/Kconfig
index a976803d9..d2436c723 100644
--- a/nuttx/arch/avr/src/atmega/Kconfig
+++ b/nuttx/arch/avr/src/atmega/Kconfig
@@ -15,6 +15,11 @@ config ARCH_CHIP_ATMEGA128
 	---help---
 		Atmel ATMega128 8-bit AVR.
 
+config ARCH_CHIP_ATMEGA1284P
+	bool "ATMega1284P"
+	---help---
+		Atmel ATMega1284P 8-bit AVR.
+
 endchoice # ATMega Configuration Options
 
 menu "ATMega Peripheral Selections"
diff --git a/nuttx/arch/avr/src/atmega/atmega_lowconsole.c b/nuttx/arch/avr/src/atmega/atmega_lowconsole.c
index ba3255741..02cad5ba1 100644
--- a/nuttx/arch/avr/src/atmega/atmega_lowconsole.c
+++ b/nuttx/arch/avr/src/atmega/atmega_lowconsole.c
@@ -218,8 +218,13 @@ void usart0_reset(void)
 
   /* Unconfigure pins (no action needed */
 
+#ifdef CONFIG_ARCH_CHIP_ATMEGA1284P
+  DDRD  &= ~(1 << 1);
+  PORTD &= ~(1 << 0);
+#else
   DDRE  &= ~(1 << 1);
   PORTE &= ~(1 << 0);
+#endif
 
   /* Unconfigure BAUD divisor */
 
@@ -309,6 +314,22 @@ void usart0_configure(void)
   UCSR0B = ucsr0b;
   UCSR0C = ucsr0c;
 
+#ifdef CONFIG_ARCH_CHIP_ATMEGA1284P
+  /* Pin Configuration: None necessary, Port D bits 0&1 are automatically
+   * configured:
+   *
+   * Port D, Bit 0: RXD0, USART0 Receive Pin. Receive Data (Data input pin
+   *   for the USART0). When the USART0 receiver is enabled this pin is
+   *   configured as an input regardless of the value of DDRD0. When the
+   *   USART0 forces this pin to be an input, a logical one in PORTD0 will
+   *   turn on the internal pull-up.
+   *
+   * Port D, Bit 1: TXD0, UART0 Transmit pin.
+   */
+
+  DDRD  |= (1 << 1);   /* Force Port D pin 1 to be an output -- should not be necessary */
+  PORTD |= (1 << 0);   /* Set pull-up on Port D pin 0 */
+#else
   /* Pin Configuration: None necessary, Port E bits 0&1 are automatically
    * configured:
    *
@@ -324,8 +345,9 @@ void usart0_configure(void)
    * However, this is not explicitly stated in the text.
    */
 
-  DDRE  |= (1 << 1);   /* Force Port E pin 1 to be an input -- might not be necessary */
+  DDRE  |= (1 << 1);   /* Force Port E pin 1 to be an output -- might not be necessary */
   PORTE |= (1 << 0);   /* Set pull-up on Port E pin 0 */
+#endif
 
   /* Set the baud rate divisor */
 
diff --git a/nuttx/arch/avr/src/atmega/atmega_lowinit.c b/nuttx/arch/avr/src/atmega/atmega_lowinit.c
index 1ac5661f6..0acd08422 100644
--- a/nuttx/arch/avr/src/atmega/atmega_lowinit.c
+++ b/nuttx/arch/avr/src/atmega/atmega_lowinit.c
@@ -128,7 +128,12 @@ void up_lowinit(void)
 
   /* Set the system clock divider to 1 */
 
+#ifdef CONFIG_ARCH_CHIP_ATMEGA1284P
+  CLKPR = 0x80;
+  CLKPR = 0;
+#else
   XDIV = 0;
+#endif
 
   /* Initialize the watchdog timer */
 
diff --git a/nuttx/arch/avr/src/atmega/atmega_timerisr.c b/nuttx/arch/avr/src/atmega/atmega_timerisr.c
index 069935fb0..faa74eb61 100644
--- a/nuttx/arch/avr/src/atmega/atmega_timerisr.c
+++ b/nuttx/arch/avr/src/atmega/atmega_timerisr.c
@@ -177,5 +177,9 @@ void up_timer_initialize(void)
 
   /* Enable the interrupt on compare match A */
 
+#ifdef CONFIG_ARCH_CHIP_ATMEGA1284P
+  TIMSK1 |= (1 << OCIE1A);
+#else
   TIMSK |= (1 << OCIE1A);
+#endif
 }
diff --git a/nuttx/arch/avr/src/avr/Toolchain.defs b/nuttx/arch/avr/src/avr/Toolchain.defs
index b1b60587b..138cc1254 100644
--- a/nuttx/arch/avr/src/avr/Toolchain.defs
+++ b/nuttx/arch/avr/src/avr/Toolchain.defs
@@ -70,6 +70,8 @@ endif
 
 ifeq ($(CONFIG_ARCH_CHIP_ATMEGA128),y)
   ARCHCPUFLAGS += -mmcu=atmega128
+else ifeq ($(CONFIG_ARCH_CHIP_ATMEGA1284P),y)
+  ARCHCPUFLAGS += -mmcu=atmega1284p
 else ifeq ($(CONFIG_ARCH_CHIP_AT90USB646),y)
   ARCHCPUFLAGS += -mmcu=at90usb646
 else ifeq ($(CONFIG_ARCH_CHIP_AT90USB647),y)