Add beginning of m9s12x GPIO support

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3317 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 212 insertions, 1 deletions

diff --git a/nuttx/arch/hc/src/m9s12/m9s12_internal.h b/nuttx/arch/hc/src/m9s12/m9s12_internal.h
index 43d4188f2..643627f30 100755
--- a/nuttx/arch/hc/src/m9s12/m9s12_internal.h
+++ b/nuttx/arch/hc/src/m9s12/m9s12_internal.h
@@ -55,7 +55,132 @@
  * Definitions
  ************************************************************************************/
 
-/* Configuration ********************************************************************/
+/* GPIO management macros:
+ *
+ * The GPIO configuration is represented by a 16-bit value encoded as follows:
+ *
+ *   xxII OUUR DMGG GPPP
+ *     || |||| |||    `-Pin number
+ *     || |||| || `- Port number
+ *     || |||| | `- PIM Ports
+ *     || |||| `- Direction
+ *     || |||`- Reduced drive
+ *     || ||`- Polarity
+ *     || |`- Pull up (or down)
+ *     || `- Wired OR open drain
+ *     |`- Interrupt or rising/falling (polarity)
+ *     `- Interrupt
+ *
+ * NOTE: MEBI ports E and K can have special configurations as controlled by
+ * the PEAR and MODE registers.  Those special configurations are not managed
+ * by the logic below; that logic is only intended to support general GPIO
+ * pin usage.
+ */
+
+/* Interrupts:
+ *
+ *   xxII xxxx xxxx xxxx
+ *
+ * For PIM ports G, H, and J.  NOTE:  If pull up/down is also selected, then
+ * it must be consistent with the selected interrupt edge (because both are
+ * controlled by the same polarity register):
+ *
+ *   Rising edge <-> Pull down
+ *   Falling Edge <-> Pull up
+ *
+ * Selecting input also selects direction == input (it is unless to specify
+ * GPIO_INPUT and an error if GPIO_OUTPUT is also specified)
+ */
+
+#define GPIO_INT_SHIFT      (12)
+#define GPIO_INT_MASK       (3 << GPIO_PULLUP_SHIFT)
+#  define GPIO_INT_POLARITY (1 << GPIO_PULLUP_SHIFT)
+#  define GPIO_INT_ENABLE   (2 << GPIO_PULLUP_SHIFT)
+#  define GPIO_INT_FALLING  (2 << GPIO_PULLUP_SHIFT)
+#  define GPIO_INT_RISING   (3 << GPIO_PULLUP_SHIFT)
+
+/* Wired OR open-drain:
+ *
+ *   xxxx Oxxx xxxx xxxx
+ *
+ * Only PIM ports S and L
+ */
+
+#define GPIO_OPENDRAN (1 << 11)
+
+/* Pull up (or down):
+ *
+ *   xxxx xUUx xxxx xxxx
+ *
+ * For PIM ports (T,S,G,H,J,L), selection is per-pin
+ * For MEBI ports (A,B,E,K), selection is per-port, polarity is ignored
+ */
+
+#define GPIO_PULLUP_SHIFT    (9)
+#define GPIO_PULLUP_MASK     (3 << GPIO_PULLUP_SHIFT)
+#  define GPIO_PULL_POLARITY (1 << GPIO_PULLUP_SHIFT)
+#  define GPIO_PULL_ENABLE   (2 << GPIO_PULLUP_SHIFT)
+#  define GPIO_PULLUP        (2 << GPIO_PULLUP_SHIFT)
+#  define GPIO_PULLDOWN      (3 << GPIO_PULLUP_SHIFT)
+
+/* Reduced drive:
+ *
+ *   xxxx xxxR xxxx xxxx
+ *
+ * For PIM ports (T,S,G,H,J,L), selection is per-pin
+ * For MEBI ports (A,B,E,K), selection is per-port
+ */
+
+#define GPIO_REDUCED (1 << 8)
+
+/* Data direction (All ports -- A,B,E,K,T,S,G,H,J,L)
+ *
+ *   xxxx xxxx Dxxx xxxx
+ *
+ */
+
+#define GPIO_DIRECTION (1 << 7)
+#  define GPIO_INPUT   (0)
+#  define GPIO_OUTPUT   GPIO_DIRECTION
+
+/* Port selection
+ *
+ *   xxxx xxxx xGGG Gxxx
+ *
+ * Ports A, B, E, and K reside in the MEBI block
+ * Ports T,S,G,H,J, and L reside in the PIM block.
+ */
+ 
+#define GPIO_PORT_SHIFT 3
+#define GPIO_PORT_MASK  (15 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_A   (0 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_B   (1 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_E   (2 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_K   (3 << GPIO_PORT_SHIFT)
+
+#  define GPIO_PORT_PIM (8 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_T   (8 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_S   (9 << GPIO_PORT_SHIFT
+#  define GPIO_PORT_G   (10 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_H   (11 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_J   (12 << GPIO_PORT_SHIFT)
+#  define GPIO_PORT_L   (13 << GPIO_PORT_SHIFT)
+
+/* Pin numbers
+ *
+ *   xxxx xxxx xxxx xPPP
+ */
+
+#define GPIO_PIN_SHIFT  (0)
+#define GPIO_PIN_MASK   (7 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_0    (0 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_1    (1 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_2    (2 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_3    (3 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_4    (4 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_5    (5 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_6    (6 << GPIO_PORT_SHIFT)
+#  define GPIO_PIN_7    (7 << GPIO_PORT_SHIFT)
 
 /************************************************************************************
  * Inline Functions
@@ -80,6 +205,92 @@ extern "C" {
  ************************************************************************************/
 
 /************************************************************************************
+ * Name: hcs12_gpioirqinitialize
+ *
+ * Description:
+ *   Initialize logic to support a second level of interrupt decoding for GPIO pins.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+EXTERN void hcs12_gpioirqinitialize(void);
+#else
+#  define hcs12_gpioirqinitialize()
+#endif
+
+/************************************************************************************
+ * Name: hcs12_configgpio
+ *
+ * Description:
+ *   Configure a GPIO pin based on bit-encoded description of the pin.
+ *
+ ************************************************************************************/
+
+EXTERN int hcs12_configgpio(uint16_t cfgset);
+
+/************************************************************************************
+ * Name: hcs12_gpiowrite
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ ************************************************************************************/
+
+EXTERN void hcs12_gpiowrite(uint16_t pinset, bool value);
+
+/************************************************************************************
+ * Name: hcs12_gpioread
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ ************************************************************************************/
+
+EXTERN bool hcs12_gpioread(uint16_t pinset);
+
+/************************************************************************************
+ * Name: hcs12_gpioirqenable
+ *
+ * Description:
+ *   Enable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+EXTERN void hcs12_gpioirqenable(int irq);
+#else
+#  define hcs12_gpioirqenable(irq)
+#endif
+
+/************************************************************************************
+ * Name: hcs12_gpioirqdisable
+ *
+ * Description:
+ *   Disable the interrupt for specified GPIO IRQ
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_GPIO_IRQ
+EXTERN void hcs12_gpioirqdisable(int irq);
+#else
+#  define hcs12_gpioirqdisable(irq)
+#endif
+
+/************************************************************************************
+ * Function:  hcs12_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the base address of the provided pinset.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO
+EXTERN int hcs12_dumpgpio(uint16_t pinset, const char *msg);
+#else
+#  define hcs12_dumpgpio(p,m)
+#endif
+
+/************************************************************************************
  * Function: hcs12_ethinitialize
  *
  * Description: