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authorpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2011-02-20 15:19:44 +0000
committerpatacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>2011-02-20 15:19:44 +0000
commit2d795267b97ca49c544ca4a38dbf3771d3cd4697 (patch)
tree84c0f2def09c2c2e7712cc448ed152cb3652ad4b /nuttx/arch/hc/src/m9s12/m9s12_lowputc.S
parent2beb149e9bbba41c18ec8b3d83c2ba81c39b35a0 (diff)
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Add m9s12 serial logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3305 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/hc/src/m9s12/m9s12_lowputc.S')
-rwxr-xr-xnuttx/arch/hc/src/m9s12/m9s12_lowputc.S107
1 files changed, 104 insertions, 3 deletions
diff --git a/nuttx/arch/hc/src/m9s12/m9s12_lowputc.S b/nuttx/arch/hc/src/m9s12/m9s12_lowputc.S
index e4bc7858c..a04d6a1d8 100755
--- a/nuttx/arch/hc/src/m9s12/m9s12_lowputc.S
+++ b/nuttx/arch/hc/src/m9s12/m9s12_lowputc.S
@@ -41,12 +41,65 @@
#include "up_internal.h"
#include "m9s12_internal.h"
-#include "m9s12_flash.h"
+#include "m9s12_sci.h"
+#include "m9s12_serial.h"
+
+#ifdef CONFIG_HCS12_SERIALMON
+# include "m9s12_flash.h"
+#endif
/**************************************************************************
* Private Definitions
**************************************************************************/
+/* Select SCI parameters for the selected console */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
+# define HCS12_CONSOLE_BASE HCS12_SCI0_BASE
+# define HCS12_CONSOLE_BAUD CONFIG_SCI0_BAUD
+# define HCS12_CONSOLE_BITS CONFIG_SCI0_BITS
+# define HCS12_CONSOLE_PARITY CONFIG_SCI0_PARITY
+# define HCS12_CONSOLE_2STOP CONFIG_SCI0_2STOP
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
+# define HCS12_CONSOLE_BASE HCS12_SCI1_BASE
+# define HCS12_CONSOLE_BAUD CONFIG_SCI1_BAUD
+# define HCS12_CONSOLE_BITS CONFIG_SCI1_BITS
+# define HCS12_CONSOLE_PARITY CONFIG_SCI1_PARITY
+# define HCS12_CONSOLE_2STOP CONFIG_SCI1_2STOP
+#else
+# warning "No CONFIG_SCIn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Selete the SCIBR register value */
+
+#define CONSOLE_SCIBR_VALUE SCIBR_VALUE(HCS12_CONSOLE_BAUD)
+
+/* Select the SCICR1 register settings */
+
+#if HCS12_CONSOLE_BITS == 9
+# define UART_SCICR1_NBITS SCI_CR1_M
+#elif HCS12_CONSOLE_BITS == 8
+# define UART_SCICR1_NBITS 0
+#else
+# warning "Number of bits not supported"
+#endif
+
+#if HCS12_CONSOLE_PARITY == 0
+# define UART_SCICR1_PARITY 0
+#elif HCS12_CONSOLE_PARITY == 1
+# define UART_SCICR1_PARITY SCI_CR1_PE
+#elif HCS12_CONSOLE_PARITY == 2
+# define UART_SCICR1_PARITY (SCI_CR1_PE|SCI_CR1_PT)
+#else
+# error "ERROR: Invalid parity selection"
+#endif
+
+#if HCS12_CONSOLE_2STOP != 0
+# warning "Only a single stop bit supported"
+#endif
+
+#define CONSOLE_SCICR_VALUE (UART_SCICR1_NBITS|UART_SCICR1_PARITY)
+
/**************************************************************************
* Private Types
**************************************************************************/
@@ -82,7 +135,31 @@ up_lowsetup:
#ifdef CONFIG_HCS12_SERIALMON
rts
#else
-# error "up_lowsetup not implemented"
+ /* Disable the console */
+
+ ldab #0
+ stab (HCS12_CONSOLE_BASE+HCS12_SCI_CR1_OFFSET)
+ stab (HCS12_CONSOLE_BASE+HCS12_SCI_CR2_OFFSET)
+
+ /* Set the BAUD pre-scaler value */
+
+ ldab #(CONSOLE_SCIBR_VALUE >> 8)
+ stab (HCS12_CONSOLE_BASE+HCS12_SCI_BDH_OFFSET)
+
+ ldab #(CONSOLE_SCIBR_VALUE & 0xff)
+ stab (HCS12_CONSOLE_BASE+HCS12_SCI_BDL_OFFSET)
+
+ /* Set number of bits, parity, stop bits, etc. */
+
+ ldab #CONSOLE_SCICR_VALUE
+ stab (HCS12_CONSOLE_BASE+HCS12_SCI_CR1_OFFSET)
+
+ /* Enable transmitter and receiver */
+
+ ldab #(SCI_CR2_RE|SCI_CR2_TE)
+ stab (HCS12_CONSOLE_BASE+HCS12_SCI_CR2_OFFSET)
+ rts
+
#endif
.size up_lowsetup, . - up_lowsetup
@@ -97,7 +174,31 @@ up_lowputc:
#ifdef CONFIG_HCS12_SERIALMON
jmp PutChar
#else
-# error "up_lowputc not implemented"
+# if HCS12_CONSOLE_BITS == 9
+ staa 1, -sp
+# endif
+
+ /* Wait for the transmit data register to be available (TRDE==1) */
+
+.Lwait:
+ ldaa (HCS12_CONSOLE_BASE+HCS12_SCI_SR1_OFFSET)
+ bita #SCI_SR1_TDRE
+ bne .Lwait
+
+ /* Then write the byte to the transmit data register */
+
+# if HCS12_CONSOLE_BITS == 9
+ ldaa 1, sp+
+ bita #(0x01)
+ bne .L8bit
+ ldaa #SCI_DRH_T8
+ bra .Lwrdrh
+.L8bit:
+ ldaa #0
+.Lwrdrh:
+ staa (HCS12_CONSOLE_BASE+HCS12_SCI_DRH_OFFSET)
+# endif
+ stab (HCS12_CONSOLE_BASE+HCS12_SCI_DRL_OFFSET)
rts
#endif
.size up_lowputc, . - up_lowputc