diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-10-28 01:33:47 +0000 |
---|---|---|
committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2010-10-28 01:33:47 +0000 |
commit | 34617fe9e3de82b58d80f225deeea46326ee9da4 (patch) | |
tree | 004f4fd0b3dfd6a17fc058fe234d3fa6503aae7e /nuttx/arch/hc/src | |
parent | 96a45c67960e9bac5562508fe8fd63738e7943c8 (diff) | |
download | px4-nuttx-34617fe9e3de82b58d80f225deeea46326ee9da4.tar.gz px4-nuttx-34617fe9e3de82b58d80f225deeea46326ee9da4.tar.bz2 px4-nuttx-34617fe9e3de82b58d80f225deeea46326ee9da4.zip |
Reorg some headers
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3055 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch/hc/src')
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/chip.h | 4 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crgv4.h (renamed from nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h) | 8 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_intv1.h | 12 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h | 41 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mmcv4.h | 31 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_sciv3.h | 34 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_spiv3.h | 10 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_start.S | 2 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h | 54 |
9 files changed, 107 insertions, 89 deletions
diff --git a/nuttx/arch/hc/src/mc9s12ne64/chip.h b/nuttx/arch/hc/src/mc9s12ne64/chip.h index 555cd3901..0b0541fc7 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/chip.h +++ b/nuttx/arch/hc/src/mc9s12ne64/chip.h @@ -60,12 +60,12 @@ #define HCS12_PPAGE_BASE 0x8000 /* 0x8000-0xbfff: 16Kb Page window */ #define HCS12_FFLASH2_BASE 0xc000 /* 0xc000-0xffff: 16Kb Fixed FLASH EEPROM */ -/* Device Register Map Overview (all relatvie to HCS12_REG_BASE) */ +/* Device Register Map Overview (all relative to HCS12_REG_BASE) */ #define HCS12_CORE1_BASE 0x0000 /* 0x0000–0x0017: Ports A, B, E, Modes, Inits (MMC, INT, MEBI) */ /* 0x0018–0x0019: Reserved */ #define HCS12_DEVID_BASE 0x001a /* 0x001a-0x001b: Device ID register (PARTID) */ -#define HCS12_CORE2_BASE 0x001C /* 0x001c–0x001f: MEMSIZ, IRQ, HPRIO (INT, MMC) */ +#define HCS12_CORE2_BASE 0x001c /* 0x001c–0x001f: MEMSIZ, IRQ, HPRIO (INT, MMC) */ #define HCS12_CORE3_BASE 0x0020 /* 0x0020-0x002f: DBG */ #define HCS12_CORE4_BASE 0x0030 /* 0x0030–0x0033: PPAGE, Port K (MEBI, MMC) */ #define HCS12_CRG_BASE 0x0034 /* 0x0034–0x003f: Clock and Reset Generator (PLL, RTI, COP) */ diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crgv4.h index 9929ceadf..0d8a91717 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_crgv4.h @@ -1,5 +1,5 @@ /************************************************************************************
- * arch/hc/src/mc9s12ne64/mc9s12ne64_crg.h
+ * arch/hc/src/mc9s12ne64/mc9s12ne64_crgv4.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -33,8 +33,8 @@ *
************************************************************************************/
-#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRG_H
-#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRG_H
+#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRGV4_H
+#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRGV4_H
/************************************************************************************
* Included Files
@@ -137,4 +137,4 @@ * Public Functions
************************************************************************************/
-#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRG_H */
+#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_CRGV4_H */
diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_intv1.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_intv1.h index 2f0369497..7aa6b996f 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_intv1.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_intv1.h @@ -48,16 +48,20 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ +/* Offsets relative to CORE1 */ #define HCS12_INT_ITCR_OFFSET 0x0015 /* Interrupt Test Control Register */ #define HCS12_INT_ITEST_OFFSET 0x0016 /* Interrupt Test Registers */ -#define HCS12_INT_HPRIO_OFFSET 0x001f /* Highest Priority Interrupt */ + +/* Offsets relative to CORE2 */ + +#define HCS12_INT_HPRIO_OFFSET 0x0003 /* Highest Priority Interrupt */ /* Register Addresses ***************************************************************/ -#define HCS12_INT_ITCR (HCS12_CORE1_BASE+HCS12_INT_ITCR_OFFSET) -#define HCS12_INT_ITEST (HCS12_CORE1_BASE+HCS12_INT_ITEST_OFFSET) -#define HCS12_INT_HPRIO (HCS12_CORE1_BASE+HCS12_INT_HPRIO_OFFSET) +#define HCS12_INT_ITCR (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_INT_ITCR_OFFSET) +#define HCS12_INT_ITEST (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_INT_ITEST_OFFSET) +#define HCS12_INT_HPRIO (HCS12_REG_BASE+HCS12_CORE2_BASE+HCS12_INT_HPRIO_OFFSET) /* Register Bit-Field Definitions ***************************************************/ diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h index e85d0952f..e1bc6cddd 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mebiv3.h @@ -48,6 +48,7 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ +/* Offsets relative to CORE1 */ #define HCS12_MEBI_PORTA_OFFSET 0x0000 /* Port A Data Register */ #define HCS12_MEBI_PORTB_OFFSET 0x0001 /* Port B Data Register */ @@ -60,26 +61,32 @@ #define HCS12_MEBI_PUCR_OFFSET 0x000c /* Pull Control Register */ #define HCS12_MEBI_RDRIV_OFFSET 0x000d /* Reduced Drive Register */ #define HCS12_MEBI_EBICTL_OFFSET 0x000e /* External Bus Interface Control Register */ -#define HCS12_MEBI_IRQCR_OFFSET 0x001e /* IRQ Control Register */ -#define HCS12_MEBI_PORTK_OFFSET 0x0032 /* Port K Data Register */ -#define HCS12_MEBI_DDRK_OFFSET 0x0033 /* Data Direction Register K */ + +/* Offsets relative to CORE2 */ + +#define HCS12_MEBI_IRQCR_OFFSET 0x0002 /* IRQ Control Register */ + +/* Offsets relative to CORE4 */ + +#define HCS12_MEBI_PORTK_OFFSET 0x0002 /* Port K Data Register */ +#define HCS12_MEBI_DDRK_OFFSET 0x0003 /* Data Direction Register K */ /* Register Addresses ***************************************************************/ -#define HCS12_MEBI_PORTA (HCS12_CORE1_BASE+HCS12_MEBI_PORTA_OFFSET) -#define HCS12_MEBI_PORTB (HCS12_CORE1_BASE+HCS12_MEBI_PORTB_OFFSET) -#define HCS12_MEBI_DDRA (HCS12_CORE1_BASE+HCS12_MEBI_DDRA_OFFSET) -#define HCS12_MEBI_DDRB (HCS12_CORE1_BASE+HCS12_MEBI_DDRB_OFFSET) -#define HCS12_MEBI_PORTE (HCS12_CORE1_BASE+HCS12_MEBI_PORTE_OFFSET) -#define HCS12_MEBI_DDRE (HCS12_CORE1_BASE+HCS12_MEBI_DDRE_OFFSET) -#define HCS12_MEBI_PEAR (HCS12_CORE1_BASE+HCS12_MEBI_PEAR_OFFSET) -#define HCS12_MEBI_MODE (HCS12_CORE1_BASE+HCS12_MEBI_MODE_OFFSET) -#define HCS12_MEBI_PUCR (HCS12_CORE1_BASE+HCS12_MEBI_PUCR_OFFSET) -#define HCS12_MEBI_RDRIV (HCS12_CORE1_BASE+HCS12_MEBI_RDRIV_OFFSET) -#define HCS12_MEBI_EBICTL (HCS12_CORE1_BASE+HCS12_MEBI_EBICTL_OFFSET) -#define HCS12_MEBI_IRQCR (HCS12_CORE1_BASE+HCS12_MEBI_IRQCR_OFFSET) -#define HCS12_MEBI_PORTK (HCS12_CORE1_BASE+HCS12_MEBI_PORTK_OFFSET) -#define HCS12_MEBI_DDRK (HCS12_CORE1_BASE+HCS12_MEBI_DDRK_OFFSET) +#define HCS12_MEBI_PORTA (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_PORTA_OFFSET) +#define HCS12_MEBI_PORTB (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_PORTB_OFFSET) +#define HCS12_MEBI_DDRA (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_DDRA_OFFSET) +#define HCS12_MEBI_DDRB (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_DDRB_OFFSET) +#define HCS12_MEBI_PORTE (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_PORTE_OFFSET) +#define HCS12_MEBI_DDRE (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_DDRE_OFFSET) +#define HCS12_MEBI_PEAR (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_PEAR_OFFSET) +#define HCS12_MEBI_MODE (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_MODE_OFFSET) +#define HCS12_MEBI_PUCR (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_PUCR_OFFSET) +#define HCS12_MEBI_RDRIV (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_RDRIV_OFFSET) +#define HCS12_MEBI_EBICTL (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MEBI_EBICTL_OFFSET) +#define HCS12_MEBI_IRQCR (HCS12_REG_BASE+HCS12_CORE2_BASE+HCS12_MEBI_IRQCR_OFFSET) +#define HCS12_MEBI_PORTK (HCS12_REG_BASE+HCS12_CORE4_BASE+HCS12_MEBI_PORTK_OFFSET) +#define HCS12_MEBI_DDRK (HCS12_REG_BASE+HCS12_CORE4_BASE+HCS12_MEBI_DDRK_OFFSET) /* Register Bit-Field Definitions ***************************************************/ diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mmcv4.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mmcv4.h index 639d00e79..495307663 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mmcv4.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_mmcv4.h @@ -48,6 +48,7 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ +/* Offsets relative to CORE1 */ #define HCS12_MMC_INITRM_OFFSET 0x0010 /* Internal RAM Position Register */ #define HCS12_MMC_INITRG_OFFSET 0x0011 /* Internal Registers Position Register */ @@ -55,21 +56,27 @@ #define HCS12_MMC_MISC_OFFSET 0x0013 /* Miscellaneous System Control Register */ #define HCS12_MMC_MTST0_OFFSET 0x0014 /* Reserved Test Register 0 */ #define HCS12_MMC_MTST1_OFFSET 0x0017 /* Reserved Test Register 1 */ -#define HCS12_MMC_MEMSIZ0_OFFSET 0x001c /* Memory Size Register 0 */ -#define HCS12_MMC_MEMSIZ1_OFFSET 0x001d /* Memory Size Register 1 */ -#define HCS12_MMC_PPAGE_OFFSET 0x0030 /* Program Page Index Register */ + +/* Offsets relative to CORE2 */ + +#define HCS12_MMC_MEMSIZ0_OFFSET 0x0000 /* Memory Size Register 0 */ +#define HCS12_MMC_MEMSIZ1_OFFSET 0x0001 /* Memory Size Register 1 */ + +/* Offsets relative to CORE4 */ + +#define HCS12_MMC_PPAGE_OFFSET 0x0000 /* Program Page Index Register */ /* Register Addresses ***************************************************************/ -#define HCS12_MMC_INITRM (HCS12_CORE1_BASE+HCS12_MMC_INITRM_OFFSET) -#define HCS12_MMC_INITRG (HCS12_CORE1_BASE+HCS12_MMC_INITRG_OFFSET) -#define HCS12_MMC_INITEE (HCS12_CORE1_BASE+HCS12_MMC_INITEE_OFFSET) -#define HCS12_MMC_MISC (HCS12_CORE1_BASE+HCS12_MMC_MISC_OFFSET) -#define HCS12_MMC_MTST0 (HCS12_CORE1_BASE+HCS12_MMC_MTST0_OFFSET) -#define HCS12_MMC_MTST1 (HCS12_CORE1_BASE+HCS12_MMC_MTST1_OFFSET) -#define HCS12_MMC_MEMSIZ0 (HCS12_CORE1_BASE+HCS12_MMC_MEMSIZ0_OFFSET) -#define HCS12_MMC_MEMSIZ1 (HCS12_CORE1_BASE+HCS12_MMC_MEMSIZ1_OFFSET) -#define HCS12_MMC_PPAGE (HCS12_CORE1_BASE+HCS12_MMC_PPAGE_OFFSET) +#define HCS12_MMC_INITRM (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_INITRM_OFFSET) +#define HCS12_MMC_INITRG (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_INITRG_OFFSET) +#define HCS12_MMC_INITEE (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_INITEE_OFFSET) +#define HCS12_MMC_MISC (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_MISC_OFFSET) +#define HCS12_MMC_MTST0 (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_MTST0_OFFSET) +#define HCS12_MMC_MTST1 (HCS12_REG_BASE+HCS12_CORE1_BASE+HCS12_MMC_MTST1_OFFSET) +#define HCS12_MMC_MEMSIZ0 (HCS12_REG_BASE+HCS12_CORE2_BASE+HCS12_MMC_MEMSIZ0_OFFSET) +#define HCS12_MMC_MEMSIZ1 (HCS12_REG_BASE+HCS12_CORE2_BASE+HCS12_MMC_MEMSIZ1_OFFSET) +#define HCS12_MMC_PPAGE (HCS12_REG_BASE+HCS12_CORE4_BASE+HCS12_MMC_PPAGE_OFFSET) /* Register Bit-Field Definitions ***************************************************/ diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_sciv3.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_sciv3.h index 6249f52fe..fdcae5415 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_sciv3.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_sciv3.h @@ -60,23 +60,23 @@ /* Register Addresses ***************************************************************/ -#define HCS12_SCI0_BDH (HCS12_SCI0_BASE+HCS12_SCI_BDH_OFFSET) -#define HCS12_SCI0_BDL (HCS12_SCI0_BASE+HCS12_SCI_BDL_OFFSET) -#define HCS12_SCI0_CR1 (HCS12_SCI0_BASE+HCS12_SCI_CR1_OFFSET) -#define HCS12_SCI0_CR2 (HCS12_SCI0_BASE+HCS12_SCI_CR2_OFFSET) -#define HCS12_SCI0_SR1 (HCS12_SCI0_BASE+HCS12_SCI_SR1_OFFSET) -#define HCS12_SCI0_SR2 (HCS12_SCI0_BASE+HCS12_SCI_SR2_OFFSET) -#define HCS12_SCI0_DRH (HCS12_SCI0_BASE+HCS12_SCI_DRH_OFFSET) -#define HCS12_SCI0_DRL (HCS12_SCI0_BASE+HCS12_SCI_DRL_OFFSET) - -#define HCS12_SCI1_BDH (HCS12_SCI1_BASE+HCS12_SCI_BDH_OFFSET) -#define HCS12_SCI1_BDL (HCS12_SCI1_BASE+HCS12_SCI_BDL_OFFSET) -#define HCS12_SCI1_CR1 (HCS12_SCI1_BASE+HCS12_SCI_CR1_OFFSET) -#define HCS12_SCI1_CR2 (HCS12_SCI1_BASE+HCS12_SCI_CR2_OFFSET) -#define HCS12_SCI1_SR1 (HCS12_SCI1_BASE+HCS12_SCI_SR1_OFFSET) -#define HCS12_SCI1_SR2 (HCS12_SCI1_BASE+HCS12_SCI_SR2_OFFSET) -#define HCS12_SCI1_DRH (HCS12_SCI1_BASE+HCS12_SCI_DRH_OFFSET) -#define HCS12_SCI1_DRL (HCS12_SCI1_BASE+HCS12_SCI_DRL_OFFSET) +#define HCS12_SCI0_BDH (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_BDH_OFFSET) +#define HCS12_SCI0_BDL (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_BDL_OFFSET) +#define HCS12_SCI0_CR1 (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_CR1_OFFSET) +#define HCS12_SCI0_CR2 (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_CR2_OFFSET) +#define HCS12_SCI0_SR1 (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_SR1_OFFSET) +#define HCS12_SCI0_SR2 (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_SR2_OFFSET) +#define HCS12_SCI0_DRH (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_DRH_OFFSET) +#define HCS12_SCI0_DRL (HCS12_REG_BASE+HCS12_SCI0_BASE+HCS12_SCI_DRL_OFFSET) + +#define HCS12_SCI1_BDH (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_BDH_OFFSET) +#define HCS12_SCI1_BDL (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_BDL_OFFSET) +#define HCS12_SCI1_CR1 (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_CR1_OFFSET) +#define HCS12_SCI1_CR2 (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_CR2_OFFSET) +#define HCS12_SCI1_SR1 (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_SR1_OFFSET) +#define HCS12_SCI1_SR2 (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_SR2_OFFSET) +#define HCS12_SCI1_DRH (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_DRH_OFFSET) +#define HCS12_SCI1_DRL (HCS12_REG_BASE+HCS12_SCI1_BASE+HCS12_SCI_DRL_OFFSET) /* Register Bit-Field Definitions ***************************************************/ diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_spiv3.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_spiv3.h index 052abe2c9..6469c4d8f 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_spiv3.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_spiv3.h @@ -57,11 +57,11 @@ /* Register Addresses ***************************************************************/ -#define HCS12_SPI_CR1 (HCS12_SPI_BASE+HCS12_SPI_CR1_OFFSET) -#define HCS12_SPI_CR2 (HCS12_SPI_BASE+HCS12_SPI_CR2_OFFSET) -#define HCS12_SPI_BR (HCS12_SPI_BASE+HCS12_SPI_BR_OFFSET) -#define HCS12_SPI_SR (HCS12_SPI_BASE+HCS12_SPI_SR_OFFSET) -#define HCS12_SPI_DR (HCS12_SPI_BASE+HCS12_SPI_DR_OFFSET) +#define HCS12_SPI_CR1 (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_CR1_OFFSET) +#define HCS12_SPI_CR2 (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_CR2_OFFSET) +#define HCS12_SPI_BR (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_BR_OFFSET) +#define HCS12_SPI_SR (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_SR_OFFSET) +#define HCS12_SPI_DR (HCS12_REG_BASE+HCS12_SPI_BASE+HCS12_SPI_DR_OFFSET) /* Register Bit-Field Definitions ***************************************************/ diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_start.S b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_start.S index aa87ac519..f39792ccb 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_start.S +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_start.S @@ -42,7 +42,7 @@ #include "mc9s12ne64_internal.h" #include "mc9s12ne64_mmcv4.h" -#include "mc9s12ne64_crg.h" +#include "mc9s12ne64_crgv4.h" #include "mc9s12ne64_flash.h" /**************************************************************************** diff --git a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h index 3fe2f4880..29d0fcd74 100755 --- a/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h +++ b/nuttx/arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h @@ -79,33 +79,33 @@ /* Register Addresses ***************************************************************/ -#define HCS12_TIM_TIOS (HCS12_TIM_BASE+HCS12_TIM_TIOS_OFFSET) -#define HCS12_TIM_CFORC (HCS12_TIM_BASE+HCS12_TIM_CFORC_OFFSET) -#define HCS12_TIM_OC7M (HCS12_TIM_BASE+HCS12_TIM_OC7M_OFFSET) -#define HCS12_TIM_OC7D (HCS12_TIM_BASE+HCS12_TIM_OC7D_OFFSET) -#define HCS12_TIM_TCNTHI2 (HCS12_TIM_BASE+HCS12_TIM_TCNTHI2_OFFSET) -#define HCS12_TIM_TCNTLO2 (HCS12_TIM_BASE+HCS12_TIM_TCNTLO2_OFFSET) -#define HCS12_TIM_TSCR1 (HCS12_TIM_BASE+HCS12_TIM_TSCR1_OFFSET) -#define HCS12_TIM_TTOV (HCS12_TIM_BASE+HCS12_TIM_TTOV_OFFSET) -#define HCS12_TIM_TCTL1 (HCS12_TIM_BASE+HCS12_TIM_TCTL1_OFFSET) -#define HCS12_TIM_TCTL3 (HCS12_TIM_BASE+HCS12_TIM_TCTL3_OFFSET) -#define HCS12_TIM_TIE (HCS12_TIM_BASE+HCS12_TIM_TIE_OFFSET) -#define HCS12_TIM_TSCR2 (HCS12_TIM_BASE+HCS12_TIM_TSCR2_OFFSET) -#define HCS12_TIM_TFLG1 (HCS12_TIM_BASE+HCS12_TIM_TFLG1_OFFSET) -#define HCS12_TIM_TFLG2 (HCS12_TIM_BASE+HCS12_TIM_TFLG2_OFFSET) -#define HCS12_TIM_TC4HI (HCS12_TIM_BASE+HCS12_TIM_TC4HI_OFFSET) -#define HCS12_TIM_TC4LO (HCS12_TIM_BASE+HCS12_TIM_TC4LO_OFFSET) -#define HCS12_TIM_TC5HI (HCS12_TIM_BASE+HCS12_TIM_TC5HI_OFFSET) -#define HCS12_TIM_TC5LO (HCS12_TIM_BASE+HCS12_TIM_TC6HI_OFFSET) -#define HCS12_TIM_TC6HI (HCS12_TIM_BASE+HCS12_TIM_TC6LO_OFFSET) -#define HCS12_TIM_TC6LO (HCS12_TIM_BASE+HCS12_TIM_TC7HI_OFFSET) -#define HCS12_TIM_TC7HI (HCS12_TIM_BASE+HCS12_TIM_TC7LO_OFFSET) -#define HCS12_TIM_TC7LO (HCS12_TIM_BASE+HCS12_TIM_PACTL_OFFSET) -#define HCS12_TIM_PACTL (HCS12_TIM_BASE+HCS12_TIM_PAFLG_OFFSET) -#define HCS12_TIM_PAFLG (HCS12_TIM_BASE+HCS12_TIM_PACNTHI_OFFSET) -#define HCS12_TIM_PACNTHI (HCS12_TIM_BASE+HCS12_TIM_PACNTLO_OFFSET) -#define HCS12_TIM_PACNTLO (HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET) -#define HCS12_TIM_TIMTST2 (HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET) +#define HCS12_TIM_TIOS (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TIOS_OFFSET) +#define HCS12_TIM_CFORC (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_CFORC_OFFSET) +#define HCS12_TIM_OC7M (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_OC7M_OFFSET) +#define HCS12_TIM_OC7D (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_OC7D_OFFSET) +#define HCS12_TIM_TCNTHI2 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TCNTHI2_OFFSET) +#define HCS12_TIM_TCNTLO2 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TCNTLO2_OFFSET) +#define HCS12_TIM_TSCR1 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TSCR1_OFFSET) +#define HCS12_TIM_TTOV (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TTOV_OFFSET) +#define HCS12_TIM_TCTL1 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TCTL1_OFFSET) +#define HCS12_TIM_TCTL3 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TCTL3_OFFSET) +#define HCS12_TIM_TIE (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TIE_OFFSET) +#define HCS12_TIM_TSCR2 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TSCR2_OFFSET) +#define HCS12_TIM_TFLG1 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TFLG1_OFFSET) +#define HCS12_TIM_TFLG2 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TFLG2_OFFSET) +#define HCS12_TIM_TC4HI (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TC4HI_OFFSET) +#define HCS12_TIM_TC4LO (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TC4LO_OFFSET) +#define HCS12_TIM_TC5HI (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TC5HI_OFFSET) +#define HCS12_TIM_TC5LO (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TC6HI_OFFSET) +#define HCS12_TIM_TC6HI (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TC6LO_OFFSET) +#define HCS12_TIM_TC6LO (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TC7HI_OFFSET) +#define HCS12_TIM_TC7HI (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TC7LO_OFFSET) +#define HCS12_TIM_TC7LO (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_PACTL_OFFSET) +#define HCS12_TIM_PACTL (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_PAFLG_OFFSET) +#define HCS12_TIM_PAFLG (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_PACNTHI_OFFSET) +#define HCS12_TIM_PACNTHI (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_PACNTLO_OFFSET) +#define HCS12_TIM_PACNTLO (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET) +#define HCS12_TIM_TIMTST2 (HCS12_REG_BASE+HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET) /* Register Bit-Field Definitions ***************************************************/ |