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| author | Gregory Nutt <gnutt@nuttx.org> | 2015-02-28 11:54:47 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2015-02-28 11:54:47 -0600 |
| commit | 3e7f22d582c74d4109c4069ff104f2c5e901d4ca (patch) | |
| tree | a297c18fc0be553222dcbe8ee14aab572f3e737c /nuttx/arch/mips/src | |
| parent | 5f990259ede6fc8497557513351d3de7b9c4d6a4 (diff) | |
| download | px4-nuttx-3e7f22d582c74d4109c4069ff104f2c5e901d4ca.tar.gz px4-nuttx-3e7f22d582c74d4109c4069ff104f2c5e901d4ca.tar.bz2 px4-nuttx-3e7f22d582c74d4109c4069ff104f2c5e901d4ca.zip | |
PIC32MZ: Fix some configuration settings and POSC mode should be external clock
Diffstat (limited to 'nuttx/arch/mips/src')
| -rw-r--r-- | nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/mips/src/pic32mz/pic32mz-config.h | 10 |
2 files changed, 7 insertions, 5 deletions
diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h index 7ff410044..7cc9b2634 100644 --- a/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h +++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mzec-features.h @@ -439,6 +439,8 @@ #define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */ #define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT) # define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */ +# define DEVCFG1_DMTCNT_MIN (0 << DEVCFG1_DMTCNT_SHIFT) /* 2**8 (256) */ +# define DEVCFG1_DMTCNT_MAX (12 << DEVCFG1_DMTCNT_SHIFT) /* 2**318 (2147483648) */ #define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */ #define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */ diff --git a/nuttx/arch/mips/src/pic32mz/pic32mz-config.h b/nuttx/arch/mips/src/pic32mz/pic32mz-config.h index 38c49798c..5440fecaf 100644 --- a/nuttx/arch/mips/src/pic32mz/pic32mz-config.h +++ b/nuttx/arch/mips/src/pic32mz/pic32mz-config.h @@ -211,13 +211,13 @@ #if (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 5000000 # error BOARD_PLL_INPUT / BOARD_PLL_IDIV too low # define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_BYPASS /* < 5 MHz */ -#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 9000000 +#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 8000000 # define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_5_10MHZ /* 5-10 MHz */ -#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 14500000 +#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 13000000 # define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_8_16MHZ /* 8-16 MHz */ -#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 23500000 +#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 210000000 # define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_13_26MHZ /* 13-26 MHz */ -#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 39000000 +#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 36000000 # define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_21_42MHZ /* 21-42 MHz */ #elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 64000000 # define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_34_64MHZ /* 36-64 MHz */ @@ -393,7 +393,7 @@ #define CONFIG_PIC32MZ_WDTSPGM DEVCFG1_WDTSPGM_STOP #define CONFIG_PIC32MZ_WINDIS DEVCFG1_WDT_NORMAL #define CONFIG_PIC32MZ_FWDTWINSZ DEVCFG1_FWDTWINSZ_25 -#define CONFIG_PIC32MZ_DMTCNT DEVCFG1_DMTCNT_MASK +#define CONFIG_PIC32MZ_DMTCNT DEVCFG1_DMTCNT_MAX #define CONFIG_PIC32MZ_FDMTEN 0 /* DEVCFG0 */ |