Add on-demand paging support to ARM9 prefetch abort handler

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2860 42af7a65-404d-4744-a932-0658087f49c3

3 files changed, 75 insertions, 20 deletions

diff --git a/nuttx/arch/arm/include/arm/irq.h b/nuttx/arch/arm/include/arm/irq.h
index 38ea20553..6e361d4f6 100644
--- a/nuttx/arch/arm/include/arm/irq.h
+++ b/nuttx/arch/arm/include/arm/irq.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/include/arm/irq.h
  *
- *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/nuttx/arch/arm/src/arm/up_prefetchabort.c b/nuttx/arch/arm/src/arm/up_prefetchabort.c
index 3d6f5b8d8..13d4f5a07 100644
--- a/nuttx/arch/arm/src/arm/up_prefetchabort.c
+++ b/nuttx/arch/arm/src/arm/up_prefetchabort.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  *  arch/arm/src/src/up_prefetchabort.c
  *
- *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -41,7 +41,11 @@
 
 #include <stdint.h>
 #include <debug.h>
+
 #include <nuttx/irq.h>
+#ifdef CONFIG_PAGING
+#  include <nuttx/page.h>
+#endif
 
 #include "os_internal.h"
 #include "up_internal.h"
@@ -50,6 +54,20 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+/* Configuration ************************************************************/
+
+#ifdef CONFIG_PAGING
+#  ifndef CONFIG_PAGING_PAGESIZE
+#    error "CONFIG_PAGING_PAGESIZE is not defined in your .config file"
+#  endif
+#  ifndef CONFIG_PAGING_NLOCKED
+#    error "CONFIG_PAGING_NLOCKED is not defined in your .config file"
+#  endif
+#  ifndef CONFIG_PAGING_NPAGES
+#    error "CONFIG_PAGING_NPAGES is not defined in your .config file"
+#  endif
+#endif
+
 /* Output debug info if stack dump is selected -- even if 
  * debug is not selected.
  */
@@ -77,7 +95,43 @@
 
 void up_prefetchabort(uint32_t *regs)
 {
-  lldbg("Prefetch abort at 0x%x\n", regs[REG_PC]);
+  /* Save the saved processor context in current_regs where it can be accessed
+   * for register dumps and possibly context switching.
+   */
+
   current_regs = regs;
-  PANIC(OSERR_ERREXCEPTION);
+
+#ifdef CONFIG_PAGING
+  /* Get the (virtual) address of instruction that caused the prefetch abort.
+   * When the exception occurred, this address was provide in the lr register
+   * and this value was saved in the context save area as the PC at the
+   * REG_R15 index.
+   *
+   * Check to see if this miss address is within the configured range of
+   * virtual addresses.
+   */
+
+  if (regs[REG_R15] >= CONFIG_PAGING_PAGEDBASE &&
+      regs[REG_R15] <  CONFIG_PAGING_PAGEDEND)
+    {
+      /* Call pg_miss() to schedule the page fill.  A consequences of this
+       * call are:
+       *
+       * (1) The currently executing task will be blocked and saved on
+       *     on the g_waitingforfill task list.
+       * (2) An interrupt-level context switch will occur so that when
+       *     this function returns, it will return to a different task,
+       *     most likely the page fill worker thread.
+       * (3) The page fill worker task has been signalled and should
+       *     execute immediately when we return from this exception.
+       */
+
+      pg_miss();
+    }
+  else
+#endif
+    {
+      lldbg("Prefetch abort at 0x%x\n", regs[REG_PC]);
+      PANIC(OSERR_ERREXCEPTION);
+    }
 }
diff --git a/nuttx/arch/arm/src/arm/up_vectors.S b/nuttx/arch/arm/src/arm/up_vectors.S
index 987b875ce..6072e6387 100644
--- a/nuttx/arch/arm/src/arm/up_vectors.S
+++ b/nuttx/arch/arm/src/arm/up_vectors.S
@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/arm/up_vectors.S
  *
- *   Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -82,8 +82,8 @@ g_aborttmp:
  * Name: up_vectorirq
  *
  * Description:
- *   Interrupt excetpion. Entered in IRQ mode with spsr = SVC
- *   CPSR, lr = SVC PC
+ *   Interrupt excetpion. Entered in IRQ mode with spsr = SVC CPSR, lr = SVC PC
+ *
  ************************************************************************************/
 
 	.globl	up_vectorirq
@@ -91,7 +91,6 @@ g_aborttmp:
 up_vectorirq:
 	/* On entry, we are in IRQ mode.  We are free to use
 	 * the IRQ mode r13 and r14.
-         *
 	 */
 
 	ldr	r13, .Lirqtmp
@@ -159,7 +158,8 @@ up_vectorirq:
  * Function: up_vectorswi
  * 
  * Description:
- *   SWI interrupt. We enter the SWI in SVC mode
+ *   SWI interrupt. We enter the SWI in SVC mode.
+ *
  ************************************************************************************/
 
 	.globl	up_vectorswi
@@ -205,9 +205,10 @@ up_vectorswi:
  * Name: up_vectordata
  *
  * Description:
- *   Data abort Exception dispatcher. Give control to data
- *   abort handler.  This function is entered in ABORT mode
- *   with spsr = SVC CPSR, lr = SVC PC
+ *   This is the data abort exception dispatcher. The ARM data abort exception occurs
+ *   when a memory fault is detected during a data transfer.  This handler saves the
+ *   current processor state and gives control to data abort handler.  This function
+ *   is entered in ABORT mode with spsr = SVC CPSR, lr = SVC PC
  *
  ************************************************************************************/
 	
@@ -274,8 +275,11 @@ up_vectordata:
  * Name: up_vectorprefetch
  *
  * Description:
- *    Prefetch abort exception.  Entered in ABT mode with
- *    spsr = SVC CPSR, lr = SVC PC
+ *   This is the prefetch abort exception dispatcher. The ARM prefetch abort exception
+ *   occurs when a memory fault is detected during an an instruction fetch.  This
+ *   handler saves the current processor state and gives control to prefetch abort
+ *   handler.  This function is entered in ABT mode with spsr = SVC CPSR, lr = SVC PC.
+ *
  ************************************************************************************/
 	
 	.globl	up_vectorprefetch
@@ -341,8 +345,8 @@ up_vectorprefetch:
  * Name: up_vectorundefinsn
  *
  * Description:
- *   Undefined instruction entry exception.  Entered in
- *   UND mode, spsr = SVC  CPSR, lr = SVC PC
+ *   Undefined instruction entry exception.  Entered in UND mode, spsr = SVC  CPSR,
+ *   lr = SVC PC
  *
  ************************************************************************************/
 	
@@ -409,6 +413,7 @@ up_vectorundefinsn:
  *
  * Description:
  *   Shouldn't happen
+ *
  ************************************************************************************/
 
 	.globl	up_vectorfiq
@@ -419,10 +424,6 @@ up_vectorfiq:
 
 /************************************************************************************
  *  Name: up_interruptstack/g_userstack
- *
- * Description:
- *   Shouldn't happen
- *
  ************************************************************************************/
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3