SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz

3 files changed, 4 insertions, 4 deletions

diff --git a/nuttx/arch/arm/src/sama5/chip/sam_hsmci.h b/nuttx/arch/arm/src/sama5/chip/sam_hsmci.h
index 8c3782065..9cc286aea 100644
--- a/nuttx/arch/arm/src/sama5/chip/sam_hsmci.h
+++ b/nuttx/arch/arm/src/sama5/chip/sam_hsmci.h
@@ -174,7 +174,7 @@
 #define HSMCI_MR_WRPROOF              (1 << 12) /* Bit 12: Write Proof Enable */
 #define HSMCI_MR_FBYTE                (1 << 13) /* Bit 13: Force Byte Transfer */
 #define HSMCI_MR_PADV                 (1 << 14) /* Bit 14: Padding Value */
-#define HSMCI_MR_CLKODD               (1 << 15) /* Bit 15: Clock divider is odd */
+#define HSMCI_MR_CLKODD               (1 << 16) /* Bit 15: Clock divider is odd */
 
 /* HSMCI Data Timeout Register */
 
diff --git a/nuttx/arch/arm/src/sama5/sam_clockconfig.c b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
index 859550a6f..f8ecdbd10 100644
--- a/nuttx/arch/arm/src/sama5/sam_clockconfig.c
+++ b/nuttx/arch/arm/src/sama5/sam_clockconfig.c
@@ -374,7 +374,7 @@ static inline void sam_usbclockconfig(void)
  * Description:
  *   Called to initialize the SAM3/4.  This does whatever setup is needed to
  *   put the SoC in a usable state.  This includes the initialization of
- *   clocking using the settings in board.h.  (After power-on reset, the SAM3/4
+ *   clocking using the settings in board.h.  (After power-on reset, the SAMA5
  *   is initially running on a 12MHz internal RC clock).  This function also
  *   performs other low-level chip initialization of the chip including master
  *   clock, IRQ & watchdog configuration.
diff --git a/nuttx/arch/arm/src/sama5/sam_hsmci.c b/nuttx/arch/arm/src/sama5/sam_hsmci.c
index ae7350146..759a850cc 100644
--- a/nuttx/arch/arm/src/sama5/sam_hsmci.c
+++ b/nuttx/arch/arm/src/sama5/sam_hsmci.c
@@ -1612,10 +1612,10 @@ static void sam_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
   uint32_t regval;
   bool enable = true;
 
-  /* Fetch the current mode register and mask out the clkdiv (and pwsdiv) */
+  /* Fetch the current mode register and mask out the clkdiv+clockodd (and pwsdiv) */
 
   regval = sam_getreg(priv, SAM_HSMCI_MR_OFFSET);
-  regval &= ~(HSMCI_MR_CLKDIV_MASK | HSMCI_MR_PWSDIV_MASK);
+  regval &= ~(HSMCI_MR_CLKDIV_MASK | HSMCI_MR_PWSDIV_MASK | HSMCI_MR_CLKODD);
 
  /* These clock devisor values that must be defined in the board-specific
   * board.h header file: HSMCI_INIT_CLKDIV, HSMCI_MMCXFR_CLKDIV,