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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-06-28 14:32:08 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-06-28 14:32:08 -0600 |
| commit | ee6d71b6242b37666c09cc480e6df1ae44654b83 (patch) | |
| tree | f1ff322c514444cf3f0c069379bd9bb36d39100d /nuttx/arch | |
| parent | 536282da5a248b4edd37aa9724fe5b51b2af3d79 (diff) | |
| download | px4-nuttx-ee6d71b6242b37666c09cc480e6df1ae44654b83.tar.gz px4-nuttx-ee6d71b6242b37666c09cc480e6df1ae44654b83.tar.bz2 px4-nuttx-ee6d71b6242b37666c09cc480e6df1ae44654b83.zip | |
Add an NSH configuration for the Arduino Due; Pluse several fixes related to the Due and to the SAM3X in general
Diffstat (limited to 'nuttx/arch')
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3x_memorymap.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/sam_allocateheap.c | 10 |
2 files changed, 11 insertions, 1 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3x_memorymap.h b/nuttx/arch/arm/src/sam34/chip/sam3x_memorymap.h index 47ce5d831..4cad06dc0 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3x_memorymap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3x_memorymap.h @@ -65,7 +65,7 @@ /* Internal SRAM memory region */ #define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: Internal SRAM 0 */ -#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 0 */ +#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */ #define SAM_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x2017ffff: NAND FLASH controller (SRAM) */ #define SAM_UOTGHSRAM_BASE 0x20180000 /* 0x20100000-0x201fffff: UOTGHS controller (DMA) */ /* 0x20200000-0x201fffff: Undefined */ diff --git a/nuttx/arch/arm/src/sam34/sam_allocateheap.c b/nuttx/arch/arm/src/sam34/sam_allocateheap.c index 763a9ba19..93fae363d 100644 --- a/nuttx/arch/arm/src/sam34/sam_allocateheap.c +++ b/nuttx/arch/arm/src/sam34/sam_allocateheap.c @@ -53,6 +53,7 @@ #include "chip.h" #include "sam_mpuinit.h" +#include "sam_periphclks.h" /**************************************************************************** * Private Definitions @@ -317,6 +318,15 @@ void up_addregion(void) #endif /* HAVE_SRAM1_REGION */ #ifdef HAVE_NFCSRAM_REGION +#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) + /* In the 3X/3A family I note that clocking must appled to the SMC module + * in order for the NFCS SRAM to be functional. I don't recall such an + * issue with the 3U. + */ + + sam_smc_enableclk(); +#endif + /* Allow user access to the heap memory */ sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); |