diff options
author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-02-26 16:55:39 +0000 |
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committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-02-26 16:55:39 +0000 |
commit | aebc66f8e146b28148f5e5755f6b3252774441f8 (patch) | |
tree | 92a85e68ccfe7771cb3684247ac04c4877fbe4e8 /nuttx/arch | |
parent | 11cdbe3e35d80775ba9887a995a1e3c124c7a063 (diff) | |
download | px4-nuttx-aebc66f8e146b28148f5e5755f6b3252774441f8.tar.gz px4-nuttx-aebc66f8e146b28148f5e5755f6b3252774441f8.tar.bz2 px4-nuttx-aebc66f8e146b28148f5e5755f6b3252774441f8.zip |
Finish m9s12 GPIO support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3318 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/arch')
-rwxr-xr-x | nuttx/arch/hc/include/m9s12/irq.h | 65 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/m9s12/Make.defs | 10 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c | 207 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/m9s12/m9s12_gpio.c | 111 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c | 199 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/m9s12/m9s12_internal.h | 55 | ||||
-rwxr-xr-x | nuttx/arch/hc/src/m9s12/m9s12_irq.c | 2 |
7 files changed, 575 insertions, 74 deletions
diff --git a/nuttx/arch/hc/include/m9s12/irq.h b/nuttx/arch/hc/include/m9s12/irq.h index 9df447b14..30bed2d4c 100755 --- a/nuttx/arch/hc/include/m9s12/irq.h +++ b/nuttx/arch/hc/include/m9s12/irq.h @@ -97,8 +97,69 @@ #define HCS12_IRQ_VEMACLC 36 /* ffa2: EMAC late collision */ #define HCS12_IRQ_VEMACEC 37 /* ffa0: EMAC excessive collision */ /* ff80-ff9f: Reserved */ -#define HCS12_IRQ_VILLEGAL 38 /* Any reserved vector */ -#define NR_IRQS 39 +#define HCS12_IRQ_NVECTORS 38 + +/* GPIO interrupts. The m9s12x supports several interrupts on PIM ports G, H, + * and J. We go through some special efforts to keep the number of IRQs + * to a minimum in this sparse interrupt case. + * + * Port G: Pins 0-7 + * Port H: Pins 0-6 + * Port J: Pins 0-3 and 6-7 + */ + +#ifdef CONFIG_GPIO_IRQ + +/* To conserve space, interrupts must also be configured, port by port */ + +# define HCC12_IRQ_PGFIRST HCS12_IRQ_NVECTORS +# ifdef CONFIG_HCS12_PORTG_INTS +# define HCS12_IRQ_PGSET 0xff +# define HCS12_IRQ_PG0 (HCC12_IRQ_PGFIRST+0) +# define HCS12_IRQ_PG1 (HCC12_IRQ_PGFIRST+1) +# define HCS12_IRQ_PG2 (HCC12_IRQ_PGFIRST+2) +# define HCS12_IRQ_PG3 (HCC12_IRQ_PGFIRST+3) +# define HCS12_IRQ_PG4 (HCC12_IRQ_PGFIRST+4) +# define HCS12_IRQ_PG5 (HCC12_IRQ_PGFIRST+5) +# define HCS12_IRQ_PG6 (HCC12_IRQ_PGFIRST+6) +# define HCS12_IRQ_PG7 (HCC12_IRQ_PGFIRST+7) +# define HCC12_IRQ_PHFIRST (HCC12_IRQ_PGFIRST+8) +# else +# define HCC12_IRQ_PHFIRST HCC12_IRQ_PGFIRST +# endif + +# ifdef CONFIG_HCS12_PORTH_INTS +# define HCS12_IRQ_PHSET 0x7f +# define HCS12_IRQ_PH0 (HCC12_IRQ_PHFIRST+0) +# define HCS12_IRQ_PH1 (HCC12_IRQ_PHFIRST+1) +# define HCS12_IRQ_PH2 (HCC12_IRQ_PHFIRST+2) +# define HCS12_IRQ_PH3 (HCC12_IRQ_PHFIRST+3) +# define HCS12_IRQ_PH4 (HCC12_IRQ_PHFIRST+4) +# define HCS12_IRQ_PH5 (HCC12_IRQ_PHFIRST+5) +# define HCS12_IRQ_PH6 (HCC12_IRQ_PHFIRST+6) +# define HCC12_IRQ_PJFIRST (HCC12_IRQ_PHFIRST+7) +# else +# define HCC12_IRQ_PJFIRST HCC12_IRQ_PHFIRST +# endif + +# ifdef CONFIG_HCS12_PORTJ_INTS +# define HCS12_IRQ_PJSET 0xcf +# define HCS12_IRQ_PJ0 (HCC12_IRQ_PJFIRST+0) +# define HCS12_IRQ_PJ1 (HCC12_IRQ_PJFIRST+1) +# define HCS12_IRQ_PJ2 (HCC12_IRQ_PJFIRST+2) +# define HCS12_IRQ_PJ3 (HCC12_IRQ_PJFIRST+3) +# define HCS12_IRQ_PJ6 (HCC12_IRQ_PJFIRST+4) +# define HCS12_IRQ_PJ7 (HCC12_IRQ_PJFIRST+5) +# define HCS12_IRQ_NIRQS (HCC12_IRQ_PJFIRST+6) +# else +# define HCS12_IRQ_NIRQS HCC12_IRQ_PJFIRST +# endif +#else +# define HCS12_IRQ_NIRQS HCS12_IRQ_NVECTORS +#endif /* CONFIG_GPIO_IRQ */ + +#define HCS12_IRQ_VILLEGAL HCS12_IRQ_NIRQS /* Any reserved vector */ +#define NR_IRQS (HCS12_IRQ_NIRQS+1) /************************************************************************************ * Public Types diff --git a/nuttx/arch/hc/src/m9s12/Make.defs b/nuttx/arch/hc/src/m9s12/Make.defs index ea9d1934c..e7c0109ee 100755 --- a/nuttx/arch/hc/src/m9s12/Make.defs +++ b/nuttx/arch/hc/src/m9s12/Make.defs @@ -43,13 +43,9 @@ CMN_CSRCS = up_allocateheap.c up_blocktask.c up_copystate.c up_createstack.c \ up_udelay.c up_unblocktask.c up_usestack.c CHIP_ASRCS = m9s12_start.S m9s12_lowputc.S m9s12_saveusercontext.S -CHIP_CSRCS = m9s12_assert.c m9s12_gpio.c m9s12_initialstate.c m9s12_irq.c \ - m9s12_serial.c m9s12_timerisr.c - -ifeq ($(CONFIG_GPIO_IRQ),y) -CHIP_CSRCS += m9s12_gpioint.c -endif +CHIP_CSRCS = m9s12_assert.c m9s12_gpio.c m9s12_gpioirq.c m9s12_initialstate.c \ + m9s12_irq.c m9s12_serial.c m9s12_timerisr.c ifeq ($(CONFIG_DEBUG_GPIO),y) -CHIP_CSRCS += m9s12_gpiodbg.c +CHIP_CSRCS += m9s12_dumpgpio.c endif diff --git a/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c b/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c index a10983a4d..13a84dacf 100755 --- a/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_dumpgpio.c @@ -41,8 +41,13 @@ #include <nuttx/config.h> #include <stdint.h> +#include <debug.h> +#include <arch/irq.h> +#include "up_arch.h" #include "m9s12_internal.h" +#include "m9s12_pim.h" +#include "m9s12_mebi.h" #ifdef CONFIG_DEBUG_GPIO @@ -50,10 +55,95 @@ * Definitions ****************************************************************************/ +/* PIM ports (T,S,G,H,J,L) */ + +#define HCS12_PIM_NPORTS 6 + +/* MEBI ports (A,B,E,K) */ + +#define HCS12_MEBI_NPORTS 4 + +/* Decoding helper macros */ + +#define HCS12_PIN(cfg) (((cfg) & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT) +#define HCS12_PORTNDX(cfg) (((cfg) >> GPIO_PORT_SHIFT) & 7) +#define HCS12_PIMPORT(cfg) (((cfg) & GPIO_PORT_PIM) != 0) +#define HCS12_MEBIPORT(cfg) (((cfg) & GPIO_PORT_PIM) == 0) + +#define HCS12_PULL(cfg) (((cfg) & GPIO_PULLUP_MASK) >> GPIO_PULLUP_SHIFT) +# define HCS12_PULL_NONE 0 +# define HCS12_PULL_POLARITY 1 +# define HCS12_PULL_ENABLE 2 +# define HCS12_PULL_UP 2 +# define HCS12_PULL_DOWN 3 + +#define HCS12_INTERRUPT(cfg) (((cfg) & GPIO_INT_MASK) >> GPIO_INT_SHIFT) +# define HCS12_INT_NONE 0 +# define HCS12_INT_POLARITY 1 +# define HCS12_INT_ENABLE 2 +# define HCS12_INT_FALLING 2 +# define HCS12_INT_RISING 3 + +/* PIM ports have the following forms: + * + * FORM 1: IO INPUT DDR RDR PER PS Port T + * FORM 2: IO INPUT DDR RDR PER PS WOM Port S,L + * FORM 3: IO INPUT DDR RDR PER PS IE IF Port G,H,J + */ + +#define PIMPORT_FORM1 0 +#define PIMPORT_FORM2 1 +#define PIMPORT_FORM3 2 + +/* MEBI ports are pretty strange. Most look the same, but E and K can have + * some special attributes. + */ + +#define MEBIPORT_AB 0 +#define MEBIPORT_E 1 +#define MEBIPORT_K 2 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct gpio_piminfo_s +{ + uint16_t base; /* PIM GPIO block base address */ + char name; /* Port name */ + uint8_t form; /* Form of the PIM GPIO block registers */ +}; + +struct gpio_mebiinfo_s +{ + uint16_t data; /* MEBI data register address */ + uint16_t ddr; /* MEBI ddr register address */ + char name; /* Port name */ + uint8_t form; /* Form of the MEBI port */ +}; + /**************************************************************************** * Public Data ****************************************************************************/ +static const struct gpio_piminfo_s piminfo[HCS12_PIM_NPORTS] = +{ + {HCS12_PIM_PORTT_BASE, 'T', PIMPORT_FORM1}, /* Port T */ + {HCS12_PIM_PORTS_BASE, 'S', PIMPORT_FORM2}, /* Port S */ + {HCS12_PIM_PORTG_BASE, 'G', PIMPORT_FORM3}, /* Port G */ + {HCS12_PIM_PORTH_BASE, 'H', PIMPORT_FORM3}, /* Port H */ + {HCS12_PIM_PORTJ_BASE, 'J', PIMPORT_FORM3}, /* Port J */ + {HCS12_PIM_PORTL_BASE, 'L', PIMPORT_FORM2} /* Port L */ +}; + +static const struct gpio_mebiinfo_s mebiinfo[HCS12_MEBI_NPORTS] = +{ + {HCS12_MEBI_PORTA, HCS12_MEBI_DDRA, 'A', MEBIPORT_AB}, /* Port A */ + {HCS12_MEBI_PORTB, HCS12_MEBI_DDRB, 'B', MEBIPORT_AB}, /* Port B */ + {HCS12_MEBI_PORTE, HCS12_MEBI_DDRE, 'E', MEBIPORT_E}, /* Port E */ + {HCS12_MEBI_PORTK, HCS12_MEBI_DDRK, 'K', MEBIPORT_K} /* Port K */ +}; + /**************************************************************************** * Private Data ****************************************************************************/ @@ -63,6 +153,105 @@ ****************************************************************************/ /**************************************************************************** + * Name: hcs12_pimdump + * + * Description: + * PIM GPIO register block dump + * + ****************************************************************************/ + +static inline void hcs12_pimdump(uint8_t portndx) +{ + const struct gpio_piminfo_s *ptr; + + if (portndx >= HCS12_PIM_NPORTS) + { + lldbg(" Illegal PIM port index: %d\n", portndx); + return; + } + + ptr = &piminfo[portndx]; + lldbg(" PIM Port%c:\n", ptr->name); + lldbg(" IO:%02x INP:%02x DDR:%02x RDR:%02x\n", + getreg8(ptr->base+HCS12_PIM_IO_OFFSET), + getreg8(ptr->base+HCS12_PIM_INPUT_OFFSET), + getreg8(ptr->base+HCS12_PIM_DDR_OFFSET), + getreg8(ptr->base+HCS12_PIM_RDR_OFFSET)); + + switch (ptr->form) + { + case PIMPORT_FORM1: + lldbg(" PER:%02x PS:%02x\n", + getreg8(ptr->base+HCS12_PIM_PER_OFFSET), + getreg8(ptr->base+HCS12_PIM_PS_OFFSET)); + break; + + case PIMPORT_FORM2: + lldbg(" PER:%02x PS:%02x WOM:%02x\n", + getreg8(ptr->base+HCS12_PIM_PER_OFFSET), + getreg8(ptr->base+HCS12_PIM_PS_OFFSET), + getreg8(ptr->base+HCS12_PIM_WOM_OFFSET)); + break; + + case PIMPORT_FORM3: + lldbg(" PER:%02x PS:%02x IE:%02x IF:%02x\n", + getreg8(ptr->base+HCS12_PIM_PER_OFFSET), + getreg8(ptr->base+HCS12_PIM_PS_OFFSET), + getreg8(ptr->base+HCS12_PIM_IE_OFFSET), + getreg8(ptr->base+HCS12_PIM_IF_OFFSET)); + break; + + default: + break; + } +} + +/**************************************************************************** + * Name: hcs12_mebidump + * + * Description: + * PIM GPIO register block dump + * + ****************************************************************************/ + +static inline void hcs12_mebidump(uint8_t portndx) +{ + const struct gpio_mebiinfo_s *ptr; + + if (portndx >= HCS12_MEBI_NPORTS) + { + lldbg(" Illegal MEBI port index: %d\n", portndx); + return; + } + + ptr = &mebiinfo[portndx]; + lldbg(" MEBI Port%c:\n", ptr->name); + + switch (ptr->form) + { + case MEBIPORT_AB: + lldbg(" DATA:%02x DDR:%02x\n", + getreg8(ptr->data), getreg8(ptr->ddr)); + break; + + case MEBIPORT_E: + lldbg(" DATA:%02x DDR:%02x MODE:%02x PEAR:%02x\n", + getreg8(ptr->data), getreg8(ptr->ddr), + getreg8(HCS12_MEBI_MODE), getreg8(HCS12_MEBI_PEAR)); + break; + + case MEBIPORT_K: + lldbg(" DATA:%02x DDR:%02x MODE:%02x\n", + getreg8(ptr->data), getreg8(ptr->ddr), + getreg8(HCS12_MEBI_MODE)); + break; + + default: + break; + } +} + +/**************************************************************************** * Public Functions ****************************************************************************/ @@ -76,8 +265,22 @@ int hcs12_dumpgpio(uint16_t pinset, const char *msg) { -#warning "Not implemented" - return -ENOSYS; + uint8_t portndx = HCS12_PORTNDX(pinset); + irqstate_t flags = irqsave(); + + lldbg("pinset: %08x -- %s\n", pinset, msg); + + if (HCS12_PIMPORT(pinset)) + { + hcs12_pimdump(portndx); + } + else + { + hcs12_mebidump(portndx); + } + + irqrestore(flags); + return OK; } #endif /* CONFIG_DEBUG_GPIO */ diff --git a/nuttx/arch/hc/src/m9s12/m9s12_gpio.c b/nuttx/arch/hc/src/m9s12/m9s12_gpio.c index 58e61094d..0f866dc87 100755 --- a/nuttx/arch/hc/src/m9s12/m9s12_gpio.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_gpio.c @@ -45,6 +45,8 @@ #include <assert.h> #include <errno.h> +#include <nuttx/arch.h> + #include "up_arch.h" #include "m9s12_internal.h" #include "m9s12_pim.h" @@ -57,17 +59,18 @@ * * The GPIO configuration is represented by a 16-bit value encoded as follows: * - * xxII OUUR DMGG GPPP - * || |||| ||| `-Pin number - * || |||| || `- Port number - * || |||| | `- PIM Ports - * || |||| `- Direction - * || |||`- Reduced drive - * || ||`- Polarity - * || |`- Pull up (or down) - * || `- Wired OR open drain - * |`- Interrupt or rising/falling (polarity) - * `- Interrupt + * xIIO UURV DMGG GPPP + * ||| |||| ||| `-Pin number + * ||| |||| || `- Port number + * ||| |||| | `- PIM Ports + * ||| |||| `- Direction + * ||| |||`- Initial value of output + * ||| ||`- Reduced drive + * ||| |`- Polarity + * ||| `- Pull up (or down) + * ||`- Wired OR open drain + * |`- Interrupt or rising/falling (polarity) + * `- Interrupt * * NOTE: MEBI ports E and K can have special configurations as controlled by * the PEAR and MODE registers. Those special configurations are not managed @@ -103,12 +106,13 @@ #define HCS12_IE_PORTS (HCS12_PORT_G|HCS12_PORT_H|HCS12_PORT_J) #define HCS12_IF_PORTS (HCS12_PORT_G|HCS12_PORT_H|HCS12_PORT_J) -/* Decoding help macros */ +/* Decoding helper macros */ #define HCS12_PIN(cfg) (((cfg) & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT) #define HCS12_PORTNDX(cfg) (((cfg) >> GPIO_PORT_SHIFT) & 7) #define HCS12_PIMPORT(cfg) (((cfg) & GPIO_PORT_PIM) != 0) #define HCS12_MEBIPORT(cfg) (((cfg) & GPIO_PORT_PIM) == 0) +#define HCS12_OUTPUT(cfg) (((cfg) & GPIO_DIRECTION) == GPIO_OUTPUT) #define HCS12_PULL(cfg) (((cfg) & GPIO_PULLUP_MASK) >> GPIO_PULLUP_SHIFT) # define HCS12_PULL_NONE 0 @@ -138,6 +142,10 @@ struct mebi_portaddr_s * Public Data ****************************************************************************/ +/**************************************************************************** + * Private Data + ****************************************************************************/ + static const struct mebi_portaddr_s mebi_portaddr[HCS12_MEBI_NPORTS] = { {HCS12_MEBI_PORTA, HCS12_MEBI_DDRA}, /* Port A */ @@ -152,10 +160,6 @@ static uint8_t mebi_bits[HCS12_MEBI_NPORTS] = }; /**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** * Private Functions ****************************************************************************/ @@ -163,6 +167,8 @@ static uint8_t mebi_bits[HCS12_MEBI_NPORTS] = * Misc. Low-Level, Inline Helper Functions ****************************************************************************/ +/* Set or clear a bit in a register */ + static inline void gpio_writebit(uint16_t regaddr, uint8_t pin, bool set) { uint8_t regval = getreg8(regaddr); @@ -177,28 +183,38 @@ static inline void gpio_writebit(uint16_t regaddr, uint8_t pin, bool set) putreg8(regval, regaddr); } +/* Return the value of a bit in a register */ + static inline bool gpio_readbit(uint16_t regaddr, uint8_t pin) { uint8_t regval = getreg8(regaddr); return ((regval & (1 << pin)) != 0); } +/* Set the direction of a PIM port */ + static inline void pim_direction(uint8_t portndx, uint8_t pin, bool output) { gpio_writebit(HCS12_PIM_PORT_DDR(portndx), pin, output); } +/* Set the direction of a MEBI port */ + static inline void mebi_direction(uint8_t portndx, uint8_t pin, bool output) { gpio_writebit(mebi_portaddr[portndx].ddr, pin, output); } +/* Write to the Wired-OR register of a PIM port */ + static inline void pim_opendrain(uint8_t portndx, uint8_t pin, bool opendrain) { DEBUGASSERT(!opendrain || (HCS12_WOM_PORTS & (1 << pin)) != 0); gpio_writebit(HCS12_PIM_PORT_WOM(portndx), pin, opendrain); } +/* Configure pull up resisters on on a PIM port pin */ + static inline void pim_pullpin(uint8_t portndx, uint8_t pin, uint8_t pull) { bool enable = false; @@ -217,6 +233,8 @@ static inline void pim_pullpin(uint8_t portndx, uint8_t pin, uint8_t pull) gpio_writebit(HCS12_PIM_PORT_PS(portndx), pin, polarity); } +/* Configure pull up resisters on on a while PIM port */ + static inline void mebi_pullport(uint8_t portndx, uint8_t pull) { uint8_t regval = getreg8(HCS12_MEBI_PUCR); @@ -231,11 +249,15 @@ static inline void mebi_pullport(uint8_t portndx, uint8_t pull) putreg8(regval, HCS12_MEBI_PUCR); } +/* Select/deselect reduced drive for a PIM port pin */ + static inline void pim_rdpin(uint8_t portndx, uint8_t pin, bool rdenable) { gpio_writebit(HCS12_PIM_PORT_RDR(portndx), pin, rdenable); } +/* Select/deselect reduced drive for a whole MEBI port */ + static inline void mebi_rdport(uint8_t portndx, bool rdenable) { uint8_t regval = getreg8(HCS12_MEBI_RDRIV); @@ -250,6 +272,8 @@ static inline void mebi_rdport(uint8_t portndx, bool rdenable) putreg8(regval, HCS12_MEBI_RDRIV); } +/* Configure the PIM port pin as a interrupt */ + static inline void pim_interrupt(uint8_t portndx, unsigned pin, uint8_t type) { if (type != HCS12_INT_NONE) @@ -268,7 +292,7 @@ static inline void pim_interrupt(uint8_t portndx, unsigned pin, uint8_t type) * Name: pim_configgpio * * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. + * Configure a PIM pin based on bit-encoded description of the pin. * ****************************************************************************/ @@ -281,34 +305,34 @@ static inline void pim_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin) DEBUGASSERT(portndx < HCS12_PIM_NPORTS); #ifdef CONFIG_DEBUG - if ((cfgset) & GPIO_INT_ENABLE) != 0) + if ((cfgset & GPIO_INT_ENABLE) != 0) { /* Yes.. then it must not be tagged as an output */ - ASSERT(((cfgset) & GPIO_DIRECTION) != GPIO_OUTPUT); + ASSERT((cfgset & GPIO_DIRECTION) != GPIO_OUTPUT); /* If the pull-driver is also enabled, it must be enabled with a * compatible priority. */ - if ((cfgset) & GPIO_PULL_ENABLE) != 0) + if ((cfgset & GPIO_PULL_ENABLE) != 0) { - if ((cfgset) & GPIO_INT_POLARITY) != 0) + if ((cfgset & GPIO_INT_POLARITY) != 0) { - ASSERT(((cfgset) & GPIO_PULL_POLARITY) != 0); + ASSERT((cfgset & GPIO_PULL_POLARITY) != 0); } else { - ASSERT(((cfgset) & GPIO_PULL_POLARITY) = 0); + ASSERT((cfgset & GPIO_PULL_POLARITY) == 0); } } } #endif - pim_direction(portndx, pin, (((cfgset) & GPIO_DIRECTION) == GPIO_OUTPUT)); - pim_opendrain(portndx, pin, (((cfgset) & GPIO_OPENDRAN) != 0)); + pim_direction(portndx, pin, ((cfgset & GPIO_DIRECTION) == GPIO_OUTPUT)); + pim_opendrain(portndx, pin, ((cfgset & GPIO_OPENDRAIN) != 0)); pim_pullpin(portndx, pin, HCS12_PULL(cfgset)); - pim_rdpin(portndx, pin, (((cfgset) & GPIO_REDUCED) != 0)); + pim_rdpin(portndx, pin, ((cfgset & GPIO_REDUCED) != 0)); pim_interrupt(portndx, pin, HCS12_INTERRUPT(cfgset)); } @@ -316,29 +340,33 @@ static inline void pim_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin) * Name: mebi_configgpio * * Description: - * Configure a GPIO pin based on bit-encoded description of the pin. + * Configure a MEBI pin based on bit-encoded description of the pin. * ****************************************************************************/ static inline void mebi_configgpio(uint16_t cfgset, uint8_t portndx, uint8_t pin) { DEBUGASSERT(portndx < HCS12_MEBI_NPORTS); - mebi_direction(portndx, pin, (((cfgset) & GPIO_DIRECTION) == GPIO_OUTPUT)); + mebi_direction(portndx, pin, ((cfgset & GPIO_DIRECTION) == GPIO_OUTPUT)); mebi_pullport(portndx, HCS12_PULL(cfgset)); - mebi_rdport(portndx, (((cfgset) & GPIO_REDUCED) != 0)); + mebi_rdport(portndx, ((cfgset & GPIO_REDUCED) != 0)); } /**************************************************************************** * Read/Write Helpers ****************************************************************************/ +/* Set the output state of a PIM port pin */ + static inline void pim_gpiowrite(uint8_t portndx, uint8_t pin, bool value) { - uint16_t regaddr = HCS12_PIM_PORT_IO(portndx) + uint16_t regaddr = HCS12_PIM_PORT_IO(portndx); DEBUGASSERT(portndx < HCS12_PIM_NPORTS); gpio_writebit(regaddr, pin, value); } +/* Set the output state of a MEBI port pin */ + static inline void mebi_gpiowrite(uint8_t portndx, uint8_t pin, bool value) { uint16_t regaddr; @@ -347,13 +375,17 @@ static inline void mebi_gpiowrite(uint8_t portndx, uint8_t pin, bool value) gpio_writebit(regaddr, pin, value); } +/* Get the current state of a PIM port pin */ + static inline bool pim_gpioread(uint8_t portndx, uint8_t pin) { - uint16_t regaddr = HCS12_PIM_PORT_INPUT(portndx) + uint16_t regaddr = HCS12_PIM_PORT_INPUT(portndx); DEBUGASSERT(portndx < HCS12_PIM_NPORTS); return gpio_readbit(regaddr, pin); } +/* Get the current state of a MEBI port pin */ + static inline bool mebi_gpioread(uint8_t portndx, uint8_t pin) { uint16_t regaddr; @@ -376,9 +408,13 @@ static inline bool mebi_gpioread(uint8_t portndx, uint8_t pin) int hcs12_configgpio(uint16_t cfgset) { + /* Get the port index and pin number */ + uint8_t portndx = HCS12_PORTNDX(cfgset); uint8_t pin = HCS12_PIN(cfgset); + /* Configure the pin */ + if (HCS12_PIMPORT(cfgset)) { pim_configgpio(cfgset, portndx, pin); @@ -387,6 +423,13 @@ int hcs12_configgpio(uint16_t cfgset) { mebi_configgpio(cfgset, portndx, pin); } + + /* If the pin is an output, then set the initial value of the output */ + + if (HCS12_OUTPUT(cfgset)) + { + hcs12_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_VALUE) == GPIO_OUTPUT_HIGH); + } return OK; } @@ -400,8 +443,9 @@ int hcs12_configgpio(uint16_t cfgset) void hcs12_gpiowrite(uint16_t pinset, bool value) { - uint8_t portndx = HCS12_PORTNDX(pinset); - uint8_t pin = HCS12_PIN(pinset); + uint8_t portndx = HCS12_PORTNDX(pinset); + uint8_t pin = HCS12_PIN(pinset); + irqstate_t flags = irqsave(); DEBUGASSERT((pinset & GPIO_DIRECTION) == GPIO_OUTPUT); if (HCS12_PIMPORT(pinset)) @@ -412,6 +456,7 @@ void hcs12_gpiowrite(uint16_t pinset, bool value) { mebi_gpiowrite(portndx, pin, value); } + irqrestore(flags); } /**************************************************************************** diff --git a/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c b/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c index cc45426e1..6d31513d2 100755 --- a/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_gpioirq.c @@ -40,9 +40,17 @@ #include <nuttx/config.h> -#include "m9s12_internal.h" +#include <stdint.h> +#include <errno.h> -#ifdef CONFIG_GPIO_IRQ +#include <nuttx/arch.h> +#include <nuttx/irq.h> +#include <arch/irq.h> + +#include "up_arch.h" +#include "m9s12_internal.h" +#include "m9s12_pim.h" +#include "m9s12_mebi.h" /**************************************************************************** * Definitions @@ -61,6 +69,145 @@ ****************************************************************************/ /**************************************************************************** + * Name: hcs12_gpioirqinitialize + * + * Description: + * Map an IRQ number to a port address and a bit number. + * + ****************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +static int hcs12_mapirq(int irq, uint16_t *regaddr, uint8_t *pin) +{ + if (irq >= HCC12_IRQ_PGFIRST) + { + /* Port G: Pins 0-7 */ + +#ifdef CONFIG_HCS12_PORTG_INTS + if (irq < HCC12_IRQ_PHFIRST) + { + *regaddr = HCS12_PIM_PORTG_IE; + *pin = irq - HCC12_IRQ_PGFIRST; + return OK; + } +#endif + + /* Port H: Pins 0-6 */ + +#ifdef CONFIG_HCS12_PORTH_INTS + if (irq < HCC12_IRQ_PJFIRST) + { + *regaddr = HCS12_PIM_PORTH_IE; + *pin = irq - HCC12_IRQ_PHFIRST; + return OK; + } +#endif + + /* Port J: Pins 0-3 and 6-7 */ + +#ifdef CONFIG_HCS12_PORTJ_INTS + if (irq < HCC12_IRQ_PJFIRST) + { + uint8_t pjpin = irq - HCC12_IRQ_PJFIRST; + if (irq >= HCS12_IRQ_PJ6) + { + pjpin += 2; + } + + *regaddr = HCS12_PIM_PORTJ_IE; + *pin = pjpin; + return OK; + } +#endif + } + return -EINVAL; +} +#endif /* CONFIG_GPIO_IRQ */ + +/**************************************************************************** + * Name: up_gpioa/b/cinterrupt + * + * Description: + * Receive GPIOA/B/C interrupts + * + ****************************************************************************/ + +#ifdef CONFIG_GPIO_IRQ +static int hcs12_interrupt(uint16_t base, int irq0, uint8_t valid, void *context) +{ + uint8_t pending; + uint8_t bit; + int irq; + + /* Get the set of enabled (unmasked) interrupts pending on this port */ + + pending = getreg8(base+HCS12_PIM_IF_OFFSET) && getreg8(base+HCS12_PIM_IE_OFFSET); + + /* Then check each bit in the set of interrupts */ + + for (bit = 1, irq = irq0; pending != 0; bit <<= 1) + { + /* We may need to skip over some bits in the interrupt register (without + * incrementing the irq value. + */ + + if ((valid & bit) != 0) + { + /* This is a real interrupt bit -- Check if an unmasked interrupt + * is pending. + */ + + if ((pending & bit) != 0) + { + /* Yes.. clear the pending interrupt by writing '1' to the + * flags registers. + */ + + putreg8(bit, base+HCS12_PIM_IF_OFFSET); + + /* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */ + + irq_dispatch(irq, context); + + /* Remove this from the set of pending interrupts */ + + pending &= ~bit; + } + + /* Bump up the IRQ number for the next pass through the loop */ + + irq++; + } + } + return OK; +} + +#ifdef CONFIG_HCS12_PORTG_INTS +static int hcs12_pginterrupt(int irq, void *context) +{ + return hcs12_interrupt(HCS12_PIM_PORTG_BASE, HCS12_IRQ_PG0, + HCS12_IRQ_PGSET, context); +} +#endif + +#ifdef CONFIG_HCS12_PORTH_INTS +static int hcs12_phinterrupt(int irq, void *context) +{ + return hcs12_interrupt(HCS12_PIM_PORTH_BASE, HCS12_IRQ_PH0, + HCS12_IRQ_PHSET, context); +} +#endif + +#ifdef CONFIG_HCS12_PORTJ_INTS +static int hcs12_pjinterrupt(int irq, void *context) +{ + return hcs12_interrupt(HCS12_PIM_PORTJ_BASE, HCS12_IRQ_PJ0, + HCS12_IRQ_PJSET, context); +} +#endif +#endif /* CONFIG_GPIO_IRQ */ + +/**************************************************************************** * Public Functions ****************************************************************************/ @@ -75,7 +222,25 @@ void hcs12_gpioirqinitialize(void) { -#warning "Not implemented" + /* Disable all GPIO IRQs -- Ports G, H, and J */ + + putreg8(0, HCS12_PIM_PORTG_IE); + putreg8(0, HCS12_PIM_PORTH_IE); + putreg8(0, HCS12_PIM_PORTJ_IE); + + /* Attach GPIO IRQ interrupt handlers */ + +#ifdef CONFIG_GPIO_IRQ +# ifdef CONFIG_HCS12_PORTG_INTS + irq_attach(HCS12_IRQ_VPORTG, hcs12_pginterrupt); +# endif +# ifdef CONFIG_HCS12_PORTH_INTS + irq_attach(HCS12_IRQ_VPORTH, hcs12_phinterrupt); +# endif +# ifdef CONFIG_HCS12_PORTJ_INTS + irq_attach(HCS12_IRQ_VPORTJ, hcs12_pjinterrupt); +# endif +#endif /* CONFIG_GPIO_IRQ */ } /**************************************************************************** @@ -86,10 +251,22 @@ void hcs12_gpioirqinitialize(void) * ****************************************************************************/ +#ifdef CONFIG_GPIO_IRQ void hcs12_gpioirqenable(int irq) { -#warning "Not implemented" + uint16_t regaddr; + uint8_t pin; + + if (hcs12_mapirq(irq, ®addr, &pin) == OK) + { + irqstate_t flags = irqsave(); + uint8_t regval = getreg8(regaddr); + regval |= (1 << pin); + putreg8(regval, regaddr); + irqrestore(flags); + } } +#endif /* CONFIG_GPIO_IRQ */ /**************************************************************************** * Name: hcs12_gpioirqdisable @@ -99,10 +276,20 @@ void hcs12_gpioirqenable(int irq) * ****************************************************************************/ +#ifdef CONFIG_GPIO_IRQ void hcs12_gpioirqdisable(int irq) { -#warning "Not implemented" -} + uint16_t regaddr; + uint8_t pin; + if (hcs12_mapirq(irq, ®addr, &pin) == OK) + { + irqstate_t flags = irqsave(); + uint8_t regval = getreg8(regaddr); + regval &= ~(1 << pin); + putreg8(regval, regaddr); + irqrestore(flags); + } +} #endif /* CONFIG_GPIO_IRQ */ diff --git a/nuttx/arch/hc/src/m9s12/m9s12_internal.h b/nuttx/arch/hc/src/m9s12/m9s12_internal.h index 643627f30..e4aa1e36d 100755 --- a/nuttx/arch/hc/src/m9s12/m9s12_internal.h +++ b/nuttx/arch/hc/src/m9s12/m9s12_internal.h @@ -59,17 +59,18 @@ * * The GPIO configuration is represented by a 16-bit value encoded as follows: * - * xxII OUUR DMGG GPPP - * || |||| ||| `-Pin number - * || |||| || `- Port number - * || |||| | `- PIM Ports - * || |||| `- Direction - * || |||`- Reduced drive - * || ||`- Polarity - * || |`- Pull up (or down) - * || `- Wired OR open drain - * |`- Interrupt or rising/falling (polarity) - * `- Interrupt + * xIIO UURV DMGG GPPP + * ||| |||| ||| `-Pin number + * ||| |||| || `- Port number + * ||| |||| | `- PIM Ports + * ||| |||| `- Direction + * ||| |||`- Initial value of output + * ||| ||`- Reduced drive + * ||| |`- Polarity + * ||| `- Pull up (or down) + * ||`- Wired OR open drain + * |`- Interrupt or rising/falling (polarity) + * `- Interrupt * * NOTE: MEBI ports E and K can have special configurations as controlled by * the PEAR and MODE registers. Those special configurations are not managed @@ -79,7 +80,7 @@ /* Interrupts: * - * xxII xxxx xxxx xxxx + * xIIx xxxx xxxx xxxx * * For PIM ports G, H, and J. NOTE: If pull up/down is also selected, then * it must be consistent with the selected interrupt edge (because both are @@ -92,7 +93,7 @@ * GPIO_INPUT and an error if GPIO_OUTPUT is also specified) */ -#define GPIO_INT_SHIFT (12) +#define GPIO_INT_SHIFT (13) #define GPIO_INT_MASK (3 << GPIO_PULLUP_SHIFT) # define GPIO_INT_POLARITY (1 << GPIO_PULLUP_SHIFT) # define GPIO_INT_ENABLE (2 << GPIO_PULLUP_SHIFT) @@ -101,22 +102,22 @@ /* Wired OR open-drain: * - * xxxx Oxxx xxxx xxxx + * xxxO xxxx xxxx xxxx * * Only PIM ports S and L */ -#define GPIO_OPENDRAN (1 << 11) +#define GPIO_OPENDRAIN (1 << 12) /* Pull up (or down): * - * xxxx xUUx xxxx xxxx + * xxxx UUxx xxxx xxxx * * For PIM ports (T,S,G,H,J,L), selection is per-pin * For MEBI ports (A,B,E,K), selection is per-port, polarity is ignored */ -#define GPIO_PULLUP_SHIFT (9) +#define GPIO_PULLUP_SHIFT (10) #define GPIO_PULLUP_MASK (3 << GPIO_PULLUP_SHIFT) # define GPIO_PULL_POLARITY (1 << GPIO_PULLUP_SHIFT) # define GPIO_PULL_ENABLE (2 << GPIO_PULLUP_SHIFT) @@ -125,13 +126,25 @@ /* Reduced drive: * - * xxxx xxxR xxxx xxxx + * xxxx xxRx xxxx xxxx * * For PIM ports (T,S,G,H,J,L), selection is per-pin * For MEBI ports (A,B,E,K), selection is per-port */ -#define GPIO_REDUCED (1 << 8) +#define GPIO_REDUCED (1 << 9) + +/* Initial value of output: + * + * xxxx xxxV xxxx xxxx + * + * For PIM ports (T,S,G,H,J,L), selection is per-pin + * For MEBI ports (A,B,E,K), selection is per-port + */ + +#define GPIO_OUTPUT_VALUE (1 << 8) +#define GPIO_OUTPUT_LOW (0) +#define GPIO_OUTPUT_HIGH GPIO_OUTPUT_VALUE /* Data direction (All ports -- A,B,E,K,T,S,G,H,J,L) * @@ -212,11 +225,7 @@ extern "C" { * ************************************************************************************/ -#ifdef CONFIG_GPIO_IRQ EXTERN void hcs12_gpioirqinitialize(void); -#else -# define hcs12_gpioirqinitialize() -#endif /************************************************************************************ * Name: hcs12_configgpio diff --git a/nuttx/arch/hc/src/m9s12/m9s12_irq.c b/nuttx/arch/hc/src/m9s12/m9s12_irq.c index 076ef0b3c..1e95c4e68 100755 --- a/nuttx/arch/hc/src/m9s12/m9s12_irq.c +++ b/nuttx/arch/hc/src/m9s12/m9s12_irq.c @@ -89,7 +89,7 @@ void up_irqinitialize(void) */ #ifdef CONFIG_GPIO_IRQ - lpc17_gpioirqinitialize(); + hcs12_gpioirqinitialize(); #endif /* And finally, enable interrupts */ |