diff options
| author | Gregory Nutt <gnutt@nuttx.org> | 2014-10-25 10:34:07 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-10-25 10:34:07 -0600 |
| commit | 01ac095544a9cf9cfa3a33225b9d5eb103c5d052 (patch) | |
| tree | 8b9b85241779a86e8c4af2f1b89c4e042e23f211 /nuttx/arch | |
| parent | abde10c13e5bb93d0f40b96f8d9e87a2021bd1db (diff) | |
| download | px4-nuttx-01ac095544a9cf9cfa3a33225b9d5eb103c5d052.tar.gz px4-nuttx-01ac095544a9cf9cfa3a33225b9d5eb103c5d052.tar.bz2 px4-nuttx-01ac095544a9cf9cfa3a33225b9d5eb103c5d052.zip | |
EFM32: A little more DMA logic. Still incomplete
Diffstat (limited to 'nuttx/arch')
| -rw-r--r-- | nuttx/arch/arm/src/efm32/chip/efm32_dma.h | 533 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/efm32/efm32_dma.c | 303 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/efm32/efm32_dma.h | 71 |
3 files changed, 676 insertions, 231 deletions
diff --git a/nuttx/arch/arm/src/efm32/chip/efm32_dma.h b/nuttx/arch/arm/src/efm32/chip/efm32_dma.h index 5dce46f12..38db920b8 100644 --- a/nuttx/arch/arm/src/efm32/chip/efm32_dma.h +++ b/nuttx/arch/arm/src/efm32/chip/efm32_dma.h @@ -1768,166 +1768,299 @@ #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /* Shift value for DMA_SIGSEL */ #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /* Bit mask for DMA_SIGSEL */ -#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /* Mode ADC0SINGLE for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /* Mode DAC0CH0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /* Mode USART0RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /* Mode USART1RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /* Mode USART2RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /* Mode LEUART0RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /* Mode LEUART1RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /* Mode I2C0RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /* Mode I2C1RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /* Mode TIMER0UFOF for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /* Mode TIMER1UFOF for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /* Mode TIMER2UFOF for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /* Mode TIMER3UFOF for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL /* Mode UART0RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000000UL /* Mode UART1RXDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /* Mode MSCWDATA for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /* Mode AESDATAWR for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /* Mode LESENSEBUFDATAV for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /* Mode EBIPXL0EMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /* Mode ADC0SCAN for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /* Mode DAC0CH1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /* Mode USART0TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /* Mode USART1TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /* Mode USART2TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /* Mode LEUART0TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /* Mode LEUART1TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /* Mode I2C0TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /* Mode I2C1TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /* Mode TIMER0CC0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /* Mode TIMER1CC0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /* Mode TIMER2CC0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /* Mode TIMER3CC0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL /* Mode UART0TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_UART1TXBL 0x00000001UL /* Mode UART1TXBL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /* Mode AESXORDATAWR for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /* Mode EBIPXL1EMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /* Mode USART0TXEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /* Mode USART1TXEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /* Mode USART2TXEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /* Mode LEUART0TXEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /* Mode LEUART1TXEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /* Mode TIMER0CC1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /* Mode TIMER1CC1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /* Mode TIMER2CC1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /* Mode TIMER3CC1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL /* Mode UART0TXEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 0x00000002UL /* Mode UART1TXEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /* Mode AESDATARD for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_EBIPXLFULL 0x00000002UL /* Mode EBIPXLFULL for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /* Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /* Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /* Mode TIMER0CC2 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /* Mode TIMER1CC2 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /* Mode TIMER2CC2 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /* Mode TIMER3CC2 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /* Mode AESKEYWR for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_EBIDDEMPTY 0x00000003UL /* Mode EBIDDEMPTY for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /* Mode USART1TXBLRIGHT for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /* Mode USART2TXBLRIGHT for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /* Shifted mode ADC0SINGLE for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /* Shifted mode DAC0CH0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /* Shifted mode USART0RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /* Shifted mode USART1RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /* Shifted mode USART2RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /* Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /* Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /* Shifted mode I2C0RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /* Shifted mode I2C1RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /* Shifted mode TIMER0UFOF for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /* Shifted mode TIMER1UFOF for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /* Shifted mode TIMER2UFOF for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /* Shifted mode TIMER3UFOF for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /* Shifted mode UART0RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_UART1RXDATAV (_DMA_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /* Shifted mode UART1RXDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /* Shifted mode MSCWDATA for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /* Shifted mode AESDATAWR for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /* Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY << 0) /* Shifted mode EBIPXL0EMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /* Shifted mode ADC0SCAN for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /* Shifted mode DAC0CH1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /* Shifted mode USART0TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /* Shifted mode USART1TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /* Shifted mode USART2TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /* Shifted mode LEUART0TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /* Shifted mode LEUART1TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /* Shifted mode I2C0TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /* Shifted mode I2C1TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /* Shifted mode TIMER0CC0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /* Shifted mode TIMER1CC0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /* Shifted mode TIMER2CC0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /* Shifted mode TIMER3CC0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_UART0TXBL (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0) /* Shifted mode UART0TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_UART1TXBL (_DMA_CH_CTRL_SIGSEL_UART1TXBL << 0) /* Shifted mode UART1TXBL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /* Shifted mode AESXORDATAWR for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY << 0) /* Shifted mode EBIPXL1EMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /* Shifted mode USART0TXEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /* Shifted mode USART1TXEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /* Shifted mode USART2TXEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /* Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /* Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /* Shifted mode TIMER0CC1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /* Shifted mode TIMER1CC1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /* Shifted mode TIMER2CC1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /* Shifted mode TIMER3CC1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0) /* Shifted mode UART0TXEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY << 0) /* Shifted mode UART1TXEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /* Shifted mode AESDATARD for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_EBIPXLFULL (_DMA_CH_CTRL_SIGSEL_EBIPXLFULL << 0) /* Shifted mode EBIPXLFULL for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /* Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /* Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /* Shifted mode TIMER0CC2 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /* Shifted mode TIMER1CC2 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /* Shifted mode TIMER2CC2 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /* Shifted mode TIMER3CC2 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /* Shifted mode AESKEYWR for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY (_DMA_CH_CTRL_SIGSEL_EBIDDEMPTY << 0) /* Shifted mode EBIDDEMPTY for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /* Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /* Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */ + +#if defined(CONFIG_EFM32_EFM32GG) + +# define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /* Mode ADC0SINGLE for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /* Mode DAC0CH0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /* Mode USART0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /* Mode USART1RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /* Mode USART2RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /* Mode LEUART0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /* Mode LEUART1RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /* Mode I2C0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /* Mode I2C1RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /* Mode TIMER0UFOF for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /* Mode TIMER1UFOF for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /* Mode TIMER2UFOF for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /* Mode TIMER3UFOF for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL /* Mode UART0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000000UL /* Mode UART1RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /* Mode MSCWDATA for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /* Mode AESDATAWR for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /* Mode LESENSEBUFDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /* Mode EBIPXL0EMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /* Mode ADC0SCAN for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /* Mode DAC0CH1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /* Mode USART0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /* Mode USART1TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /* Mode USART2TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /* Mode LEUART0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /* Mode LEUART1TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /* Mode I2C0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /* Mode I2C1TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /* Mode TIMER0CC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /* Mode TIMER1CC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /* Mode TIMER2CC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /* Mode TIMER3CC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL /* Mode UART0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART1TXBL 0x00000001UL /* Mode UART1TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /* Mode AESXORDATAWR for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /* Mode EBIPXL1EMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /* Mode USART0TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /* Mode USART1TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /* Mode USART2TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /* Mode LEUART0TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /* Mode LEUART1TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /* Mode TIMER0CC1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /* Mode TIMER1CC1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /* Mode TIMER2CC1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /* Mode TIMER3CC1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL /* Mode UART0TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 0x00000002UL /* Mode UART1TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /* Mode AESDATARD for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_EBIPXLFULL 0x00000002UL /* Mode EBIPXLFULL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /* Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /* Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /* Mode TIMER0CC2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /* Mode TIMER1CC2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /* Mode TIMER2CC2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /* Mode TIMER3CC2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /* Mode AESKEYWR for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_EBIDDEMPTY 0x00000003UL /* Mode EBIDDEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /* Mode USART1TXBLRIGHT for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /* Mode USART2TXBLRIGHT for DMA_CH_CTRL */ + +# define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /* Shifted mode ADC0SINGLE for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /* Shifted mode DAC0CH0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /* Shifted mode USART0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /* Shifted mode USART1RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /* Shifted mode USART2RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /* Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /* Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /* Shifted mode I2C0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /* Shifted mode I2C1RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /* Shifted mode TIMER0UFOF for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /* Shifted mode TIMER1UFOF for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /* Shifted mode TIMER2UFOF for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /* Shifted mode TIMER3UFOF for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /* Shifted mode UART0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART1RXDATAV (_DMA_CH_CTRL_SIGSEL_UART1RXDATAV << 0) /* Shifted mode UART1RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /* Shifted mode MSCWDATA for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /* Shifted mode AESDATAWR for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /* Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY << 0) /* Shifted mode EBIPXL0EMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /* Shifted mode ADC0SCAN for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /* Shifted mode DAC0CH1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /* Shifted mode USART0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /* Shifted mode USART1TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /* Shifted mode USART2TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /* Shifted mode LEUART0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /* Shifted mode LEUART1TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /* Shifted mode I2C0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /* Shifted mode I2C1TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /* Shifted mode TIMER0CC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /* Shifted mode TIMER1CC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /* Shifted mode TIMER2CC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /* Shifted mode TIMER3CC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART0TXBL (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0) /* Shifted mode UART0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART1TXBL (_DMA_CH_CTRL_SIGSEL_UART1TXBL << 0) /* Shifted mode UART1TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /* Shifted mode AESXORDATAWR for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY << 0) /* Shifted mode EBIPXL1EMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /* Shifted mode USART0TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /* Shifted mode USART1TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /* Shifted mode USART2TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /* Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /* Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /* Shifted mode TIMER0CC1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /* Shifted mode TIMER1CC1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /* Shifted mode TIMER2CC1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /* Shifted mode TIMER3CC1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0) /* Shifted mode UART0TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY << 0) /* Shifted mode UART1TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /* Shifted mode AESDATARD for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_EBIPXLFULL (_DMA_CH_CTRL_SIGSEL_EBIPXLFULL << 0) /* Shifted mode EBIPXLFULL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /* Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /* Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /* Shifted mode TIMER0CC2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /* Shifted mode TIMER1CC2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /* Shifted mode TIMER2CC2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /* Shifted mode TIMER3CC2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /* Shifted mode AESKEYWR for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY (_DMA_CH_CTRL_SIGSEL_EBIDDEMPTY << 0) /* Shifted mode EBIDDEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /* Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /* Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */ + +#elif defined(CONFIG_EFM32_EFM32G) + +# define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /* Mode ADC0SINGLE for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /* Mode DAC0CH0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /* Mode USART0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /* Mode USART1RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /* Mode USART2RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /* Mode LEUART0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /* Mode LEUART1RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /* Mode I2C0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /* Mode TIMER0UFOF for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /* Mode TIMER1UFOF for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /* Mode TIMER2UFOF for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL /* Mode UART0RXDATAV for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /* Mode MSCWDATA for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /* Mode AESDATAWR for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /* Mode ADC0SCAN for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /* Mode DAC0CH1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /* Mode USART0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /* Mode USART1TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /* Mode USART2TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /* Mode LEUART0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /* Mode LEUART1TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /* Mode I2C0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /* Mode TIMER0CC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /* Mode TIMER1CC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /* Mode TIMER2CC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL /* Mode UART0TXBL for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /* Mode AESXORDATAWR for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /* Mode USART0TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /* Mode USART1TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /* Mode USART2TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /* Mode LEUART0TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /* Mode LEUART1TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /* Mode TIMER0CC1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /* Mode TIMER1CC1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /* Mode TIMER2CC1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL /* Mode UART0TXEMPTY for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /* Mode AESDATARD for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /* Mode TIMER0CC2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /* Mode TIMER1CC2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /* Mode TIMER2CC2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /* Mode AESKEYWR for DMA_CH_CTRL */ + +# define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (0x00000000UL << 0) /* Shifted mode ADC0SINGLE for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_DAC0CH0 (0x00000000UL << 0) /* Shifted mode DAC0CH0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (0x00000000UL << 0) /* Shifted mode USART0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (0x00000000UL << 0) /* Shifted mode USART1RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (0x00000000UL << 0) /* Shifted mode USART2RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (0x00000000UL << 0) /* Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (0x00000000UL << 0) /* Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (0x00000000UL << 0) /* Shifted mode I2C0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (0x00000000UL << 0) /* Shifted mode TIMER0UFOF for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (0x00000000UL << 0) /* Shifted mode TIMER1UFOF for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (0x00000000UL << 0) /* Shifted mode TIMER2UFOF for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (0x00000000UL << 0) /* Shifted mode UART0RXDATAV for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_MSCWDATA (0x00000000UL << 0) /* Shifted mode MSCWDATA for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESDATAWR (0x00000000UL << 0) /* Shifted mode AESDATAWR for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_ADC0SCAN (0x00000001UL << 0) /* Shifted mode ADC0SCAN for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_DAC0CH1 (0x00000001UL << 0) /* Shifted mode DAC0CH1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART0TXBL (0x00000001UL << 0) /* Shifted mode USART0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1TXBL (0x00000001UL << 0) /* Shifted mode USART1TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2TXBL (0x00000001UL << 0) /* Shifted mode USART2TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (0x00000001UL << 0) /* Shifted mode LEUART0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (0x00000001UL << 0) /* Shifted mode LEUART1TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_I2C0TXBL (0x00000001UL << 0) /* Shifted mode I2C0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000001UL << 0) /* Shifted mode TIMER0CC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000001UL << 0) /* Shifted mode TIMER1CC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000001UL << 0) /* Shifted mode TIMER2CC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART0TXBL (0x00000001UL << 0) /* Shifted mode UART0TXBL for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (0x00000001UL << 0) /* Shifted mode AESXORDATAWR for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (0x00000002UL << 0) /* Shifted mode USART0TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (0x00000002UL << 0) /* Shifted mode USART1TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (0x00000002UL << 0) /* Shifted mode USART2TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (0x00000002UL << 0) /* Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (0x00000002UL << 0) /* Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000002UL << 0) /* Shifted mode TIMER0CC1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000002UL << 0) /* Shifted mode TIMER1CC1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000002UL << 0) /* Shifted mode TIMER2CC1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (0x00000002UL << 0) /* Shifted mode UART0TXEMPTY for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESDATARD (0x00000002UL << 0) /* Shifted mode AESDATARD for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000003UL << 0) /* Shifted mode TIMER0CC2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000003UL << 0) /* Shifted mode TIMER1CC2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000003UL << 0) /* Shifted mode TIMER2CC2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SIGSEL_AESKEYWR (0x00000003UL << 0) /* Shifted mode AESKEYWR for DMA_CH_CTRL */ + +#endif + #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /* Shift value for DMA_SOURCESEL */ #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /* Bit mask for DMA_SOURCESEL */ -#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /* Mode NONE for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /* Mode ADC0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /* Mode DAC0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /* Mode USART0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /* Mode USART1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /* Mode USART2 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /* Mode LEUART0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /* Mode LEUART1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /* Mode I2C0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /* Mode I2C1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /* Mode TIMER0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /* Mode TIMER1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /* Mode TIMER2 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /* Mode TIMER3 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL /* Mode UART0 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_UART1 0x0000002DUL /* Mode UART1 for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /* Mode MSC for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /* Mode AES for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /* Mode LESENSE for DMA_CH_CTRL */ -#define _DMA_CH_CTRL_SOURCESEL_EBI 0x00000033UL /* Mode EBI for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /* Shifted mode NONE for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /* Shifted mode ADC0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /* Shifted mode DAC0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /* Shifted mode USART0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /* Shifted mode USART1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /* Shifted mode USART2 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /* Shifted mode LEUART0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /* Shifted mode LEUART1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /* Shifted mode I2C0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /* Shifted mode I2C1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /* Shifted mode TIMER0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /* Shifted mode TIMER1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /* Shifted mode TIMER2 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /* Shifted mode TIMER3 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_UART0 (_DMA_CH_CTRL_SOURCESEL_UART0 << 16) /* Shifted mode UART0 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_UART1 (_DMA_CH_CTRL_SOURCESEL_UART1 << 16) /* Shifted mode UART1 for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /* Shifted mode MSC for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /* Shifted mode AES for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /* Shifted mode LESENSE for DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16) /* Shifted mode EBI for DMA_CH_CTRL */ + +#if defined(CONFIG_EFM32_EFM32GG) + +# define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /* Mode NONE for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /* Mode ADC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /* Mode DAC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /* Mode USART0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /* Mode USART1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /* Mode USART2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /* Mode LEUART0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /* Mode LEUART1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /* Mode I2C0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /* Mode I2C1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /* Mode TIMER0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /* Mode TIMER1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /* Mode TIMER2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /* Mode TIMER3 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL /* Mode UART0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_UART1 0x0000002DUL /* Mode UART1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /* Mode MSC for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /* Mode AES for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /* Mode LESENSE for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_EBI 0x00000033UL /* Mode EBI for DMA_CH_CTRL */ + +# define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /* Shifted mode NONE for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /* Shifted mode ADC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /* Shifted mode DAC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /* Shifted mode USART0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /* Shifted mode USART1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /* Shifted mode USART2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /* Shifted mode LEUART0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /* Shifted mode LEUART1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /* Shifted mode I2C0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /* Shifted mode I2C1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /* Shifted mode TIMER0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /* Shifted mode TIMER1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /* Shifted mode TIMER2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /* Shifted mode TIMER3 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_UART0 (_DMA_CH_CTRL_SOURCESEL_UART0 << 16) /* Shifted mode UART0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_UART1 (_DMA_CH_CTRL_SOURCESEL_UART1 << 16) /* Shifted mode UART1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /* Shifted mode MSC for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /* Shifted mode AES for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /* Shifted mode LESENSE for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16) /* Shifted mode EBI for DMA_CH_CTRL */ + +#elif defined(CONFIG_EFM32_EFM32G) + +# define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /* Mode NONE for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /* Mode ADC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /* Mode DAC0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /* Mode USART0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /* Mode USART1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /* Mode USART2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /* Mode LEUART0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /* Mode LEUART1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /* Mode I2C0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /* Mode TIMER0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /* Mode TIMER1 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /* Mode TIMER2 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL /* Mode UART0 for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /* Mode MSC for DMA_CH_CTRL */ +# define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /* Mode AES for DMA_CH_CTRL */ + +# define DMA_CH_CTRL_SOURCESEL_NONE (0x00000000UL << 16) /* Shifted mode NONE for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_ADC0 (0x00000008UL << 16) /* Shifted mode ADC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_DAC0 (0x0000000AUL << 16) /* Shifted mode DAC0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_USART0 (0x0000000CUL << 16) /* Shifted mode USART0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_USART1 (0x0000000DUL << 16) /* Shifted mode USART1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_USART2 (0x0000000EUL << 16) /* Shifted mode USART2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_LEUART0 (0x00000010UL << 16) /* Shifted mode LEUART0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_LEUART1 (0x00000011UL << 16) /* Shifted mode LEUART1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_I2C0 (0x00000014UL << 16) /* Shifted mode I2C0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_TIMER0 (0x00000018UL << 16) /* Shifted mode TIMER0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_TIMER1 (0x00000019UL << 16) /* Shifted mode TIMER1 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_TIMER2 (0x0000001AUL << 16) /* Shifted mode TIMER2 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_UART0 (0x0000002CUL << 16) /* Shifted mode UART0 for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_MSC (0x00000030UL << 16) /* Shifted mode MSC for DMA_CH_CTRL */ +# define DMA_CH_CTRL_SOURCESEL_AES (0x00000031UL << 16) /* Shifted mode AES for DMA_CH_CTRL */ + +#endif /* DMA Descriptor Bit Field Definitions ****************************************************************************************/ @@ -2091,54 +2224,54 @@ # define DMAREQ_EBI_PXLFULL ((51 << 16) + 2) /* DMA channel select for EBI_PXLFULL */ # define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /* DMA channel select for EBI_DDEMPTY */ #elif defined(CONFIG_EFM32_EFM32G) -# define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */ -# define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */ -# define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */ -# define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */ -# define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */ -# define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */ -# define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */ -# define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */ -# define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */ -# define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */ -# define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */ -# define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */ -# define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */ -# define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */ -# define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */ -# define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */ -# define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */ -# define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */ -# define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */ -# define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */ -# define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */ -# define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */ -# define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */ -# define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */ -# define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */ -# define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */ -# define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */ -# define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */ -# define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */ -# define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */ -# define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */ -# define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */ -# define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */ -# define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */ -# define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */ -# define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */ -# define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */ -# define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */ -# define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */ -# define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */ -# define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */ +# define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /* DMA channel select for ADC0_SINGLE */ +# define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /* DMA channel select for ADC0_SCAN */ +# define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /* DMA channel select for DAC0_CH0 */ +# define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /* DMA channel select for DAC0_CH1 */ +# define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /* DMA channel select for USART0_RXDATAV */ +# define DMAREQ_USART0_TXBL ((12 << 16) + 1) /* DMA channel select for USART0_TXBL */ +# define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /* DMA channel select for USART0_TXEMPTY */ +# define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /* DMA channel select for USART1_RXDATAV */ +# define DMAREQ_USART1_TXBL ((13 << 16) + 1) /* DMA channel select for USART1_TXBL */ +# define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /* DMA channel select for USART1_TXEMPTY */ +# define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /* DMA channel select for USART2_RXDATAV */ +# define DMAREQ_USART2_TXBL ((14 << 16) + 1) /* DMA channel select for USART2_TXBL */ +# define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /* DMA channel select for USART2_TXEMPTY */ +# define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /* DMA channel select for LEUART0_RXDATAV */ +# define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /* DMA channel select for LEUART0_TXBL */ +# define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /* DMA channel select for LEUART0_TXEMPTY */ +# define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /* DMA channel select for LEUART1_RXDATAV */ +# define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /* DMA channel select for LEUART1_TXBL */ +# define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /* DMA channel select for LEUART1_TXEMPTY */ +# define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /* DMA channel select for I2C0_RXDATAV */ +# define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /* DMA channel select for I2C0_TXBL */ +# define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /* DMA channel select for TIMER0_UFOF */ +# define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /* DMA channel select for TIMER0_CC0 */ +# define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /* DMA channel select for TIMER0_CC1 */ +# define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /* DMA channel select for TIMER0_CC2 */ +# define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /* DMA channel select for TIMER1_UFOF */ +# define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /* DMA channel select for TIMER1_CC0 */ +# define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /* DMA channel select for TIMER1_CC1 */ +# define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /* DMA channel select for TIMER1_CC2 */ +# define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /* DMA channel select for TIMER2_UFOF */ +# define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /* DMA channel select for TIMER2_CC0 */ +# define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /* DMA channel select for TIMER2_CC1 */ +# define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /* DMA channel select for TIMER2_CC2 */ +# define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /* DMA channel select for UART0_RXDATAV */ +# define DMAREQ_UART0_TXBL ((44 << 16) + 1) /* DMA channel select for UART0_TXBL */ +# define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /* DMA channel select for UART0_TXEMPTY */ +# define DMAREQ_MSC_WDATA ((48 << 16) + 0) /* DMA channel select for MSC_WDATA */ +# define DMAREQ_AES_DATAWR ((49 << 16) + 0) /* DMA channel select for AES_DATAWR */ +# define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /* DMA channel select for AES_XORDATAWR */ +# define DMAREQ_AES_DATARD ((49 << 16) + 2) /* DMA channel select for AES_DATARD */ +# define DMAREQ_AES_KEYWR ((49 << 16) + 3) /* DMA channel select for AES_KEYWR */ #endif /******************************************************************************************************************************* * Public Types *******************************************************************************************************************************/ -struct dma_desriptor_s +struct dma_descriptor_s { volatile void * volatile srcend; /* DMA source address end */ volatile void * volatile dstend; /* DMA destination address end */ diff --git a/nuttx/arch/arm/src/efm32/efm32_dma.c b/nuttx/arch/arm/src/efm32/efm32_dma.c index 0b6263bf1..9b91efcee 100644 --- a/nuttx/arch/arm/src/efm32/efm32_dma.c +++ b/nuttx/arch/arm/src/efm32/efm32_dma.c @@ -49,9 +49,19 @@ #include <nuttx/arch.h> +#include "up_arch.h" +#include "chip/efm32_dma.h" #include "efm32_dma.h" /***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +#define ALIGN_MASK(s) ((1 << s) - 1) +#define ALIGN_DOWN(v,m) ((v) & ~m) +#define ALIGN_UP(v,m) (((v) + (m)) & ~m) + +/***************************************************************************** * Public Types *****************************************************************************/ /* This union allows us to keep free DMA descriptors in in a list */ @@ -59,28 +69,29 @@ union dma_descriptor_u { sq_entry_t link; - struct dma_desriptor_s desc; + struct dma_descriptor_s desc; }; /* This structure describes one DMA channel */ struct dma_channel_s { - uint8_t chan; /* DMA channel number (0-EFM_DMA_NCHANNELS) */ - bool inuse; /* TRUE: The DMA channel is in use */ - struct dms_descriptor_s *desc; /* DMA descriptor assigned to the channel */ - dma_callback_t callback; /* Callback invoked when the DMA completes */ - void *arg; /* Argument passed to callback function */ + uint8_t chan; /* DMA channel number (0-EFM_DMA_NCHANNELS) */ + bool inuse; /* TRUE: The DMA channel is in use */ + struct dma_descriptor_s *desc; /* DMA descriptor assigned to the channel */ + dma_config_t config; /* Current configuration */ + dma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ }; /* This structure describes the state of the DMA controller */ struct dma_controller_s { - sem_t exclsem; /* Protects channel table */ - sem_t chansem; /* Count of free channels */ - sem_t freesem; /* Count of free descriptors */ - sq_queue_t freedesc; /* List of free DMA descriptors */ + sem_t exclsem; /* Protects channel table */ + sem_t chansem; /* Count of free channels */ + sem_t freesem; /* Count of free descriptors */ + sq_queue_t freedesc; /* List of free DMA descriptors */ }; /***************************************************************************** @@ -187,6 +198,46 @@ static void efm32_free_descriptor(struct dma_descriptor_s *desc) } /**************************************************************************** + * Name: efm32_set_chctrl + * + * Description: + * Set the channel control register + * + ****************************************************************************/ + +static void efm32_set_chctrl(struct dma_channel_s *dmach, dma_config_t config) +{ + uintptr_t regaddr; + uint32_t decoded; + uint32_t regval; + + decoded = (uint32_t)(config & EFM32_DMA_SIGSEL_MASK) >> EFM32_DMA_SIGSEL_SHIFT; + regval = (decoded << _DMA_CH_CTRL_SIGSEL_SHIFT); + decoded = (uint32_t)(config & EFM32_DMA_SOURCSEL_MASK) >> EFM32_DMA_SOURCSEL_SHIFT; + regval |= (decoded << _DMA_CH_CTRL_SOURCESEL_SHIFT); + + regaddr = EFM_DMA_CHn_CTRL(dmach->chan); + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: efm32_align_shift + * + * Description: + * Set the channel control register + * + ****************************************************************************/ + +static inline unsigned int efm32_align_shift(dma_config_t config) +{ + unsigned int shift; + + shift = (config & EFM32_DMA_XFERSIZE_MASK) >> EFM32_DMA_XFERSIZE_SHIFT; + DEBUGASSERT(shift != 3); + return shift; +} + +/**************************************************************************** * Name: efm32_dmac_interrupt * * Description: @@ -248,8 +299,9 @@ void weak_function up_dmainitialize(void) (void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt); - /* Initialize the controller */ -#warning Missing logic + /* Enale the DMA controller */ + + putreg32(DMA_CONFIG_EN, EFM_DMA_CONFIG); /* Enable the IRQ at the AIC (still disabled at the DMA controller) */ @@ -313,14 +365,15 @@ DMA_HANDLE efm32_dmachannel(void) struct dma_channel_s *candidate = &g_dmach[chndx]; if (!candidate->inuse) { - dmach = candidate; - dmach->inuse = true; + dmach = candidate; + dmach->inuse = true; /* Clear any pending channel interrupts */ #warning Missing logic /* Disable the channel */ -#warning Missing logic + + putreg32(1 << dmach->chan, EFM_DMA_CHENC); break; } } @@ -368,9 +421,10 @@ void efm32_dmafree(DMA_HANDLE handle) dmavdbg("DMA channel %d\n", dmach->chan); /* Disable the channel */ -#warning Missing logic - /* Mark the channel no longer in use. Clearing the inuse flag is an atomic + putreg32(1 << dmach->chan, EFM_DMA_CHENC); + + /* Mark the channel no longer in use. Clearing the in-use flag is an atomic * operation and so should be safe. */ @@ -384,17 +438,175 @@ void efm32_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: efm32_dmasetup + * Name: efm32_rxdmasetup * * Description: - * Configure DMA before using + * Configure an RX (peripheral-to-memory) DMA before starting the transfer. + * + * Input Parameters: + * paddr - Peripheral address (source) + * maddr - Memory address (destination) + * nbytes - Number of bytes to transfer. Must be an even multiple of the + * configured transfer size. + * config - Channel configuration selections * ****************************************************************************/ -void efm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr) +void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, + size_t nbytes, dma_config_t config) { -#warning Missing logic + struct dma_channel_s *dmach = (struct dma_channel_s *)handle; + struct dma_descriptor_s *desc; + unsigned int xfersize; + unsigned int shift; + uint32_t regval; + uint32_t mask; + + DEBUGASSERT(dmach != NULL && dmach->inuse); + + /* Get the properly alignment shift and mask */ + + shift = efm32_align_shift(config); + mask = ALIGN_MASK(shift); + + /* Make sure that the number of bytes we are asked to transfer is a multiple + * of the transfer size. + */ + + xfersize = (1 << shift); + nbytes = ALIGN_DOWN(nbytes, mask); + DEBUGASSERT(nbytes > 0); + + /* Allocate a DMA descriptor for the channel. We may block here. */ + + desc = efm32_alloc_descriptor(); + dmach->desc = desc; + dmach->config = config; + + /* Configure for the selected peripheral */ + + efm32_set_chctrl(dmach, config); + + /* Configure the primary channel descriptor */ + + desc->srcend = (uint32_t *)paddr; + desc->dstend = (uint32_t *)(maddr + nbytes - xfersize); + + /* No source increment, destination increments according to transfer size. + * No privileges. Arbitrate after each transfer. + */ + + regval = DMA_CTRL_SRC_INC_NONE | DMA_CTRL_DST_PROT_NON_PRIVILEGED | + DMA_CTRL_SRC_PROT_NON_PRIVILEGED | DMA_CTRL_R_POWER_1 | + (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT) | _DMA_CTRL_CYCLE_CTRL_BASIC; + + switch (shift) + { + default: + case 0: /* Byte transfer */ + regval = DMA_CTRL_DST_INC_BYTE | DMA_CTRL_DST_SIZE_BYTE | DMA_CTRL_SRC_SIZE_BYTE; + break; + + case 1: /* Half word transfer */ + regval = DMA_CTRL_DST_INC_HALFWORD | DMA_CTRL_DST_SIZE_HALFWORD | DMA_CTRL_SRC_SIZE_HALFWORD; + break; + + case 2: /* Word transfer */ + regval = DMA_CTRL_DST_INC_WORD | DMA_CTRL_DST_SIZE_WORD | DMA_CTRL_SRC_SIZE_WORD; + break; + } + + /* Set the number of transfers (minus 1) */ + + regval |= ((nbytes >> shift) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT; + desc->ctrl = regval; + desc->user = 0; +} + +/**************************************************************************** + * Name: efm32_txdmasetup + * + * Description: + * Configure an TX (memory-to-memory) DMA before starting the transfer. + * + * Input Parameters: + * paddr - Peripheral address (destination) + * maddr - Memory address (source) + * nbytes - Number of bytes to transfer. Must be an even multiple of the + * configured transfer size. + * config - Channel configuration selections + * + ****************************************************************************/ + +void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, + size_t nbytes, dma_config_t config) +{ + struct dma_channel_s *dmach = (struct dma_channel_s *)handle; + struct dma_descriptor_s *desc; + unsigned int xfersize; + unsigned int shift; + uint32_t regval; + uint32_t mask; + + DEBUGASSERT(dmach != NULL && dmach->inuse); + + /* Get the properly alignment shift and mask */ + + shift = efm32_align_shift(config); + mask = ALIGN_MASK(shift); + + /* Make sure that the number of bytes we are asked to transfer is a multiple + * of the transfer size. + */ + + xfersize = (1 << shift); + nbytes = ALIGN_DOWN(nbytes, mask); + DEBUGASSERT(nbytes > 0); + + /* Allocate a DMA descriptor for the channel. We may block here. */ + + desc = efm32_alloc_descriptor(); + dmach->desc = desc; + dmach->config = config; + + /* Configure for the selected peripheral */ + + efm32_set_chctrl(dmach, config); + + /* Configure the primary channel descriptor */ + + desc->srcend = (uint32_t *)(maddr + nbytes - xfersize); + desc->dstend = (uint32_t *)paddr; + + /* No source increment, destination increments according to transfer size. + * No privileges. Arbitrate after each transfer. + */ + + regval = DMA_CTRL_DST_INC_NONE | DMA_CTRL_DST_PROT_NON_PRIVILEGED | + DMA_CTRL_SRC_PROT_NON_PRIVILEGED | DMA_CTRL_R_POWER_1 | + (0 << _DMA_CTRL_NEXT_USEBURST_SHIFT) | _DMA_CTRL_CYCLE_CTRL_BASIC; + + switch (shift) + { + default: + case 0: /* Byte transfer */ + regval = DMA_CTRL_DST_SIZE_BYTE | DMA_CTRL_SRC_INC_BYTE | DMA_CTRL_SRC_SIZE_BYTE; + break; + + case 1: /* Half word transfer */ + regval = DMA_CTRL_DST_SIZE_HALFWORD | DMA_CTRL_SRC_INC_HALFWORD | DMA_CTRL_SRC_SIZE_HALFWORD; + break; + + case 2: /* Word transfer */ + regval = DMA_CTRL_DST_SIZE_WORD | DMA_CTRL_SRC_INC_WORD | DMA_CTRL_SRC_SIZE_WORD; + break; + } + + /* Set the number of transfers (minus 1) */ + + regval |= ((nbytes >> shift) - 1) << _DMA_CTRL_N_MINUS_1_SHIFT; + desc->ctrl = regval; + desc->user = 0; } /**************************************************************************** @@ -409,10 +621,51 @@ void efm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * ****************************************************************************/ -void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half) +void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) { -#warning Missing logic + struct dma_channel_s *dmach = (struct dma_channel_s *)handle; + uint32_t bit; + + DEBUGASSERT(dmach && dmach->inuse && dmach->desc); + + /* Save the DMA complete callback info */ + + dmach->callback = callback; + dmach->arg = arg; + + /* Finish configuring the channel */ + + bit = 1 << dmach->chan; + if ((dmach->config & EFM32_DMA_SINGLE_MASK) == EFM32_DMA_BUFFER_FULL) + { + /* Disable the single requests for the channel (i.e. do not react to data + * available, wait for buffer full) + */ + + putreg32(bit, EFM_DMA_CHUSEBURSTS); + + /* Enable buffer-full requests for the channel */ + + putreg32(bit, EFM_DMA_CHREQMASKC); + } + else + { + /* Enable the single requests for the channel */ + + putreg32(bit, EFM_DMA_CHUSEBURSTC); + + /* Disable buffer-full requests for the channel */ + + putreg32(bit, EFM_DMA_CHREQMASKS); + } + + /* Use the primary data structure for channel 0 */ + + putreg32(bit, EFM_DMA_CHALTC); + + /* Enable the channel */ + + putreg32(bit, EFM_DMA_CHENS); } /**************************************************************************** diff --git a/nuttx/arch/arm/src/efm32/efm32_dma.h b/nuttx/arch/arm/src/efm32/efm32_dma.h index 8d0262caf..6be4071c5 100644 --- a/nuttx/arch/arm/src/efm32/efm32_dma.h +++ b/nuttx/arch/arm/src/efm32/efm32_dma.h @@ -50,6 +50,37 @@ #include "chip/efm32_dma.h" /************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Bit encoded input parameter to efm32_channel() + * + * Current limitations/assumptions in the encoding: + * + * - RX transfers are peripheral to memory + * - TX transfers are memory to peripheral + * - Memory address is always incremented. + */ + +#define EFM32_DMA_SIGSEL_SHIFT (0) /* Bits 0-3: _DMA_CH_CTRL_ * value */ +#define EFM32_DMA_SIGSEL_MASK (15 << EFM32_DMA_SIGSEL_SHIFT) +# define EFM32_DMA_SIGSEL(n) ((dma_config_t)(n) << EFM32_DMA_SIGSEL_SHIFT) + +#define EFM32_DMA_SOURCSEL_SHIFT (4) /* Bits 4-9: _DMA_CH_SOURCESEL_* value */ +#define EFM32_DMA_SOURCSEL_MASK (63 << EFM32_DMA_SOURCSEL_SHIFT) +# define EFM32_DMA_SOURCSEL(n) (dma_config_t)(n) << EFM32_DMA_SOURCSEL_SHIFT) + +#define EFM32_DMA_XFERSIZE_SHIFT (10) /* Bits 10-11: Transfer size */ +#define EFM32_DMA_XFERSIZE_MASK (3 << EFM32_DMA_XFERSIZE_SHIFT) +# define EFM32_DMA_XFERSIZE_SHIFT_BYTE (0 << EFM32_DMA_SOURCSEL_SHIFT) +# define EFM32_DMA_XFERSIZE_SHIFT_HWORD (1 << EFM32_DMA_SOURCSEL_SHIFT) +# define EFM32_DMA_XFERSIZE_SHIFT_WORD (2 << EFM32_DMA_SOURCSEL_SHIFT) + +#define EFM32_DMA_SINGLE_MASK (1 << 12) /* Bit 12: Single or Buffer full request */ +# define EFM32_DMA_SINGLE (1 << 12) /* 1=Buffer full request */ +# define EFM32_DMA_BUFFER_FULL (0) /* 0=Buffer full request */ + +/************************************************************************************ * Public Types ************************************************************************************/ @@ -101,6 +132,10 @@ struct efm32_dmaregs_s }; #endif +/* Type of 'config' argument passed to efm32_rxdmasetup() and efm32_txdmasetup */ + +typedef uint32_t dma_config_t; + /************************************************************************************ * Public Data ************************************************************************************/ @@ -167,15 +202,40 @@ DMA_HANDLE efm32_dmachannel(void); void efm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: efm32_dmasetup + * Name: efm32_rxdmasetup + * + * Description: + * Configure an RX (peripheral-to-memory) DMA before starting the transfer. + * + * Input Parameters: + * paddr - Peripheral address (source) + * maddr - Memory address (destination) + * nbytes - Number of bytes to transfer. Must be an even multiple of the + * configured transfer size. + * config - Channel configuration selections + * + ****************************************************************************/ + +void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, + size_t nbytes, dma_config_t config); + +/**************************************************************************** + * Name: efm32_txdmasetup * * Description: - * Configure DMA before using + * Configure an TX (memory-to-memory) DMA before starting the transfer. + * + * Input Parameters: + * paddr - Peripheral address (destination) + * maddr - Memory address (source) + * nbytes - Number of bytes to transfer. Must be an even multiple of the + * configured transfer size. + * config - Channel configuration selections * ****************************************************************************/ -void efm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); +void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr, + size_t nbytes, dma_config_t config); /**************************************************************************** * Name: efm32_dmastart @@ -189,8 +249,7 @@ void efm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * ****************************************************************************/ -void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half); +void efm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); /**************************************************************************** * Name: efm32_dmastop |