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authorGregory Nutt <gnutt@nuttx.org>2014-08-24 14:12:45 -0600
committerGregory Nutt <gnutt@nuttx.org>2014-08-24 14:12:45 -0600
commit54f46fc6998873b204ac161371cb1ae90ea7151d (patch)
tree565efdd20ae50c978dfda2ee4e98d100e09741d0 /nuttx/arch
parent14f5d59d7bac51278acdcd4db24af4a8624464db (diff)
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After cached related fix, the ELF example is now functional
Diffstat (limited to 'nuttx/arch')
-rw-r--r--nuttx/arch/Kconfig4
-rw-r--r--nuttx/arch/arm/Kconfig2
-rw-r--r--nuttx/arch/arm/src/a1x/Make.defs2
-rw-r--r--nuttx/arch/arm/src/armv7-a/Kconfig3
-rw-r--r--nuttx/arch/arm/src/armv7-a/arch_coherent_dcache.c94
-rw-r--r--nuttx/arch/arm/src/sama5/Make.defs2
6 files changed, 104 insertions, 3 deletions
diff --git a/nuttx/arch/Kconfig b/nuttx/arch/Kconfig
index a3537ece6..0cb83efcf 100644
--- a/nuttx/arch/Kconfig
+++ b/nuttx/arch/Kconfig
@@ -130,6 +130,10 @@ config ARCH_L2CACHE
bool
default n
+config ARCH_HAVE_COHERENT_DCACHE
+ bool
+ default n
+
config CUSTOM_STACK
bool
default n
diff --git a/nuttx/arch/arm/Kconfig b/nuttx/arch/arm/Kconfig
index 0cb3c587e..31007c7d3 100644
--- a/nuttx/arch/arm/Kconfig
+++ b/nuttx/arch/arm/Kconfig
@@ -212,12 +212,14 @@ config ARCH_CORTEXA5
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
+ select ARCH_HAVE_COHERENT_DCACHE if ELF
config ARCH_CORTEXA8
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
+ select ARCH_HAVE_COHERENT_DCACHE if ELF
config ARCH_FAMILY
string
diff --git a/nuttx/arch/arm/src/a1x/Make.defs b/nuttx/arch/arm/src/a1x/Make.defs
index 4c3755352..17eb91642 100644
--- a/nuttx/arch/arm/src/a1x/Make.defs
+++ b/nuttx/arch/arm/src/a1x/Make.defs
@@ -87,7 +87,7 @@ CMN_CSRCS += arm_addrenv.c
endif
ifeq ($(CONFIG_ELF),y)
-CMN_CSRCS += arm_elf.c
+CMN_CSRCS += arm_elf.c arch_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
diff --git a/nuttx/arch/arm/src/armv7-a/Kconfig b/nuttx/arch/arm/src/armv7-a/Kconfig
index dc85421b5..fb82ad13b 100644
--- a/nuttx/arch/arm/src/armv7-a/Kconfig
+++ b/nuttx/arch/arm/src/armv7-a/Kconfig
@@ -9,7 +9,8 @@ config ARMV7A_HAVE_L2CC
bool
default n
---help---
- Selected by the configuration tool if the architecutre supports any kind of L2 cache.
+ Selected by the configuration tool if the architecutre supports any
+ kind of L2 cache.
config ARMV7A_HAVE_L2CC_PL310
bool
diff --git a/nuttx/arch/arm/src/armv7-a/arch_coherent_dcache.c b/nuttx/arch/arm/src/armv7-a/arch_coherent_dcache.c
new file mode 100644
index 000000000..4ab5acf49
--- /dev/null
+++ b/nuttx/arch/arm/src/armv7-a/arch_coherent_dcache.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+ * arch/arm/src/armv7/arch_undefinedinsn.c
+ *
+ * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+
+#include "cp15_cacheops.h"
+
+#include <nuttx/binfmt/elf.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arch_coherent_dcache
+ *
+ * Description:
+ * Ensure that the I and D caches are coherent within specified region
+ * by cleaning the D cache (i.e., flushing the D cache contents to memory
+ * and invalidating the I cache. This is typically used when code has been
+ * written to a memory region, and will be executed.
+ *
+ * Input Parameters:
+ * addr - virtual start address of region
+ * len - Size of the address region in bytes
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void arch_coherent_dcache(uintptr_t addr, size_t len)
+{
+ /* Perform the operation on the L1 cache */
+
+ cp15_coherent_dcache(addr, addr+len);
+
+#ifdef CONFIG_ARCH_L2CACHE
+ /* If we have an L2 cache, then there more things that need to done */
+
+# warning This is insufficient
+#endif
+}
diff --git a/nuttx/arch/arm/src/sama5/Make.defs b/nuttx/arch/arm/src/sama5/Make.defs
index c588864c2..4adc5bdd3 100644
--- a/nuttx/arch/arm/src/sama5/Make.defs
+++ b/nuttx/arch/arm/src/sama5/Make.defs
@@ -89,7 +89,7 @@ CMN_CSRCS += arm_addrenv.c
endif
ifeq ($(CONFIG_ELF),y)
-CMN_CSRCS += arm_elf.c
+CMN_CSRCS += arm_elf.c arch_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)