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| author | Gregory Nutt <gnutt@nuttx.org> | 2014-02-22 10:32:28 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2014-02-22 10:32:28 -0600 |
| commit | 336e93df0acfc8c3c4db17ee236d245c2a00da5e (patch) | |
| tree | 42b88d976fa045682a7dc847398869917e4a8a57 /nuttx/arch | |
| parent | f94ed85a9d85ceb0144c6053cb2230cc758983bf (diff) | |
| download | px4-nuttx-336e93df0acfc8c3c4db17ee236d245c2a00da5e.tar.gz px4-nuttx-336e93df0acfc8c3c4db17ee236d245c2a00da5e.tar.bz2 px4-nuttx-336e93df0acfc8c3c4db17ee236d245c2a00da5e.zip | |
SAM4E: Update PMC and SPI register definition header files
Diffstat (limited to 'nuttx/arch')
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam_spi.h | 9 |
2 files changed, 7 insertions, 4 deletions
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h index d04150008..8fd82a8f4 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -185,7 +185,7 @@ * Clock Status Register common bit-field definitions */ -#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4S) +#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM4S) # define PMC_UOTGCLK (1 << 5) /* Bit 5: Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */ #endif diff --git a/nuttx/arch/arm/src/sam34/chip/sam_spi.h b/nuttx/arch/arm/src/sam34/chip/sam_spi.h index b19ba1b4e..25ac74c51 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_spi.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_spi.h @@ -1,6 +1,6 @@ /**************************************************************************************** * arch/arm/src/sam34/chip/sam_spi.h - * Serial Peripheral Interface (SPI) definitions for the SAM3U, SAM4S, and SAM4L + * Serial Peripheral Interface (SPI) definitions for the SAM3U, SAM4S, SAM4E, and SAM4L * * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> @@ -78,7 +78,7 @@ #endif /* 0x100-0x124 Reserved for PDC Registers */ -/* SPI register adresses ****************************************************************/ +/* SPI register addresses ***************************************************************/ #define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ #define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ @@ -188,7 +188,7 @@ #define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */ #define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */ -#if defined(CONFIG_ARCH_CHIP_SAM4S) +#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) # define SPI_INT_ENDRX (1 << 4) /* Bit 4: End of RX buffer */ # define SPI_INT_ENDTX (1 << 5) /* Bit 5: End of TX buffer */ # define SPI_INT_RXBUFF (1 << 6) /* Bit 6: RX Buffer Full */ @@ -220,10 +220,13 @@ # define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */ #define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ #define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT) +# define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT) #define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */ #define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT) +# define SPI_CSR_DLYBS(n) ((uint32_t)(n) << SPI_CSR_DLYBS_SHIFT) #define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */ #define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT) +# define SPI_CSR_DLYBCT(n) ((uint32_t)(n) << SPI_CSR_DLYBCT_SHIFT) /* SPI Write Protection Control Register */ |