PIC32MZ: Correct the base address of Ethernet registers. From Kristopher Tate

1 files changed, 186 insertions, 186 deletions

diff --git a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-ethernet.h b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-ethernet.h
index 753c3d9fd..ae0836589 100644
--- a/nuttx/arch/mips/src/pic32mz/chip/pic32mz-ethernet.h
+++ b/nuttx/arch/mips/src/pic32mz/chip/pic32mz-ethernet.h
@@ -260,207 +260,207 @@
 
 /* Controller and DMA Engine Configuration/Status Registers */
 
-#define PIC32MZ_ETH_CON1               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON1_OFFSET)
-#define PIC32MZ_ETH_CON1CLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON1CLR_OFFSET)
-#define PIC32MZ_ETH_CON1SET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON1SET_OFFSET)
-#define PIC32MZ_ETH_CON1INV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON1INV_OFFSET)
-
-#define PIC32MZ_ETH_CON2               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON2_OFFSET)
-#define PIC32MZ_ETH_CON2CLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON2CLR_OFFSET)
-#define PIC32MZ_ETH_CON2SET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON2SET_OFFSET)
-#define PIC32MZ_ETH_CON2INV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_CON2INV_OFFSET)
-
-#define PIC32MZ_ETH_TXST               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_TXST_OFFSET)
-#define PIC32MZ_ETH_TXSTCLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_TXSTCLR_OFFSET)
-#define PIC32MZ_ETH_TXSTSET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_TXSTSET_OFFSET)
-#define PIC32MZ_ETH_TXSTINV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_TXSTINV_OFFSET)
-
-#define PIC32MZ_ETH_RXST               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXST_OFFSET)
-#define PIC32MZ_ETH_RXSTCLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXSTCLR_OFFSET)
-#define PIC32MZ_ETH_RXSTSET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXSTSET_OFFSET)
-#define PIC32MZ_ETH_RXSTINV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXSTINV_OFFSET)
-
-#define PIC32MZ_ETH_IEN                (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IEN_OFFSET)
-#define PIC32MZ_ETH_IENCLR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IENCLR_OFFSET)
-#define PIC32MZ_ETH_IENSET             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IENSET_OFFSET)
-#define PIC32MZ_ETH_IENINV             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IENINV_OFFSET)
-
-#define PIC32MZ_ETH_IRQ                (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IRQ_OFFSET)
-#define PIC32MZ_ETH_IRQCLR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IRQCLR_OFFSET)
-#define PIC32MZ_ETH_IRQSET             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IRQSET_OFFSET)
-#define PIC32MZ_ETH_IRQINV             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_IRQINV_OFFSET)
-
-#define PIC32MZ_ETH_STAT               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_STAT_OFFSET)
+#define PIC32MZ_ETH_CON1               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON1_OFFSET)
+#define PIC32MZ_ETH_CON1CLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON1CLR_OFFSET)
+#define PIC32MZ_ETH_CON1SET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON1SET_OFFSET)
+#define PIC32MZ_ETH_CON1INV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON1INV_OFFSET)
+
+#define PIC32MZ_ETH_CON2               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON2_OFFSET)
+#define PIC32MZ_ETH_CON2CLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON2CLR_OFFSET)
+#define PIC32MZ_ETH_CON2SET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON2SET_OFFSET)
+#define PIC32MZ_ETH_CON2INV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_CON2INV_OFFSET)
+
+#define PIC32MZ_ETH_TXST               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_TXST_OFFSET)
+#define PIC32MZ_ETH_TXSTCLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_TXSTCLR_OFFSET)
+#define PIC32MZ_ETH_TXSTSET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_TXSTSET_OFFSET)
+#define PIC32MZ_ETH_TXSTINV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_TXSTINV_OFFSET)
+
+#define PIC32MZ_ETH_RXST               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXST_OFFSET)
+#define PIC32MZ_ETH_RXSTCLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXSTCLR_OFFSET)
+#define PIC32MZ_ETH_RXSTSET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXSTSET_OFFSET)
+#define PIC32MZ_ETH_RXSTINV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXSTINV_OFFSET)
+
+#define PIC32MZ_ETH_IEN                (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IEN_OFFSET)
+#define PIC32MZ_ETH_IENCLR             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IENCLR_OFFSET)
+#define PIC32MZ_ETH_IENSET             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IENSET_OFFSET)
+#define PIC32MZ_ETH_IENINV             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IENINV_OFFSET)
+
+#define PIC32MZ_ETH_IRQ                (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IRQ_OFFSET)
+#define PIC32MZ_ETH_IRQCLR             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IRQCLR_OFFSET)
+#define PIC32MZ_ETH_IRQSET             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IRQSET_OFFSET)
+#define PIC32MZ_ETH_IRQINV             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_IRQINV_OFFSET)
+
+#define PIC32MZ_ETH_STAT               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_STAT_OFFSET)
 
 /* RX Filtering Configuration Registers */
 
-#define PIC32MZ_ETH_RXFC               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXFC_OFFSET)
-#define PIC32MZ_ETH_RXFCCLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXFCCLR_OFFSET)
-#define PIC32MZ_ETH_RXFCSET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXFCSET_OFFSET)
-#define PIC32MZ_ETH_RXFCINV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXFCINV_OFFSET)
-
-#define PIC32MZ_ETH_HT0                (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT0_OFFSET)
-#define PIC32MZ_ETH_HT0CLR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT0CLR_OFFSET)
-#define PIC32MZ_ETH_HT0SET             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT0SET_OFFSET)
-#define PIC32MZ_ETH_HT0INV             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT0INV_OFFSET)
-
-#define PIC32MZ_ETH_HT1                (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT1_OFFSET)
-#define PIC32MZ_ETH_HT1CLR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT1CLR_OFFSET)
-#define PIC32MZ_ETH_HT1SET             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT1SET_OFFSET)
-#define PIC32MZ_ETH_HT1INV             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_HT1INV_OFFSET)
-
-#define PIC32MZ_ETH_PMM0               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM0_OFFSET)
-#define PIC32MZ_ETH_PMM0CLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM0CLR_OFFSET)
-#define PIC32MZ_ETH_PMM0SET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM0SET_OFFSET)
-#define PIC32MZ_ETH_PMM0INV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM0INV_OFFSET)
-
-#define PIC32MZ_ETH_PMM1               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM1_OFFSET)
-#define PIC32MZ_ETH_PMM1CLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM1CLR_OFFSET)
-#define PIC32MZ_ETH_PMM1SET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM1SET_OFFSET)
-#define PIC32MZ_ETH_PMM1INV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMM1INV_OFFSET)
-
-#define PIC32MZ_ETH_PMCS               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMCS_OFFSET)
-#define PIC32MZ_ETH_PMCSCLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMCSCLR_OFFSET)
-#define PIC32MZ_ETH_PMCSSET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMCSSET_OFFSET)
-#define PIC32MZ_ETH_PMCSINV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMCSINV_OFFSET)
-
-#define PIC32MZ_ETH_PMO                (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMO_OFFSET)
-#define PIC32MZ_ETH_PMOCLR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMOCLR_OFFSET)
-#define PIC32MZ_ETH_PMOSET             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMOSET_OFFSET)
-#define PIC32MZ_ETH_PMOINV             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_PMOINV_OFFSET)
+#define PIC32MZ_ETH_RXFC               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXFC_OFFSET)
+#define PIC32MZ_ETH_RXFCCLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXFCCLR_OFFSET)
+#define PIC32MZ_ETH_RXFCSET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXFCSET_OFFSET)
+#define PIC32MZ_ETH_RXFCINV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXFCINV_OFFSET)
+
+#define PIC32MZ_ETH_HT0                (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT0_OFFSET)
+#define PIC32MZ_ETH_HT0CLR             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT0CLR_OFFSET)
+#define PIC32MZ_ETH_HT0SET             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT0SET_OFFSET)
+#define PIC32MZ_ETH_HT0INV             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT0INV_OFFSET)
+
+#define PIC32MZ_ETH_HT1                (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT1_OFFSET)
+#define PIC32MZ_ETH_HT1CLR             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT1CLR_OFFSET)
+#define PIC32MZ_ETH_HT1SET             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT1SET_OFFSET)
+#define PIC32MZ_ETH_HT1INV             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_HT1INV_OFFSET)
+
+#define PIC32MZ_ETH_PMM0               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM0_OFFSET)
+#define PIC32MZ_ETH_PMM0CLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM0CLR_OFFSET)
+#define PIC32MZ_ETH_PMM0SET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM0SET_OFFSET)
+#define PIC32MZ_ETH_PMM0INV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM0INV_OFFSET)
+
+#define PIC32MZ_ETH_PMM1               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM1_OFFSET)
+#define PIC32MZ_ETH_PMM1CLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM1CLR_OFFSET)
+#define PIC32MZ_ETH_PMM1SET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM1SET_OFFSET)
+#define PIC32MZ_ETH_PMM1INV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMM1INV_OFFSET)
+
+#define PIC32MZ_ETH_PMCS               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMCS_OFFSET)
+#define PIC32MZ_ETH_PMCSCLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMCSCLR_OFFSET)
+#define PIC32MZ_ETH_PMCSSET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMCSSET_OFFSET)
+#define PIC32MZ_ETH_PMCSINV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMCSINV_OFFSET)
+
+#define PIC32MZ_ETH_PMO                (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMO_OFFSET)
+#define PIC32MZ_ETH_PMOCLR             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMOCLR_OFFSET)
+#define PIC32MZ_ETH_PMOSET             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMOSET_OFFSET)
+#define PIC32MZ_ETH_PMOINV             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_PMOINV_OFFSET)
 
 /* Flow Control Configuring Register */
 
-#define PIC32MZ_ETH_RXWM               (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXWM_OFFSET)
-#define PIC32MZ_ETH_RXWMCLR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXWMCLR_OFFSET)
-#define PIC32MZ_ETH_RXWMSET            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXWMSET_OFFSET)
-#define PIC32MZ_ETH_RXWMINV            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXWMINV_OFFSET)
+#define PIC32MZ_ETH_RXWM               (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXWM_OFFSET)
+#define PIC32MZ_ETH_RXWMCLR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXWMCLR_OFFSET)
+#define PIC32MZ_ETH_RXWMSET            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXWMSET_OFFSET)
+#define PIC32MZ_ETH_RXWMINV            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXWMINV_OFFSET)
 
 /* Ethernet Statistics Registers */
 
-#define PIC32MZ_ETH_RXOVFLOW           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXOVFLOW_OFFSET)
-#define PIC32MZ_ETH_RXOVFLOWCLR        (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXOVFLOWCLR_OFFSET)
-#define PIC32MZ_ETH_RXOVFLOWSET        (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXOVFLOWSET_OFFSET)
-#define PIC32MZ_ETH_RXOVFLOWINV        (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_RXOVFLOWINV_OFFSET)
-
-#define PIC32MZ_ETH_FRMTXOK            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMTXOK_OFFSET)
-#define PIC32MZ_ETH_FRMTXOKCLR         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMTXOKCLR_OFFSET)
-#define PIC32MZ_ETH_FRMTXOKSET         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMTXOKSET_OFFSET)
-#define PIC32MZ_ETH_FRMTXOKINV         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMTXOKINV_OFFSET)
-
-#define PIC32MZ_ETH_SCOLFRM            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_SCOLFRM_OFFSET)
-#define PIC32MZ_ETH_SCOLFRMCLR         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_SCOLFRMCLR_OFFSET)
-#define PIC32MZ_ETH_SCOLFRMSET         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_SCOLFRMSET_OFFSET)
-#define PIC32MZ_ETH_SCOLFRMINV         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_SCOLFRMINV_OFFSET)
-
-#define PIC32MZ_ETH_MCOLFRM            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_MCOLFRM_OFFSET)
-#define PIC32MZ_ETH_MCOLFRMCLR         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_MCOLFRMCLR_OFFSET)
-#define PIC32MZ_ETH_MCOLFRMSET         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_MCOLFRMSET_OFFSET)
-#define PIC32MZ_ETH_MCOLFRMINV         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_MCOLFRMINV_OFFSET)
-
-#define PIC32MZ_ETH_FRMRXOK            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMRXOK_OFFSET)
-#define PIC32MZ_ETH_FRMRXOKCLR         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMRXOKCLR_OFFSET)
-#define PIC32MZ_ETH_FRMRXOKSET         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMRXOKSET_OFFSET)
-#define PIC32MZ_ETH_FRMRXOKINV         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FRMRXOKINV_OFFSET)
-
-#define PIC32MZ_ETH_FCSERR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FCSERR_OFFSET)
-#define PIC32MZ_ETH_FCSERRCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FCSERRCLR_OFFSET)
-#define PIC32MZ_ETH_FCSERRSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FCSERRSET_OFFSET)
-#define PIC32MZ_ETH_FCSERRINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_FCSERRINV_OFFSET)
-
-#define PIC32MZ_ETH_ALGNERR            (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_ALGNERR_OFFSET)
-#define PIC32MZ_ETH_ALGNERRCLR         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_ALGNERRCLR_OFFSET)
-#define PIC32MZ_ETH_ALGNERRSET         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_ALGNERRSET_OFFSET)
-#define PIC32MZ_ETH_ALGNERRINV         (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_ETH_ALGNERRINV_OFFSET)
+#define PIC32MZ_ETH_RXOVFLOW           (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXOVFLOW_OFFSET)
+#define PIC32MZ_ETH_RXOVFLOWCLR        (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXOVFLOWCLR_OFFSET)
+#define PIC32MZ_ETH_RXOVFLOWSET        (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXOVFLOWSET_OFFSET)
+#define PIC32MZ_ETH_RXOVFLOWINV        (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_RXOVFLOWINV_OFFSET)
+
+#define PIC32MZ_ETH_FRMTXOK            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMTXOK_OFFSET)
+#define PIC32MZ_ETH_FRMTXOKCLR         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMTXOKCLR_OFFSET)
+#define PIC32MZ_ETH_FRMTXOKSET         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMTXOKSET_OFFSET)
+#define PIC32MZ_ETH_FRMTXOKINV         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMTXOKINV_OFFSET)
+
+#define PIC32MZ_ETH_SCOLFRM            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_SCOLFRM_OFFSET)
+#define PIC32MZ_ETH_SCOLFRMCLR         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_SCOLFRMCLR_OFFSET)
+#define PIC32MZ_ETH_SCOLFRMSET         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_SCOLFRMSET_OFFSET)
+#define PIC32MZ_ETH_SCOLFRMINV         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_SCOLFRMINV_OFFSET)
+
+#define PIC32MZ_ETH_MCOLFRM            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_MCOLFRM_OFFSET)
+#define PIC32MZ_ETH_MCOLFRMCLR         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_MCOLFRMCLR_OFFSET)
+#define PIC32MZ_ETH_MCOLFRMSET         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_MCOLFRMSET_OFFSET)
+#define PIC32MZ_ETH_MCOLFRMINV         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_MCOLFRMINV_OFFSET)
+
+#define PIC32MZ_ETH_FRMRXOK            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMRXOK_OFFSET)
+#define PIC32MZ_ETH_FRMRXOKCLR         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMRXOKCLR_OFFSET)
+#define PIC32MZ_ETH_FRMRXOKSET         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMRXOKSET_OFFSET)
+#define PIC32MZ_ETH_FRMRXOKINV         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FRMRXOKINV_OFFSET)
+
+#define PIC32MZ_ETH_FCSERR             (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FCSERR_OFFSET)
+#define PIC32MZ_ETH_FCSERRCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FCSERRCLR_OFFSET)
+#define PIC32MZ_ETH_FCSERRSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FCSERRSET_OFFSET)
+#define PIC32MZ_ETH_FCSERRINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_FCSERRINV_OFFSET)
+
+#define PIC32MZ_ETH_ALGNERR            (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_ALGNERR_OFFSET)
+#define PIC32MZ_ETH_ALGNERRCLR         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_ALGNERRCLR_OFFSET)
+#define PIC32MZ_ETH_ALGNERRSET         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_ALGNERRSET_OFFSET)
+#define PIC32MZ_ETH_ALGNERRINV         (PIC32MZ_ETH_K1BASE+PIC32MZ_ETH_ALGNERRINV_OFFSET)
 
 /* MAC Configuration Registers */
 
-#define PIC32MZ_EMAC1_CFG1             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG1_OFFSET)
-#define PIC32MZ_EMAC1_CFG1CLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG1CLR_OFFSET)
-#define PIC32MZ_EMAC1_CFG1SET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG1SET_OFFSET)
-#define PIC32MZ_EMAC1_CFG1INV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG1INV_OFFSET)
-
-#define PIC32MZ_EMAC1_CFG2             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG2_OFFSET)
-#define PIC32MZ_EMAC1_CFG2CLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG2CLR_OFFSET)
-#define PIC32MZ_EMAC1_CFG2SET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG2SET_OFFSET)
-#define PIC32MZ_EMAC1_CFG2INV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CFG2INV_OFFSET)
-
-#define PIC32MZ_EMAC1_IPGT             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGT_OFFSET)
-#define PIC32MZ_EMAC1_IPGTCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGTCLR_OFFSET)
-#define PIC32MZ_EMAC1_IPGTSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGTSET_OFFSET)
-#define PIC32MZ_EMAC1_IPGTINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGTINV_OFFSET)
-
-#define PIC32MZ_EMAC1_IPGR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGR_OFFSET)
-#define PIC32MZ_EMAC1_IPGRCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGRCLR_OFFSET)
-#define PIC32MZ_EMAC1_IPGRSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGRSET_OFFSET)
-#define PIC32MZ_EMAC1_IPGRINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_IPGRINV_OFFSET)
-
-#define PIC32MZ_EMAC1_CLRT             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CLRT_OFFSET)
-#define PIC32MZ_EMAC1_CLRTCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CLRTCLR_OFFSET)
-#define PIC32MZ_EMAC1_CLRTSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CLRTSET_OFFSET)
-#define PIC32MZ_EMAC1_CLRTINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_CLRTINV_OFFSET)
-
-#define PIC32MZ_EMAC1_MAXF             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MAXF_OFFSET)
-#define PIC32MZ_EMAC1_MAXFCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MAXFCLR_OFFSET)
-#define PIC32MZ_EMAC1_MAXFSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MAXFSET_OFFSET)
-#define PIC32MZ_EMAC1_MAXFINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MAXFINV_OFFSET)
-
-#define PIC32MZ_EMAC1_SUPP             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SUPP_OFFSET)
-#define PIC32MZ_EMAC1_SUPPCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SUPPCLR_OFFSET)
-#define PIC32MZ_EMAC1_SUPPSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SUPPSET_OFFSET)
-#define PIC32MZ_EMAC1_SUPPINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SUPPINV_OFFSET)
-
-#define PIC32MZ_EMAC1_TEST             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_TEST_OFFSET)
-#define PIC32MZ_EMAC1_TESTCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_TESTCLR_OFFSET)
-#define PIC32MZ_EMAC1_TESTSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_TESTSET_OFFSET)
-#define PIC32MZ_EMAC1_TESTINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_TESTINV_OFFSET)
-
-#define PIC32MZ_EMAC1_SA0              (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA0_OFFSET)
-#define PIC32MZ_EMAC1_SA0CLR           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA0CLR_OFFSET)
-#define PIC32MZ_EMAC1_SA0SET           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA0SET_OFFSET)
-#define PIC32MZ_EMAC1_SA0INV           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA0INV_OFFSET)
-
-#define PIC32MZ_EMAC1_SA1              (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA1_OFFSET)
-#define PIC32MZ_EMAC1_SA1CLR           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA1CLR_OFFSET)
-#define PIC32MZ_EMAC1_SA1SET           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA1SET_OFFSET)
-#define PIC32MZ_EMAC1_SA1INV           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA1INV_OFFSET)
-
-#define PIC32MZ_EMAC1_SA2              (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA2_OFFSET)
-#define PIC32MZ_EMAC1_SA2CLR           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA2CLR_OFFSET)
-#define PIC32MZ_EMAC1_SA2SET           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA2SET_OFFSET)
-#define PIC32MZ_EMAC1_SA2INV           (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_SA2INV_OFFSET)
+#define PIC32MZ_EMAC1_CFG1             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG1_OFFSET)
+#define PIC32MZ_EMAC1_CFG1CLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG1CLR_OFFSET)
+#define PIC32MZ_EMAC1_CFG1SET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG1SET_OFFSET)
+#define PIC32MZ_EMAC1_CFG1INV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG1INV_OFFSET)
+
+#define PIC32MZ_EMAC1_CFG2             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG2_OFFSET)
+#define PIC32MZ_EMAC1_CFG2CLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG2CLR_OFFSET)
+#define PIC32MZ_EMAC1_CFG2SET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG2SET_OFFSET)
+#define PIC32MZ_EMAC1_CFG2INV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CFG2INV_OFFSET)
+
+#define PIC32MZ_EMAC1_IPGT             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGT_OFFSET)
+#define PIC32MZ_EMAC1_IPGTCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGTCLR_OFFSET)
+#define PIC32MZ_EMAC1_IPGTSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGTSET_OFFSET)
+#define PIC32MZ_EMAC1_IPGTINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGTINV_OFFSET)
+
+#define PIC32MZ_EMAC1_IPGR             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGR_OFFSET)
+#define PIC32MZ_EMAC1_IPGRCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGRCLR_OFFSET)
+#define PIC32MZ_EMAC1_IPGRSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGRSET_OFFSET)
+#define PIC32MZ_EMAC1_IPGRINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_IPGRINV_OFFSET)
+
+#define PIC32MZ_EMAC1_CLRT             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CLRT_OFFSET)
+#define PIC32MZ_EMAC1_CLRTCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CLRTCLR_OFFSET)
+#define PIC32MZ_EMAC1_CLRTSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CLRTSET_OFFSET)
+#define PIC32MZ_EMAC1_CLRTINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_CLRTINV_OFFSET)
+
+#define PIC32MZ_EMAC1_MAXF             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MAXF_OFFSET)
+#define PIC32MZ_EMAC1_MAXFCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MAXFCLR_OFFSET)
+#define PIC32MZ_EMAC1_MAXFSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MAXFSET_OFFSET)
+#define PIC32MZ_EMAC1_MAXFINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MAXFINV_OFFSET)
+
+#define PIC32MZ_EMAC1_SUPP             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SUPP_OFFSET)
+#define PIC32MZ_EMAC1_SUPPCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SUPPCLR_OFFSET)
+#define PIC32MZ_EMAC1_SUPPSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SUPPSET_OFFSET)
+#define PIC32MZ_EMAC1_SUPPINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SUPPINV_OFFSET)
+
+#define PIC32MZ_EMAC1_TEST             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_TEST_OFFSET)
+#define PIC32MZ_EMAC1_TESTCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_TESTCLR_OFFSET)
+#define PIC32MZ_EMAC1_TESTSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_TESTSET_OFFSET)
+#define PIC32MZ_EMAC1_TESTINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_TESTINV_OFFSET)
+
+#define PIC32MZ_EMAC1_SA0              (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA0_OFFSET)
+#define PIC32MZ_EMAC1_SA0CLR           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA0CLR_OFFSET)
+#define PIC32MZ_EMAC1_SA0SET           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA0SET_OFFSET)
+#define PIC32MZ_EMAC1_SA0INV           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA0INV_OFFSET)
+
+#define PIC32MZ_EMAC1_SA1              (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA1_OFFSET)
+#define PIC32MZ_EMAC1_SA1CLR           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA1CLR_OFFSET)
+#define PIC32MZ_EMAC1_SA1SET           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA1SET_OFFSET)
+#define PIC32MZ_EMAC1_SA1INV           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA1INV_OFFSET)
+
+#define PIC32MZ_EMAC1_SA2              (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA2_OFFSET)
+#define PIC32MZ_EMAC1_SA2CLR           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA2CLR_OFFSET)
+#define PIC32MZ_EMAC1_SA2SET           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA2SET_OFFSET)
+#define PIC32MZ_EMAC1_SA2INV           (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_SA2INV_OFFSET)
 
 /* MII Management Registers */
 
-#define PIC32MZ_EMAC1_MCFG             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCFG_OFFSET)
-#define PIC32MZ_EMAC1_MCFGCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCFGCLR_OFFSET)
-#define PIC32MZ_EMAC1_MCFGSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCFGSET_OFFSET)
-#define PIC32MZ_EMAC1_MCFGINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCFGINV_OFFSET)
-
-#define PIC32MZ_EMAC1_MCMD             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCMD_OFFSET)
-#define PIC32MZ_EMAC1_MCMDCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCMDCLR_OFFSET)
-#define PIC32MZ_EMAC1_MCMDSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCMDSET_OFFSET)
-#define PIC32MZ_EMAC1_MCMDINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MCMDINV_OFFSET)
-
-#define PIC32MZ_EMAC1_MADR             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MADR_OFFSET)
-#define PIC32MZ_EMAC1_MADRCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MADRCLR_OFFSET)
-#define PIC32MZ_EMAC1_MADRSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MADRSET_OFFSET)
-#define PIC32MZ_EMAC1_MADRINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MADRINV_OFFSET)
-
-#define PIC32MZ_EMAC1_MWTD             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MWTD_OFFSET)
-#define PIC32MZ_EMAC1_MWTDCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MWTDCLR_OFFSET)
-#define PIC32MZ_EMAC1_MWTDSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MWTDSET_OFFSET)
-#define PIC32MZ_EMAC1_MWTDINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MWTDINV_OFFSET)
-
-#define PIC32MZ_EMAC1_MRDD             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MRDD_OFFSET)
-#define PIC32MZ_EMAC1_MRDDCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MRDDCLR_OFFSET)
-#define PIC32MZ_EMAC1_MRDDSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MRDDSET_OFFSET)
-#define PIC32MZ_EMAC1_MRDDINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MRDDINV_OFFSET)
-
-#define PIC32MZ_EMAC1_MIND             (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MIND_OFFSET)
-#define PIC32MZ_EMAC1_MINDCLR          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MINDCLR_OFFSET)
-#define PIC32MZ_EMAC1_MINDSET          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MINDSET_OFFSET)
-#define PIC32MZ_EMAC1_MINDINV          (PIC32MZ_ETHERNET_K1BASE+PIC32MZ_EMAC1_MINDINV_OFFSET)
+#define PIC32MZ_EMAC1_MCFG             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCFG_OFFSET)
+#define PIC32MZ_EMAC1_MCFGCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCFGCLR_OFFSET)
+#define PIC32MZ_EMAC1_MCFGSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCFGSET_OFFSET)
+#define PIC32MZ_EMAC1_MCFGINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCFGINV_OFFSET)
+
+#define PIC32MZ_EMAC1_MCMD             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCMD_OFFSET)
+#define PIC32MZ_EMAC1_MCMDCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCMDCLR_OFFSET)
+#define PIC32MZ_EMAC1_MCMDSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCMDSET_OFFSET)
+#define PIC32MZ_EMAC1_MCMDINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MCMDINV_OFFSET)
+
+#define PIC32MZ_EMAC1_MADR             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MADR_OFFSET)
+#define PIC32MZ_EMAC1_MADRCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MADRCLR_OFFSET)
+#define PIC32MZ_EMAC1_MADRSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MADRSET_OFFSET)
+#define PIC32MZ_EMAC1_MADRINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MADRINV_OFFSET)
+
+#define PIC32MZ_EMAC1_MWTD             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MWTD_OFFSET)
+#define PIC32MZ_EMAC1_MWTDCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MWTDCLR_OFFSET)
+#define PIC32MZ_EMAC1_MWTDSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MWTDSET_OFFSET)
+#define PIC32MZ_EMAC1_MWTDINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MWTDINV_OFFSET)
+
+#define PIC32MZ_EMAC1_MRDD             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MRDD_OFFSET)
+#define PIC32MZ_EMAC1_MRDDCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MRDDCLR_OFFSET)
+#define PIC32MZ_EMAC1_MRDDSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MRDDSET_OFFSET)
+#define PIC32MZ_EMAC1_MRDDINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MRDDINV_OFFSET)
+
+#define PIC32MZ_EMAC1_MIND             (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MIND_OFFSET)
+#define PIC32MZ_EMAC1_MINDCLR          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MINDCLR_OFFSET)
+#define PIC32MZ_EMAC1_MINDSET          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MINDSET_OFFSET)
+#define PIC32MZ_EMAC1_MINDINV          (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MINDINV_OFFSET)
 
 /* Register Bit-Field Definitions *******************************************************************/