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| author | Gregory Nutt <gnutt@nuttx.org> | 2013-07-29 13:57:32 -0600 |
|---|---|---|
| committer | Gregory Nutt <gnutt@nuttx.org> | 2013-07-29 13:57:32 -0600 |
| commit | 6c9ec4933e27d479b84110b1f6f866a631300896 (patch) | |
| tree | 50ea0741adf2a4abdd0cf7ffe58ac971a0b3be7e /nuttx/configs/sama5d3x-ek/src/sam_norflash.c | |
| parent | d9acab47a1967713a2d328df3dca486ff07acd39 (diff) | |
| download | px4-nuttx-6c9ec4933e27d479b84110b1f6f866a631300896.tar.gz px4-nuttx-6c9ec4933e27d479b84110b1f6f866a631300896.tar.bz2 px4-nuttx-6c9ec4933e27d479b84110b1f6f866a631300896.zip | |
SAMA5: Add a little NuttX debug program to help debugger programs in NOR flash
Diffstat (limited to 'nuttx/configs/sama5d3x-ek/src/sam_norflash.c')
| -rw-r--r-- | nuttx/configs/sama5d3x-ek/src/sam_norflash.c | 31 |
1 files changed, 14 insertions, 17 deletions
diff --git a/nuttx/configs/sama5d3x-ek/src/sam_norflash.c b/nuttx/configs/sama5d3x-ek/src/sam_norflash.c index a4cef988a..3604dcfc2 100644 --- a/nuttx/configs/sama5d3x-ek/src/sam_norflash.c +++ b/nuttx/configs/sama5d3x-ek/src/sam_norflash.c @@ -108,33 +108,30 @@ void board_norflash_config(void) sam_hsmc_enableclk(); - /* The SAMA5D3x-EK has NOR FLASH at CS0. The NOR FLASH has already been - * configured by the first level ROM bootloader... we simply need to modify - * the timints here. + /* The SAMA5D3x-EK has 118MB of 16-bit NOR FLASH at CS0. The NOR FLASH + * has already been configured by the first level ROM bootloader... we + * simply need to modify the timing here. */ - /* Configure SMC, NCS0 is assigned to a norflash */ - - regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(0) | - HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(0); + regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(0) | + HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(0); putreg32(regval, SAM_HSMC_SETUP(HSMC_CS0)); - regval = HSMC_PULSE_NWE_PULSE(10) | HSMC_PULSE_NCS_WRPULSE(10) | - HSMC_PULSE_NRD_PULSE(11) | HSMC_PULSE_NCS_RDPULSE(11); + regval = HSMC_PULSE_NWE_PULSE(10) | HSMC_PULSE_NCS_WRPULSE(10) | + HSMC_PULSE_NRD_PULSE(11) | HSMC_PULSE_NCS_RDPULSE(11); putreg32(regval, SAM_HSMC_PULSE(HSMC_CS0)); - regval = HSMC_CYCLE_NWE_CYCLE(11) | HSMC_CYCLE_NRD_CYCLE(14); + regval = HSMC_CYCLE_NWE_CYCLE(11) | HSMC_CYCLE_NRD_CYCLE(14); putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS0)); - regval = HSMC_TIMINGS_TCLR(0) | HSMC_TIMINGS_TADL(0) | - HSMC_TIMINGS_TAR(0) | HSMC_TIMINGS_TRR(0) | - HSMC_TIMINGS_TWB(0) | HSMC_TIMINGS_RBNSEL(0); + regval = HSMC_TIMINGS_TCLR(0) | HSMC_TIMINGS_TADL(0) | + HSMC_TIMINGS_TAR(0) | HSMC_TIMINGS_TRR(0) | + HSMC_TIMINGS_TWB(0) | HSMC_TIMINGS_RBNSEL(0); putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS0)); - regval = getreg32(SAM_HSMC_MODE(HSMC_CS0)); - regval &= HSMC_MODE_DBW; /* Preserve the data bus width */ - regval |= HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE | - HSMC_MODE_EXNWMODE_DISABLED | HSMC_MODE_TDFCYCLES(1); + regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE | + HSMC_MODE_EXNWMODE_DISABLED | HSMC_MODE_BIT_16 | + HSMC_MODE_TDFCYCLES(1); putreg32(regval, SAM_HSMC_MODE(HSMC_CS0)); } |