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| author | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-03-14 14:14:54 +0000 |
|---|---|---|
| committer | patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> | 2011-03-14 14:14:54 +0000 |
| commit | ee2220174467b0e456446f5faaef1bd1660f786e (patch) | |
| tree | 61937f54d7558e15f984b0450c2958e9ed45b5bd /nuttx/configs/vsn/src/sysclock.c | |
| parent | 38121cceb67b2408c5aab1d3e9998accef0d83c8 (diff) | |
| download | px4-nuttx-ee2220174467b0e456446f5faaef1bd1660f786e.tar.gz px4-nuttx-ee2220174467b0e456446f5faaef1bd1660f786e.tar.bz2 px4-nuttx-ee2220174467b0e456446f5faaef1bd1660f786e.zip | |
VSN/apps update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3378 42af7a65-404d-4744-a932-0658087f49c3
Diffstat (limited to 'nuttx/configs/vsn/src/sysclock.c')
| -rw-r--r-- | nuttx/configs/vsn/src/sysclock.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/nuttx/configs/vsn/src/sysclock.c b/nuttx/configs/vsn/src/sysclock.c index f812dd2c1..79cc80ff2 100644 --- a/nuttx/configs/vsn/src/sysclock.c +++ b/nuttx/configs/vsn/src/sysclock.c @@ -39,6 +39,7 @@ #include <arch/board/board.h> #include "stm32_rcc.h" +#include "stm32_gpio.h" #include "stm32_flash.h" #include "up_internal.h" #include "up_arch.h" @@ -123,6 +124,11 @@ void stm32_board_select_hsi(void) // Wait until the selected source is used as the system clock source while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); + + // map port PD0 and PD1 on OSC pins + regval = getreg32(STM32_AFIO_MAPR); + regval |= AFIO_MAPR_PD01_REMAP; + putreg32(regval, STM32_AFIO_MAPR); } @@ -140,6 +146,13 @@ void stm32_board_select_hsi(void) */ int stm32_board_select_hse(void) { + uint32_t regval; + + // be sure to release PD0 and PD1 pins from the OSC pins + regval = getreg32(STM32_AFIO_MAPR); + regval &= ~AFIO_MAPR_PD01_REMAP; + putreg32(regval, STM32_AFIO_MAPR); + // if (is cc1101 9 MHz clock output enabled), otherwise return with -1 // I think that clock register provides HSE valid signal to detect that as well. |