Add m9s12 serial logic

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3305 42af7a65-404d-4744-a932-0658087f49c3

1 files changed, 21 insertions, 0 deletions

diff --git a/nuttx/configs/demo9s12ne64/include/board.h b/nuttx/configs/demo9s12ne64/include/board.h
index 9420b67dd..ee190731c 100755
--- a/nuttx/configs/demo9s12ne64/include/board.h
+++ b/nuttx/configs/demo9s12ne64/include/board.h
@@ -51,9 +51,30 @@
  ************************************************************************************/
 
 /* Clocking *************************************************************************/
+/* Frequency of the crystal oscillator */
 
 #define HCS12_OSCCLK      16000000 /* 16MHz */
 
+/* PLL Settings
+ *
+ * SYNR register controls the multiplication factor of the PLL. If the PLL is on, the
+ * count in the loop divider (SYNR) register effectively multiplies up the PLL clock
+ * (PLLCLK) from the reference frequency by 2 x (SYNR+1). PLLCLK will not be below
+ * the minimum VCO frequency (fSCM).
+ *
+ * The REFDV register provides a finer granularity for the PLL multiplier steps. The
+ * count in the reference divider divides OSCCLK frequency by REFDV + 1.
+ *
+ *   PLLCLK = 2 * OSCCLK * (SYNR + 1) / (REFDV + 1)
+ *
+ * If (PLLSEL = 1), Bus Clock = PLLCLK / 2
+ */
+
+#define HCS12_SYNR_VALUE  0x15
+#define HCS12_REFDV_VALUE 0x15
+#define HCS12_PLLCLK      (2*HCS12_OSCCLK*(HCS12_SYNR+1)/(HCS12_REFDV+1))
+#define HCS12_BUSCLK      (HSC12_PLLCLK/2)
+
 /* LED definitions ******************************************************************/
 
 /* The DEMO9S12NE64 board has 2 LEDs that we will encode as: */