Incoporate new ARMv7-M exception handling logic contributed by Mike Smith

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4413 42af7a65-404d-4744-a932-0658087f49c3

2 files changed, 105 insertions, 0 deletions

diff --git a/nuttx/configs/stm3240g-eval/README.txt b/nuttx/configs/stm3240g-eval/README.txt
index 3c4f7e77c..af6e71dad 100755
--- a/nuttx/configs/stm3240g-eval/README.txt
+++ b/nuttx/configs/stm3240g-eval/README.txt
@@ -16,6 +16,8 @@ Contents
   - Ethernet
   - PWM
   - CAN
+  - FPU
+  - STM3240G-EVAL-specific Configuration Options
   - Configurations
 
 Development Environment
@@ -289,6 +291,57 @@ Configuration Options:
   CONFIG_CAN_REGDEBUG - If CONFIG_DEBUG is set, this will generate an
     dump of all CAN registers.
 
+FPU
+===
+
+FPU Configuration Options
+-------------------------
+
+There are two version of the FPU support built into the STM32 port.
+
+1. Lazy Floating Point Register Save.
+
+   This is an untested implementation that saves and restores FPU registers
+   only on context switches.  This means: (1) floating point registers are
+   not stored on each context switch and, hence, possibly better interrupt
+   performance.  But, (2) since floating point registers are not saved,
+   you cannot use floating point operations within interrupt handlers.
+
+   This logic can be enabled by simply adding the following to your .config
+   file:
+
+   CONFIG_ARCH_FPU=y
+
+2. Non-Lazy Floating Point Register Save
+
+   Mike Smith has contributed an extensive re-write of the ARMv7-M exception
+   handling logic. This includes verified support for the FPU.  These changes
+   have not yet been incorporated into the mainline and are still considered
+   experimental.  These FPU logic can be enabled with:
+
+   CONFIG_ARCH_FPU=y
+   CONFIG_ARMV7M_CMNVECTOR=y
+
+   You will probably also changes to the ld.script in if this option is selected.
+   This should work:
+
+   -ENTRY(_stext)
+   +ENTRY(__start)         /* Treat __start as the anchor for dead code stripping */
+   +EXTERN(_vectors)       /* Force the vectors to be included in the output */
+
+CFLAGS
+------
+
+To used the FPU, you will also have to modify the CFLAGS to enable compiler
+support for the ARMv7-M FPU.  As of this writing, there are not many GCC
+toolchains that will support the ARMv7-M FPU.
+
+As a minimum, you will need to CFLAG options to (1) enable hardware floating
+point code generation, and to (2) select the FPU implementation.  You might
+try something like the following in the Make.defs file:
+
+ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+
 STM3240G-EVAL-specific Configuration Options
 ============================================
 
diff --git a/nuttx/configs/stm32f4discovery/README.txt b/nuttx/configs/stm32f4discovery/README.txt
index 7492d03b0..31b950bd6 100755
--- a/nuttx/configs/stm32f4discovery/README.txt
+++ b/nuttx/configs/stm32f4discovery/README.txt
@@ -15,6 +15,7 @@ Contents
   - PWM
   - UARTs
   - Timer Inputs/Outputs
+  - FPU
   - STM32F4Discovery-specific Configuration Options
   - Configurations
 
@@ -308,6 +309,57 @@ If enabled (by setting CONFIG_QENCODER=y), then quadrature encoder will
 user TIM2 (see nsh/defconfig) and input pins PA15, and PA1 for CH1 and
 CH2, respectively (see include board.h).
 
+FPU
+===
+
+FPU Configuration Options
+-------------------------
+
+There are two version of the FPU support built into the STM32 port.
+
+1. Lazy Floating Point Register Save.
+
+   This is an untested implementation that saves and restores FPU registers
+   only on context switches.  This means: (1) floating point registers are
+   not stored on each context switch and, hence, possibly better interrupt
+   performance.  But, (2) since floating point registers are not saved,
+   you cannot use floating point operations within interrupt handlers.
+
+   This logic can be enabled by simply adding the following to your .config
+   file:
+
+   CONFIG_ARCH_FPU=y
+
+2. Non-Lazy Floating Point Register Save
+
+   Mike Smith has contributed an extensive re-write of the ARMv7-M exception
+   handling logic. This includes verified support for the FPU.  These changes
+   have not yet been incorporated into the mainline and are still considered
+   experimental.  These FPU logic can be enabled with:
+
+   CONFIG_ARCH_FPU=y
+   CONFIG_ARMV7M_CMNVECTOR=y
+
+   You will probably also changes to the ld.script in if this option is selected.
+   This should work:
+
+   -ENTRY(_stext)
+   +ENTRY(__start)         /* Treat __start as the anchor for dead code stripping */
+   +EXTERN(_vectors)       /* Force the vectors to be included in the output */
+
+CFLAGS
+------
+
+To used the FPU, you will also have to modify the CFLAGS to enable compiler
+support for the ARMv7-M FPU.  As of this writing, there are not many GCC
+toolchains that will support the ARMv7-M FPU.
+
+As a minimum, you will need to CFLAG options to (1) enable hardware floating
+point code generation, and to (2) select the FPU implementation.  You might
+try something like the following in the Make.defs file:
+
+ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+
 STM32F4Discovery-specific Configuration Options
 ===============================================