Further NAND development

4 files changed, 330 insertions, 144 deletions

diff --git a/nuttx/drivers/mtd/Kconfig b/nuttx/drivers/mtd/Kconfig
index ed9f79850..1097897f0 100644
--- a/nuttx/drivers/mtd/Kconfig
+++ b/nuttx/drivers/mtd/Kconfig
@@ -81,8 +81,55 @@ config MTD_NAND
 	---help---
 		Enable support for NAND FLASH devices.
 
+config ARCH_NAND_HWECC
+	bool
+	default n
+
 if MTD_NAND
 
+config MTD_NAND_MAXNUMBLOCKS
+	int "Max blocks"
+	default 1024
+	---help---
+		Maximum number of blocks in a device
+
+config MTD_NAND_MAXNUMPAGESPERBLOCK
+	int "Max pages per block"
+	default 256
+	---help---
+		Maximum number of pages in one block
+
+config MTD_NAND_MAXPAGEDATASIZE
+	int "Max page size"
+	default 4096
+	---help---
+		Maximum size of the data area of one page, in bytes.
+
+config MTD_NAND_MAXPAGESPARESIZE
+	int "Max size of spare area"
+	default 256
+	---help---
+		Maximum size of the spare area of one page, in bytes.
+
+config MTD_NAND_MAXSPAREECCBYTES
+	int "Max number of ECC bytes"
+	default 48
+	---help---
+		Maximum number of ECC bytes stored in the spare for one single page.
+
+config MTD_NAND_MAXSPAREEXTRABYTES
+	int "Max extra free bytes"
+	default 206
+	---help---
+		Maximum number of extra free bytes inside the spare area of a page.
+
+config MTD_NAND_MAX_HWECCSIZE
+	int "Max H/W ECC size"
+	default 200
+	depends on ARCH_NAND_HWECC
+	---help---
+		Maximum HW ECC size
+
 config MTD_NAND_EMBEDDEDECC
 	bool "Support devices with Embedded ECC"
 	default n
diff --git a/nuttx/drivers/mtd/Make.defs b/nuttx/drivers/mtd/Make.defs
index 0595a57d5..61624e566 100644
--- a/nuttx/drivers/mtd/Make.defs
+++ b/nuttx/drivers/mtd/Make.defs
@@ -46,7 +46,7 @@ CSRCS += mtd_partition.c
 endif
 
 ifeq ($(CONFIG_MTD_NAND),y)
-CSRCS += mtd_onfi.c
+CSRCS += mtd_nand.c mtd_onfi.c
 endif
 
 ifeq ($(CONFIG_RAMMTD),y)
diff --git a/nuttx/drivers/mtd/mtd_nand.c b/nuttx/drivers/mtd/mtd_nand.c
new file mode 100755
index 000000000..45791d40e
--- /dev/null
+++ b/nuttx/drivers/mtd/mtd_nand.c
@@ -0,0 +1,187 @@
+/****************************************************************************
+ * arch/arm/src/sama5/sam_nand.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * References:
+ *   SAMA5D3 Series Data Sheet
+ *   Atmel NoOS sample code.
+ *
+ * The Atmel sample code has a BSD compatibile license that requires this
+ * copyright notice:
+ *
+ *   Copyright (c) 2011, 2012, Atmel Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the names NuttX nor Atmel nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/mtd/nand_config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include <errno.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/mtd/nand.h>
+#include <nuttx/mtd/onfi.h>
+#include <nuttx/mtd/nand_scheme.h>
+#include <nuttx/mtd/nand_model.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nand_initialize
+ *
+ * Description:
+ *   Probe and initialize NAND.
+ *
+ * Input parameters:
+ *   cmdaddr  - NAND command address base
+ *   addraddr - NAND address address base
+ *   dataaddr - NAND data address
+ *
+ * Returned value.
+ *   OK is returned on success; A negated errno value is returned on failure.
+ *
+ ****************************************************************************/
+
+int nand_initialize(uintptr_t cmdaddr, uintptr_t addraddr, uintptr_t dataaddr)
+{
+  struct onfi_pgparam_s onfi;
+  struct nand_model_s model;
+  bool compatible;
+  int ret;
+
+  fvdbg("cmdaddr=%p addraddr=%p dataaddr=%p\n",
+        (FAR void *)cmdaddr, (FAR void *)addraddr, (FAR void *)dataaddr);
+
+  /* Check if there is NAND connected on the EBI */
+
+  if (!onfi_ebidetect(cmdaddr, addraddr, dataaddr))
+    {
+      fdbg("ERROR: No NAND device detected at: %p %p %p\n",
+           (FAR void *)cmdaddr, (FAR void *)addraddr, (FAR void *)dataaddr);
+      return -ENODEV;
+    }
+
+  /* Read the ONFI page parameters from the NAND device */
+
+  ret = onfi_read(cmdaddr, addraddr, dataaddr, &onfi);
+  if (ret < 0)
+    {
+      fvdbg("ERROR: Failed to get ONFI page parameters: %d\n", ret);
+      compatible = false;
+    }
+  else
+    {
+      uint64_t size;
+
+      fvdbg("Found ONFI compliant NAND FLASH\n");
+      compatible = true;
+
+      /* Construct the NAND model structure */
+
+      model.devid     = onfi.manufacturer;
+      model.options   = onfi.buswidth ? NANDMODEL_DATAWIDTH16 : NANDMODEL_DATAWIDTH8;
+      model.pagesize  = onfi.pagesize;
+      model.sparesize = onfi.sparesize;
+
+      size                  = (uint64_t)onfi.pagesperblock *
+                              (uint64_t)onfi.blocksperlun *
+                              (uint64_t)onfi.pagesize;
+      DEBUGASSERT(size < (uint64_t)(1 << 21));
+
+      model.devsize   = (uint16_t)(size >> 20);
+
+      size                  = (uint64_t)onfi.pagesperblock *
+                              (uint64_t)onfi.pagesize;
+      DEBUGASSERT(size < (uint64_t)(1 << 11));
+
+      model.blocksize = (uint16_t)(size >> 10);
+
+      switch (onfi.pagesize)
+        {
+          case 256:
+            model.scheme = &g_nand_sparescheme256;
+            break;
+
+          case 512:
+            model.scheme = &g_nand_sparescheme512;
+            break;
+
+          case 2048:
+            model.scheme = &g_nand_sparescheme2048;
+            break;
+
+          case 4096:
+            model.scheme = &g_nand_sparescheme4096;
+            break;
+        }
+
+      /* Disable any internal, embedded ECC function */
+
+      (void)onfi_embeddedecc(&onfi, cmdaddr, addraddr, dataaddr, false);
+    }
+
+#warning Missing logic
+
+  /* Return the implementation-specific state structure as the MTD device */
+
+  return OK;
+}
diff --git a/nuttx/drivers/mtd/mtd_onfi.c b/nuttx/drivers/mtd/mtd_onfi.c
index 872f9a866..58cf30e6b 100644
--- a/nuttx/drivers/mtd/mtd_onfi.c
+++ b/nuttx/drivers/mtd/mtd_onfi.c
@@ -49,6 +49,7 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
+#include <nuttx/mtd/nand_config.h>
 
 #include <sys/types.h>
 
@@ -59,7 +60,6 @@
 #include <assert.h>
 #include <debug.h>
 
-#include <nuttx/kmalloc.h>
 #include <nuttx/mtd/nand_model.h>
 #include <nuttx/mtd/onfi.h>
 
@@ -89,20 +89,20 @@
 #define EBICSA_NAND_D0_ON_D16    (1 << 24)
 
  /* Misc. definitions */
- 
+
 #define MAX_READ_STATUS_COUNT    100000 /* Read status timeout */
 #define ONFI_PARAM_TABLE_SIZE    116    /* Not all 256 bytes are useful */
 
 /* NAND access macros */
 
-#define WRITE_NAND_COMMAND(d,a,c) \
+#define WRITE_NAND_COMMAND(d,c) \
   do { \
-    *(volatile uint8_t *)((uintptr_t)(a) | (uintptr_t)(c)) = (uint8_t)(d); \
+    *(volatile uint8_t *)((uintptr_t)(c)) = (uint8_t)(d); \
   } while (0)
 
-#define WRITE_NAND_ADDRESS(d,a,b) \
+#define WRITE_NAND_ADDRESS(d,b) \
   do { \
-    *(volatile uint8_t *)((uintptr_t)(a) | (uintptr_t)(b)) = (uint8_t)(d); \
+    *(volatile uint8_t *)((uintptr_t)(b)) = (uint8_t)(d); \
   } while (0)
 
 #define READ_NAND(a) \
@@ -117,24 +117,6 @@
  * Private Types
  ****************************************************************************/
 
-/* Describes memory organization block information in ONFI parameter page*/
-
-struct onfi_pgparam_s
-{   
-  uint8_t manufacturer;   /* JEDEC manufacturer ID */
-  uint8_t buswidth;       /* Bus width */
-  uint8_t luns;           /* Number of logical units */
-  uint8_t eccsize;        /* Number of bits of ECC correction */
-  uint8_t model;          /* Device model */
-  uint16_t sparesize;     /* Number of spare bytes per page */
-  uint16_t pagesperblock; /* Number of pages per block */
-  uint16_t blocksperlun;  /* Number of blocks per logical unit (LUN) */
-  uint32_t pagesize;      /* Number of data bytes per page */
-  uintptr_t cmdaddr;      /* Base address for NAND commands */
-  uintptr_t addraddr;     /* Base address for NAND addresses */
-  uintptr_t dataaddr;     /* NAND data address */
-};
-
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -167,7 +149,7 @@ static int onfi_readstatus(uintptr_t cmdaddr, uintptr_t dataaddr)
 
   /* Issue command */
 
-  WRITE_NAND_COMMAND(NAND_CMD_STATUS, dataaddr, cmdaddr);
+  WRITE_NAND_COMMAND(NAND_CMD_STATUS, cmdaddr);
   timeout = 0;
 
   while (timeout < MAX_READ_STATUS_COUNT)
@@ -205,7 +187,7 @@ static int onfi_readstatus(uintptr_t cmdaddr, uintptr_t dataaddr)
  *   This function check if the Nandflash has an embedded ECC controller.
  *
  * Input Parameters:
- *   handle - An ONFI handle previously created by onfi_create().
+ *   onfi  - An initialized ONFI data structure.
  *
  * Returned Value:
  *   True  - Internal ECC supported
@@ -258,8 +240,8 @@ bool onfi_compatible(uintptr_t cmdaddr, uintptr_t addraddr,
 
   /* Check if the Nandflash is ONFI compliant */
 
-  WRITE_NAND_COMMAND(NAND_CMD_READID, dataaddr, cmdaddr);
-  WRITE_NAND_ADDRESS(0x20, dataaddr, addraddr);
+  WRITE_NAND_COMMAND(NAND_CMD_READID, cmdaddr);
+  WRITE_NAND_ADDRESS(0x20, addraddr);
 
   parmtab[0] = READ_NAND(dataaddr);
   parmtab[1] = READ_NAND(dataaddr);
@@ -272,29 +254,28 @@ bool onfi_compatible(uintptr_t cmdaddr, uintptr_t addraddr,
 }
 
 /****************************************************************************
- * Name: onfi_create
+ * Name: onfi_read
  *
  * Description:
- *   If the addresses refer to a compatible ONFI device, then create the
- *   ONFI handle that can be used to interact with the device.
+ *   If the addresses refer to a compatible ONFI device, then read the ONFI
+ *   parameters from the FLASH into the user provided data staructure.
  *
  * Input Parameters:
  *   cmdaddr  - NAND command address base
  *   addraddr - NAND address address base
  *   dataaddr - NAND data address
+ *   onfi     - The ONFI data structure to populate.
  *
  * Returned Value:
- *   On success, a non-NULL ONFI handle is returned.  This handle must be
- *   freed by calling onfi_destroy with it is no longer needed.
- *   NULL is returned on any failure.  Failures include such things as
- *   memory allocation failures, ONFI incompatibility, timeouts, etc.
+ *   OK is returned on success and the the ONFI data structure is initialized
+ *   with NAND data.  A negated errno value is returned in the event of an
+ *   error.
  *
  ****************************************************************************/
 
-ONFI_HANDLE *onfi_create(uintptr_t cmdaddr, uintptr_t addraddr,
-                         uintptr_t dataaddr)
+int onfi_read(uintptr_t cmdaddr, uintptr_t addraddr, uintptr_t dataaddr,
+              FAR struct onfi_pgparam_s *onfi)
 {
-  FAR struct onfi_pgparam_s *onfi;
   uint8_t parmtab[ONFI_PARAM_TABLE_SIZE];
   int i;
 
@@ -303,126 +284,95 @@ ONFI_HANDLE *onfi_create(uintptr_t cmdaddr, uintptr_t addraddr,
 
   if (onfi_compatible(cmdaddr, addraddr, dataaddr))
     {
-      /* Allocate the ONFI structure */
-
-      onfi = (FAR struct onfi_pgparam_s *)kzalloc(sizeof(struct onfi_pgparam_s));
-      if (!onfi)
-        {
-          fdbg("ERROR: Failed to allocate ONFI structure\n");
-          return (ONFI_HANDLE)NULL;
-        }
-
-      /* Save the NAND base addresses */
- 
-      onfi->cmdaddr  = cmdaddr;
-      onfi->addraddr = addraddr;
-      onfi->dataaddr = dataaddr;
-
-      /* Initialize the ONFI parameter table */
+      fdbg("ERROR: No ONFI compatible device detected\n");
+      return -ENODEV;
+    }
 
-      memset(parmtab, 0xff, ONFI_PARAM_TABLE_SIZE);
+  /* Initialize the ONFI parameter table */
 
-      /* Perform Read Parameter Page command */
+  memset(parmtab, 0xff, ONFI_PARAM_TABLE_SIZE);
 
-      WRITE_NAND_COMMAND(NAND_CMD_READ_PARAM_PAGE, dataaddr, cmdaddr);
-      WRITE_NAND_ADDRESS(0x0, dataaddr, addraddr);
+  /* Perform Read Parameter Page command */
 
-      /* Wait NF ready */
+  WRITE_NAND_COMMAND(NAND_CMD_READ_PARAM_PAGE, cmdaddr);
+  WRITE_NAND_ADDRESS(0x0, addraddr);
 
-      onfi_readstatus(cmdaddr, dataaddr);
+  /* Wait NF ready */
 
-      /* Re-enable data output mode required after Read Status command */
+  onfi_readstatus(cmdaddr, dataaddr);
 
-      WRITE_NAND_COMMAND(NAND_CMD_READ0, dataaddr, cmdaddr);
+  /* Re-enable data output mode required after Read Status command */
 
-      /* Read the parameter table */
+  WRITE_NAND_COMMAND(NAND_CMD_READ0, cmdaddr);
 
-      for (i = 0; i < ONFI_PARAM_TABLE_SIZE; i++)
-        {
-          parmtab[i] = READ_NAND(dataaddr);
-        }
+  /* Read the parameter table */
 
-      for (i = 0; i < ONFI_PARAM_TABLE_SIZE; i++)
-        {
-          if (parmtab[i] != 0xff)
-            {
-              break;
-            }
-        }
+  for (i = 0; i < ONFI_PARAM_TABLE_SIZE; i++)
+    {
+      parmtab[i] = READ_NAND(dataaddr);
+    }
 
-      if (i == ONFI_PARAM_TABLE_SIZE)
+  for (i = 0; i < ONFI_PARAM_TABLE_SIZE; i++)
+    {
+      if (parmtab[i] != 0xff)
         {
-          kfree(onfi);
-          return (ONFI_HANDLE)NULL;
+          break;
         }
-        
-      /* JEDEC manufacturer ID */
-
-      onfi->manufacturer = *(uint8_t *)(parmtab + 64);
-      fvdbg("ONFI manufacturer %x \n\r", onfi->manufacturer);
+    }
 
-      /* Bus width */
+  if (i == ONFI_PARAM_TABLE_SIZE)
+    {
+      fdbg("ERROR: Failed to read ONFI parameter table\n");
+      return -EIO;
+   }
 
-      onfi->buswidth = (*(uint8_t *)(parmtab + 6)) & 0x01;
+  /* JEDEC manufacturer ID */
 
-      /* Get number of data bytes per page (bytes 80-83 in the param table) */
+  onfi->manufacturer = *(uint8_t *)(parmtab + 64);
 
-      onfi->pagesize =  *(uint32_t *)(void*)(parmtab + 80);
-      fvdbg("ONFI pagesize %x \n\r", (unsigned int)onfi->pagesize);
+  /* Bus width */
 
-      /* Get number of spare bytes per page (bytes 84-85 in the param table) */
+  onfi->buswidth = (*(uint8_t *)(parmtab + 6)) & 0x01;
 
-      onfi->sparesize =  *(uint16_t *)(void*)(parmtab + 84);
-      fvdbg("ONFI sparesize %x \n\r", (unsigned int)onfi->sparesize);
+  /* Get number of data bytes per page (bytes 80-83 in the param table) */
 
-      /* Number of pages per block. */
+  onfi->pagesize =  *(uint32_t *)(void*)(parmtab + 80);
 
-      onfi->pagesperblock = *(uint32_t *)(void*)(parmtab + 92);
+  /* Get number of spare bytes per page (bytes 84-85 in the param table) */
 
-      /* Number of blocks per logical unit (LUN). */
+  onfi->sparesize =  *(uint16_t *)(void*)(parmtab + 84);
 
-      onfi->blocksperlun = *(uint32_t *)(void*)(parmtab + 96);
+  /* Number of pages per block. */
 
-      /* Number of logical units. */
+  onfi->pagesperblock = *(uint32_t *)(void*)(parmtab + 92);
 
-      onfi->luns = *(uint8_t *)(parmtab + 100);
+  /* Number of blocks per logical unit (LUN). */
 
-      /* Number of bits of ECC correction */
+  onfi->blocksperlun = *(uint32_t *)(void*)(parmtab + 96);
 
-      onfi->eccsize = *(uint8_t *)(parmtab + 112);
-      fvdbg("ONFI eccsize %x \n\r", onfi->eccsize);
+  /* Number of logical units. */
 
-      /* Device model */
+  onfi->luns = *(uint8_t *)(parmtab + 100);
 
-      onfi->model= *(uint8_t *)(parmtab + 49);
+  /* Number of bits of ECC correction */
 
-      fvdbg("Returning %p\n", onfi);
-      return (ONFI_HANDLE)onfi;
-    }
+  onfi->eccsize = *(uint8_t *)(parmtab + 112);
 
-  return (ONFI_HANDLE)NULL;
-}
+  /* Device model */
 
-/****************************************************************************
- * Name: onfi_destroy
- *
- * Description:
- *   Free resources allocated on onfi_create() when the ONFI handle was
- *   created.  Upon return, the ONFI handle is no longer valid and should not
- *   be used further.
- *
- * Input Parameters:
- *   handle - An ONFI handle previously created by onfi_create().
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
+  onfi->model= *(uint8_t *)(parmtab + 49);
 
-void onfi_destroy(ONFI_HANDLE handle)
-{
-  DEBUGASSERT(handle);
-  kfree(handle);
+  fvdbg("Returning:\n");
+  fvdbg("  manufacturer:  0x%02x\n", onfi->manufacturer);
+  fvdbg("  buswidth:      %d\n",     onfi->buswidth);
+  fvdbg("  luns:          %d\n",     onfi->luns);
+  fvdbg("  eccsize:       %d\n",     onfi->eccsize);
+  fvdbg("  model:         0x%02s\n", onfi->model);
+  fvdbg("  sparesize:     %d\n",     onfi->sparesize);
+  fvdbg("  pagesperblock: %d\n",     onfi->pagesperblock);
+  fvdbg("  blocksperlun:  %d\n",     onfi->blocksperlun);
+  fvdbg("  pagesize:      %d\n",     onfi->pagesize);
+  return OK;
 }
 
 /****************************************************************************
@@ -432,7 +382,10 @@ void onfi_destroy(ONFI_HANDLE handle)
  *   Enable or disable the NAND's embedded ECC controller.
  *
  * Input Parameters:
- *   handle - An ONFI handle previously created by onfi_create().
+ *   onfi     - An initialized ONFI data structure.
+ *   cmdaddr  - NAND command address base
+ *   addraddr - NAND address address base
+ *   dataaddr - NAND data address
  *   enable - True: enabled the embedded ECC function; False: disable it
  *
  * Returned Value:
@@ -442,11 +395,10 @@ void onfi_destroy(ONFI_HANDLE handle)
  ****************************************************************************/
 
 #ifdef CONFIG_MTD_NAND_EMBEDDEDECC
-bool onfi_embeddedecc(ONFI_HANDLE handle, bool enable)
+bool onfi_embeddedecc(FAR const struct onfi_pgparam_s *onfi,
+                      uintptr_t cmdaddr, uintptr_t addraddr,
+                      uintptr_t dataaddr, bool enable)
 {
-  FAR struct onfi_pgparam_s *onfi = (FAR struct onfi_pgparam_s *)handle;
-  DEBUGASSERT(onfi);
-
   /* Does the NAND supported the embedded ECC function? */
 
   if (onfi_have_embeddedecc(onfi))
@@ -454,27 +406,27 @@ bool onfi_embeddedecc(ONFI_HANDLE handle, bool enable)
       /* Yes... enable or disable it */
       /* Perform common setup */
 
-      WRITE_NAND_COMMAND(NAND_CMD_SET_FEATURE, onfi->dataaddr, onfi->cmdaddr);
-      WRITE_NAND_ADDRESS(0x90, onfi->dataaddr, onfi->addraddr);
+      WRITE_NAND_COMMAND(NAND_CMD_SET_FEATURE, cmdaddr);
+      WRITE_NAND_ADDRESS(0x90, addraddr);
 
       if (enable)
         {
           /* Activate the internal ECC controller */
 
-          WRITE_NAND(0x08, onfi->dataaddr);
-          WRITE_NAND(0x00, onfi->dataaddr);
-          WRITE_NAND(0x00, onfi->dataaddr);
-          WRITE_NAND(0x00, onfi->dataaddr);
+          WRITE_NAND(0x08, dataaddr);
+          WRITE_NAND(0x00, dataaddr);
+          WRITE_NAND(0x00, dataaddr);
+          WRITE_NAND(0x00, dataaddr);
           setSmcOpEccType(SMC_ECC_INTERNAL);
         }
       else
         {
           /* De-activate the internal ECC controller */
 
-          WRITE_NAND(0x00, onfi->dataaddr);
-          WRITE_NAND(0x00, onfi->dataaddr);
-          WRITE_NAND(0x00, onfi->dataaddr);
-          WRITE_NAND(0x00, onfi->dataaddr);
+          WRITE_NAND(0x00, dataaddr);
+          WRITE_NAND(0x00, dataaddr);
+          WRITE_NAND(0x00, dataaddr);
+          WRITE_NAND(0x00, dataaddr);
         }
 
       return true;
@@ -514,7 +466,7 @@ bool onfi_ebidetect(uintptr_t cmdaddr, uintptr_t addraddr,
 
   /* Send Reset command */
 
-  WRITE_NAND_COMMAND(NAND_CMD_RESET, dataaddr, cmdaddr);
+  WRITE_NAND_COMMAND(NAND_CMD_RESET, cmdaddr);
 
   /* If a Nandflash is connected, it should answer to a read status command */
 
@@ -523,8 +475,8 @@ bool onfi_ebidetect(uintptr_t cmdaddr, uintptr_t addraddr,
       rc = onfi_readstatus(cmdaddr, dataaddr);
       if (rc == OK)
         {
-          WRITE_NAND_COMMAND(NAND_CMD_READID, dataaddr, cmdaddr);
-          WRITE_NAND_ADDRESS(0, dataaddr, addraddr);
+          WRITE_NAND_COMMAND(NAND_CMD_READID, cmdaddr);
+          WRITE_NAND_ADDRESS(0, addraddr);
 
           ids[0] = READ_NAND(dataaddr);
           ids[1] = READ_NAND(dataaddr);