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author | Gregory Nutt <gnutt@nuttx.org> | 2013-04-25 12:24:11 -0600 |
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committer | Gregory Nutt <gnutt@nuttx.org> | 2013-04-25 12:24:11 -0600 |
commit | 5f6e91b0ed1b373d0b4f963b0e0f8f7fe05ec766 (patch) | |
tree | 994790bec80a7d83a625ce43a1908bb06483da81 /nuttx | |
parent | fab85cb20588413d8e82b1af461165d188e86677 (diff) | |
download | px4-nuttx-5f6e91b0ed1b373d0b4f963b0e0f8f7fe05ec766.tar.gz px4-nuttx-5f6e91b0ed1b373d0b4f963b0e0f8f7fe05ec766.tar.bz2 px4-nuttx-5f6e91b0ed1b373d0b4f963b0e0f8f7fe05ec766.zip |
KL15Z: Fix GPIO base addresses; remove GCR header file
Diffstat (limited to 'nuttx')
-rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_gcr.h | 373 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_gpio.h | 250 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/chip/kl_memorymap.h | 4 | ||||
-rw-r--r-- | nuttx/arch/arm/src/kl/kl_timerisr.c | 1 |
4 files changed, 125 insertions, 503 deletions
diff --git a/nuttx/arch/arm/src/kl/chip/kl_gcr.h b/nuttx/arch/arm/src/kl/chip/kl_gcr.h deleted file mode 100644 index f03f9f096..000000000 --- a/nuttx/arch/arm/src/kl/chip/kl_gcr.h +++ /dev/null @@ -1,373 +0,0 @@ -/******************************************************************************************** - * arch/arm/src/nuc1xx/chip/nuc_gcr.h - * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt <gnutt@nuttx.org> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ********************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_GCR_H -#define __ARCH_ARM_SRC_KL_CHIP_KL_GCR_H - -/******************************************************************************************** - * Included Files - ********************************************************************************************/ - -#include <nuttx/config.h> - -#include "chip.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ -/* Register offsets *************************************************************************/ - -#define KL_GCR_PDID_OFFSET 0x0000 /* Part didentification number register */ -#define KL_GCR_RSTSRC_OFFSET 0x0004 /* System reset source register */ -#define KL_GCR_IPRSTC1_OFFSET 0x0008 /* IP Reset control register 1 */ -#define KL_GCR_IPRSTC2_OFFSET 0x000c /* IP Reset control register 2 */ -#define KL_GCR_CPR_OFFSET 0x0010 /* Chip performance register */ -#define KL_GCR_BODCR_OFFSET 0x0018 /* Brown-out detector control register */ -#define KL_GCR_TEMPCR_OFFSET 0x001c /* Temperature sensor control register */ -#define KL_GCR_PORCR_OFFSET 0x0024 /* Power-on-reset control register */ -#define KL_GCR_GPA_MFP_OFFSET 0x0030 /* Multiple function pin GPIOA control register */ -#define KL_GCR_GPB_MFP_OFFSET 0x0034 /* Multiple function pin GPIOB control register */ -#define KL_GCR_GPC_MFP_OFFSET 0x0038 /* Multiple function pin GPIOC control register */ -#define KL_GCR_GPD_MFP_OFFSET 0x003C /* Multiple function pin GPIOD control register */ -#define KL_GCR_GPE_MFP_OFFSET 0x0040 /* Multiple function pin GPIOE control register */ -#define KL_GCR_ALT_MFP_OFFSET 0x0050 /* Alternative multiple function pin control register */ -#define KL_GCR_REGWRPROT_OFFSET 0x0100 /* Register write-protection control register */ - -/* Register addresses ***********************************************************************/ - -#define KL_GCR_PDID (KL_GCR_BASE+KL_GCR_PDID_OFFSET) -#define KL_GCR_RSTSRC (KL_GCR_BASE+KL_GCR_RSTSRC_OFFSET) -#define KL_GCR_IPRSTC1 (KL_GCR_BASE+KL_GCR_IPRSTC1_OFFSET) -#define KL_GCR_IPRSTC2 (KL_GCR_BASE+KL_GCR_IPRSTC2_OFFSET) -#define KL_GCR_CPR (KL_GCR_BASE+KL_GCR_CPR_OFFSET) -#define KL_GCR_BODCR (KL_GCR_BASE+KL_GCR_BODCR_OFFSET) -#define KL_GCR_TEMPCR (KL_GCR_BASE+KL_GCR_TEMPCR_OFFSET) -#define KL_GCR_PORCR (KL_GCR_BASE+KL_GCR_PORCR_OFFSET) -#define KL_GCR_GPA_MFP (KL_GCR_BASE+KL_GCR_GPA_MFP_OFFSET) -#define KL_GCR_GPB_MFP (KL_GCR_BASE+KL_GCR_GPB_MFP_OFFSET) -#define KL_GCR_GPC_MFP (KL_GCR_BASE+KL_GCR_GPC_MFP_OFFSET) -#define KL_GCR_GPD_MFP (KL_GCR_BASE+KL_GCR_GPD_MFP_OFFSET) -#define KL_GCR_GPE_MFP (KL_GCR_BASE+KL_GCR_GPE_MFP_OFFSET) -#define KL_GCR_ALT_MFP (KL_GCR_BASE+KL_GCR_ALT_MFP_OFFSET) -#define KL_GCR_REGWRPROT (KL_GCR_BASE+KL_GCR_REGWRPROT_OFFSET) - -/* Register bit-field definitions ***********************************************************/ - -/* Part didentification number register (32-bit part ID number) */ - -/* System reset source register */ - -#define GCR_RSTSRC_POR (1 << 0) /* Bit 0: Power-on reset (POR) or chip reset (CHIP_RST) */ -#define GCR_RSTSRC_RESET (1 << 1) /* Bit 1: /RESET pin */ -#define GCR_RSTSRC_WDT (1 << 2) /* Bit 2: Watchdog timer */ -#define GCR_RSTSRC_LVR (1 << 3) /* Bit 3: Low voltage reset controller */ -#define GCR_RSTSRC_BOD (1 << 4) /* Bit 4: Brown-out detection */ -#define GCR_RSTSRC_SYS (1 << 5) /* Bit 5: Software set AIRCR:SYSRESETREQ */ -#define GCR_RSTSRC_CPU (1 << 7) /* Bit 7: Sofware set CPU_RST */ - -/* IP Reset control register 1 */ - -#define GCR_IPRSTC1_CHIP_RST (1 << 0) /* Bit 0: Chip one-shot reset */ -#define GCR_IPRSTC1_CPU_RST (1 << 1) /* Bit 1: CPU kernel one-shot reset */ -#define GCR_IPRSTC1_PDMA_RST (1 << 2) /* Bit 2: PDMA controller reset */ -#define GCR_IPRSTC1_EBI_RST (1 << 3) /* Bit 3: EBI controller reset */ - -/* IP Reset control register 2 */ - -#define GCR_IPRSTC2_GPIO_RST (1 << 1) /* Bit 1: GPIO controller reset */ -#define GCR_IPRSTC2_TMR0_RST (1 << 2) /* Bit 2: Timer0 controller reset */ -#define GCR_IPRSTC2_TMR1_RST (1 << 3) /* Bit 3: Timer1 controller reset */ -#define GCR_IPRSTC2_TMR2_RST (1 << 4) /* Bit 4: Timer2 controller reset */ -#define GCR_IPRSTC2_TMR3_RST (1 << 5) /* Bit 5: Timer3 controller reset */ -#define GCR_IPRSTC2_I2C0_RST (1 << 8) /* Bit 8: I2C0 controller reset */ -#define GCR_IPRSTC2_I2C1_RST (1 << 9) /* Bit 9: I2C1 controller reset */ -#define GCR_IPRSTC2_SPI0_RST (1 << 12) /* Bit 12: SPI0 controller reset */ -#define GCR_IPRSTC2_SPI1_RST (1 << 13) /* Bit 13: SPI1 controller reset */ -#define GCR_IPRSTC2_SPI2_RST (1 << 14) /* Bit 14: SPI2 controller reset */ -#define GCR_IPRSTC2_SPI3_RST (1 << 15) /* Bit 15: SPI3 controller reset */ -#define GCR_IPRSTC2_UART0_RST (1 << 16) /* Bit 16: UART0 controller reset */ -#define GCR_IPRSTC2_UART1_RST (1 << 17) /* Bit 17: UART1 controller reset */ -#define GCR_IPRSTC2_UART2_RST (1 << 18) /* Bit 18: UART2 controller reset */ -#define GCR_IPRSTC2_PWM03_RST (1 << 20) /* Bit 20: PWM0/1/2/3 controller reset */ -#define GCR_IPRSTC2_PWM47_RST (1 << 21) /* Bit 21: PWM4/5/6/7 controller reset */ -#define GCR_IPRSTC2_ACMP_RST (1 << 22) /* Bit 22: Analog comparator controller reset */ -#define GCR_IPRSTC2_PS2_RST (1 << 23) /* Bit 23: PS/2 controller reset */ -#define GCR_IPRSTC2_USBD_RST (1 << 27) /* Bit 27: USB device controller reset */ -#define GCR_IPRSTC2_ADC_RST (1 << 28) /* Bit 28: ADC controller reset */ -#define GCR_IPRSTC2_I2S_RST (1 << 29) /* Bit 29: I2S controller reset */ - -/* Chip performance register */ - -#define GCR_CPR_HPE (1 << 0) /* Bit 0: High performance enable */ - -/* Brown-out detector control register */ - -#define GCR_BODCR_BOD_EN (1 << 0) /* Bit 0: Brown-ut detector enable */ -#define GCR_BODCR_BOD_VL_SHIFT (1) /* Bits 1-2: Brown-out detector threshold voltage selection */ -#define GCR_BODCR_BOD_VL_MASK (3 << GCR_BODCR_BOD_VL_SHIFT) -# define GCR_BODCR_BOD_VL_2p2V (0 << GCR_BODCR_BOD_VL_SHIFT) /* 2.2V */ -# define GCR_BODCR_BOD_VL_2p7V (1 << GCR_BODCR_BOD_VL_SHIFT) /* 2.7V */ -# define GCR_BODCR_BOD_VL_3p8V (2 << GCR_BODCR_BOD_VL_SHIFT) /* 3.8V */ -# define GCR_BODCR_BOD_VL_4p5V (3 << GCR_BODCR_BOD_VL_SHIFT) /* 4.5V */ -#define GCR_BODCR_BOD_RSTEN (1 << 3) /* Bit 3: Brown-out reset enable */ -#define GCR_BODCR_BOD_INTF (1 << 4) /* Bit 4: Brown-out deletector interrupt flag */ -#define GCR_BODCR_BOD_LPM (1 << 5) /* Bit 5: Brown-out detector low power mode */ -#define GCR_BODCR_BOD_OUT (1 << 6) /* Bit 6: Brown-out detector output status */ -#define GCR_BODCR_LVR_EN (1 << 7) /* Bit 7: Low voltaghe reset enable */ - -/* Temperature sensor control register */ - -#define GCR_TEMPCR_VTEMP_EN (1 << 0) /* Bit 0: Temperature sensor enable */ - -/* Power-on-reset control register */ - -#define GCR_PORCR_MASK (0xffff) /* Bits 9-15: POR disable code */ - -/* Multiple function pin GPIOA control register */ - -#define GCR_GPA_MFP(n) (1 << (n)) /* Bits 0-15: PAn pin function selection */ -# define GCR_GPA_MFP0 (1 << 0) -# define GCR_GPA_MFP1 (1 << 1) -# define GCR_GPA_MFP2 (1 << 2) -# define GCR_GPA_MFP3 (1 << 3) -# define GCR_GPA_MFP4 (1 << 4) -# define GCR_GPA_MFP5 (1 << 5) -# define GCR_GPA_MFP6 (1 << 6) -# define GCR_GPA_MFP7 (1 << 7) -# define GCR_GPA_MFP8 (1 << 8) -# define GCR_GPA_MFP9 (1 << 9) -# define GCR_GPA_MFP10 (1 << 10) -# define GCR_GPA_MFP11 (1 << 11) -# define GCR_GPA_MFP12 (1 << 12) -# define GCR_GPA_MFP13 (1 << 13) -# define GCR_GPA_MFP14 (1 << 14) -# define GCR_GPA_MFP15 (1 << 15) -#define GCR_GPA_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPA_TYPE0 (1 << 0) -# define GCR_GPA_TYPE1 (1 << 1) -# define GCR_GPA_TYPE2 (1 << 2) -# define GCR_GPA_TYPE3 (1 << 3) -# define GCR_GPA_TYPE4 (1 << 4) -# define GCR_GPA_TYPE5 (1 << 5) -# define GCR_GPA_TYPE6 (1 << 6) -# define GCR_GPA_TYPE7 (1 << 7) -# define GCR_GPA_TYPE8 (1 << 8) -# define GCR_GPA_TYPE9 (1 << 9) -# define GCR_GPA_TYPE10 (1 << 10) -# define GCR_GPA_TYPE11 (1 << 11) -# define GCR_GPA_TYPE12 (1 << 12) -# define GCR_GPA_TYPE13 (1 << 13) -# define GCR_GPA_TYPE14 (1 << 14) -# define GCR_GPA_TYPE15 (1 << 15) - -/* Multiple function pin GPIOB control register */ - -#define GCR_GPB_MFP(n) (1 << (n)) /* Bits 0-15: PBn pin function selection */ -# define GCR_GPB_MFP0 (1 << 0) -# define GCR_GPB_MFP1 (1 << 1) -# define GCR_GPB_MFP2 (1 << 2) -# define GCR_GPB_MFP3 (1 << 3) -# define GCR_GPB_MFP4 (1 << 4) -# define GCR_GPB_MFP5 (1 << 5) -# define GCR_GPB_MFP6 (1 << 6) -# define GCR_GPB_MFP7 (1 << 7) -# define GCR_GPB_MFP8 (1 << 8) -# define GCR_GPB_MFP9 (1 << 9) -# define GCR_GPB_MFP10 (1 << 10) -# define GCR_GPB_MFP11 (1 << 11) -# define GCR_GPB_MFP12 (1 << 12) -# define GCR_GPB_MFP13 (1 << 13) -# define GCR_GPB_MFP14 (1 << 14) -# define GCR_GPB_MFP15 (1 << 15) -#define GCR_GPB_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPB_TYPE0 (1 << 0) -# define GCR_GPB_TYPE1 (1 << 1) -# define GCR_GPB_TYPE2 (1 << 2) -# define GCR_GPB_TYPE3 (1 << 3) -# define GCR_GPB_TYPE4 (1 << 4) -# define GCR_GPB_TYPE5 (1 << 5) -# define GCR_GPB_TYPE6 (1 << 6) -# define GCR_GPB_TYPE7 (1 << 7) -# define GCR_GPB_TYPE8 (1 << 8) -# define GCR_GPB_TYPE9 (1 << 9) -# define GCR_GPB_TYPE10 (1 << 10) -# define GCR_GPB_TYPE11 (1 << 11) -# define GCR_GPB_TYPE12 (1 << 12) -# define GCR_GPB_TYPE13 (1 << 13) -# define GCR_GPB_TYPE14 (1 << 14) -# define GCR_GPB_TYPE15 (1 << 15) - -/* Multiple function pin GPIOC control register */ - -#define GCR_GPC_MFP(n) (1 << (n)) /* Bits 0-15: PCn pin function selection */ -# define GCR_GPC_MFP0 (1 << 0) -# define GCR_GPC_MFP1 (1 << 1) -# define GCR_GPC_MFP2 (1 << 2) -# define GCR_GPC_MFP3 (1 << 3) -# define GCR_GPC_MFP4 (1 << 4) -# define GCR_GPC_MFP5 (1 << 5) -# define GCR_GPC_MFP6 (1 << 6) -# define GCR_GPC_MFP7 (1 << 7) -# define GCR_GPC_MFP8 (1 << 8) -# define GCR_GPC_MFP9 (1 << 9) -# define GCR_GPC_MFP10 (1 << 10) -# define GCR_GPC_MFP11 (1 << 11) -# define GCR_GPC_MFP12 (1 << 12) -# define GCR_GPC_MFP13 (1 << 13) -# define GCR_GPC_MFP14 (1 << 14) -# define GCR_GPC_MFP15 (1 << 15) -#define GCR_GPC_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPC_TYPE0 (1 << 0) -# define GCR_GPC_TYPE1 (1 << 1) -# define GCR_GPC_TYPE2 (1 << 2) -# define GCR_GPC_TYPE3 (1 << 3) -# define GCR_GPC_TYPE4 (1 << 4) -# define GCR_GPC_TYPE5 (1 << 5) -# define GCR_GPC_TYPE6 (1 << 6) -# define GCR_GPC_TYPE7 (1 << 7) -# define GCR_GPC_TYPE8 (1 << 8) -# define GCR_GPC_TYPE9 (1 << 9) -# define GCR_GPC_TYPE10 (1 << 10) -# define GCR_GPC_TYPE11 (1 << 11) -# define GCR_GPC_TYPE12 (1 << 12) -# define GCR_GPC_TYPE13 (1 << 13) -# define GCR_GPC_TYPE14 (1 << 14) -# define GCR_GPC_TYPE15 (1 << 15) - -/* Multiple function pin GPIOD control register */ - -#define GCR_GPD_MFP(n) (1 << (n)) /* Bits 0-15: PDn pin function selection */ -# define GCR_GPD_MFP0 (1 << 0) -# define GCR_GPD_MFP1 (1 << 1) -# define GCR_GPD_MFP2 (1 << 2) -# define GCR_GPD_MFP3 (1 << 3) -# define GCR_GPD_MFP4 (1 << 4) -# define GCR_GPD_MFP5 (1 << 5) -# define GCR_GPD_MFP6 (1 << 6) -# define GCR_GPD_MFP7 (1 << 7) -# define GCR_GPD_MFP8 (1 << 8) -# define GCR_GPD_MFP9 (1 << 9) -# define GCR_GPD_MFP10 (1 << 10) -# define GCR_GPD_MFP11 (1 << 11) -# define GCR_GPD_MFP12 (1 << 12) -# define GCR_GPD_MFP13 (1 << 13) -# define GCR_GPD_MFP14 (1 << 14) -# define GCR_GPD_MFP15 (1 << 15) -#define GCR_GPD_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPD_TYPE0 (1 << 0) -# define GCR_GPD_TYPE1 (1 << 1) -# define GCR_GPD_TYPE2 (1 << 2) -# define GCR_GPD_TYPE3 (1 << 3) -# define GCR_GPD_TYPE4 (1 << 4) -# define GCR_GPD_TYPE5 (1 << 5) -# define GCR_GPD_TYPE6 (1 << 6) -# define GCR_GPD_TYPE7 (1 << 7) -# define GCR_GPD_TYPE8 (1 << 8) -# define GCR_GPD_TYPE9 (1 << 9) -# define GCR_GPD_TYPE10 (1 << 10) -# define GCR_GPD_TYPE11 (1 << 11) -# define GCR_GPD_TYPE12 (1 << 12) -# define GCR_GPD_TYPE13 (1 << 13) -# define GCR_GPD_TYPE14 (1 << 14) -# define GCR_GPD_TYPE15 (1 << 15) - -/* Multiple function pin GPIOE control register */ - -#define GCR_GPE_MFP(n) (1 << (n)) /* Bits 0-15: PDn pin function selection */ -# define GCR_GPE_MFP0 (1 << 0) -# define GCR_GPE_MFP1 (1 << 1) -# define GCR_GPE_MFP2 (1 << 2) -# define GCR_GPE_MFP3 (1 << 3) -# define GCR_GPE_MFP4 (1 << 4) -# define GCR_GPE_MFP5 (1 << 5) -#define GCR_GPE_TYPE(n) (1 << ((n)+16)) /* Bits 16-31: Enable Schmitt trigger function */ -# define GCR_GPE_TYPE0 (1 << 0) -# define GCR_GPE_TYPE1 (1 << 1) -# define GCR_GPE_TYPE2 (1 << 2) -# define GCR_GPE_TYPE3 (1 << 3) -# define GCR_GPE_TYPE4 (1 << 4) -# define GCR_GPE_TYPE5 (1 << 5) - -/* Alternative multiple function pin control register */ - -#define GCR_ALT_MFP_PB10_S01 (1 << 0) /* Bit 0: Determines PB.10 function */ -#define GCR_ALT_MFP_PB9_S11 (1 << 1) /* Bit 1: Determines PB.9 function */ -#define GCR_ALT_MFP_PA7_S21 (1 << 2) /* Bit 2: Determines PA.7 function */ -#define GCR_ALT_MFP_PB14_S31 (1 << 3) /* Bit 3: Determines PB.14 function */ -#define GCR_ALT_MFP_PB11_PWM4 (1 << 4) /* Bit 4: Determines PB.11 function */ -#define GCR_ALT_MFP_PC0_I2SRCLK (1 << 5) /* Bit 5: Determines PC.0 function */ -#define GCR_ALT_MFP_PC1_I2SBCLK (1 << 6) /* Bit 6: Determines PC.1 function */ -#define GCR_ALT_MFP_PC2_I2SD1 (1 << 7) /* Bit 7: Determines PC.2 function */ -#define GCR_ALT_MFP_PC3_I2SD0 (1 << 8) /* Bit 8: Determines PC.3 function */ -#define GCR_ALT_MFP_PA15_I2SMCLK (1 << 9) /* Bit 9: Determines PA.15 function */ -#define GCR_ALT_MFP_PB12_CLKO (1 << 10) /* Bit 10: Determines PB.12 function */ -#define GCR_ALT_MFP_EBI_EN (1 << 11) /* Bit 11: Determines PA.6, PA.7, PA.10, PA.11, - * PB.6, PB.7, PB.12, PB.13, PC.6, PC.7, PC.14, - * PC.15 function */ -#define GCR_ALT_MFP_EBI_MCLK_EN (1 << 12) /* Bit 12: Determines PC.8 function */ -#define GCR_ALT_MFP_EBI_NWRL_EN (1 << 13) /* Bit 13: Determines PB.2 function */ -#define GCR_ALT_MFP_EBI_NWRH_WN (1 << 14) /* Bit 14: Determines PB.3 function */ -#define GCR_ALT_MFP_EBI_HB_EN0 (1 << 16) /* Bit 16: Determines PA.5 function */ -#define GCR_ALT_MFP_EBI_HB_EN1 (1 << 17) /* Bit 17: Determines PA.4 function */ -#define GCR_ALT_MFP_EBI_HB_EN2 (1 << 18) /* Bit 18: Determines PA.3 function */ -#define GCR_ALT_MFP_EBI_HB_EN3 (1 << 19) /* Bit 19: Determines PA.2 function */ -#define GCR_ALT_MFP_EBI_HB_EN4 (1 << 20) /* Bit 20: Determines PA.1 function */ -#define GCR_ALT_MFP_EBI_HB_EN5 (1 << 21) /* Bit 21: Determines PA.12 function */ -#define GCR_ALT_MFP_EBI_HB_EN6 (1 << 22) /* Bit 22: Determines PA.13 function */ -#define GCR_ALT_MFP_EBI_HB_EN7 (1 << 23) /* Bit 23: Determines PA.14 function */ - -/* Register write-protection control register */ - - /* Write: */ -#define GCR_REGWRPROT_MASK (0xff) /* Bits 0-7: Register write protection code */ -# define GCR_REGWRPROT_1 (0x59) /* Disable sequence */ -# define GCR_REGWRPROT_2 (0x16) -# define GCR_REGWRPROT_3 (0x88) - /* Read: */ -#define GCR_REGWRPROT_DIS (1 << 0) /* Bit 0: Register write protectino disable index */ - -/******************************************************************************************** - * Public Types - ********************************************************************************************/ - -/******************************************************************************************** - * Public Data - ********************************************************************************************/ - -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_GCR_H */ diff --git a/nuttx/arch/arm/src/kl/chip/kl_gpio.h b/nuttx/arch/arm/src/kl/chip/kl_gpio.h index 8b6da17b6..64b1cad4b 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_gpio.h +++ b/nuttx/arch/arm/src/kl/chip/kl_gpio.h @@ -256,168 +256,168 @@ /* GPIO control registers */ -#define KL_GPIO_CTRL_BASE(n) (KL_GPIO_BASEOLD+KL_GPIO_CTRL_OFFSET(n)) -#define KL_GPIOA_CTRL_BASE (KL_GPIO_BASEOLD+KL_GPIOA_CTRL_OFFSET) -#define KL_GPIOB_CTRL_BASE (KL_GPIO_BASEOLD+KL_GPIOB_CTRL_OFFSET) -#define KL_GPIOC_CTRL_BASE (KL_GPIO_BASEOLD+KL_GPIOC_CTRL_OFFSET) -#define KL_GPIOD_CTRL_BASE (KL_GPIO_BASEOLD+KL_GPIOD_CTRL_OFFSET) -#define KL_GPIOE_CTRL_BASE (KL_GPIO_BASEOLD+KL_GPIOE_CTRL_OFFSET) +#define KL_GPIO_CTRL_BASE(n) (KL_GPIO_BASE+KL_GPIO_CTRL_OFFSET(n)) +#define KL_GPIOA_CTRL_BASE (KL_GPIO_BASE+KL_GPIOA_CTRL_OFFSET) +#define KL_GPIOB_CTRL_BASE (KL_GPIO_BASE+KL_GPIOB_CTRL_OFFSET) +#define KL_GPIOC_CTRL_BASE (KL_GPIO_BASE+KL_GPIOC_CTRL_OFFSET) +#define KL_GPIOD_CTRL_BASE (KL_GPIO_BASE+KL_GPIOD_CTRL_OFFSET) +#define KL_GPIOE_CTRL_BASE (KL_GPIO_BASE+KL_GPIOE_CTRL_OFFSET) /* GPIO port A control registers */ -#define KL_GPIOA_PMD (KL_GPIO_BASEOLD+KL_GPIOA_PMD_OFFSET) -#define KL_GPIOA_OFFD (KL_GPIO_BASEOLD+KL_GPIOA_OFFD_OFFSET) -#define KL_GPIOA_DOUT (KL_GPIO_BASEOLD+KL_GPIOA_DOUT_OFFSET) -#define KL_GPIOA_DMASK (KL_GPIO_BASEOLD+KL_GPIOA_DMASK_OFFSET) -#define KL_GPIOA_PIN (KL_GPIO_BASEOLD+KL_GPIOA_PIN_OFFSET) -#define KL_GPIOA_DBEN (KL_GPIO_BASEOLD+KL_GPIOA_DBEN_OFFSET) -#define KL_GPIOA_IMD (KL_GPIO_BASEOLD+KL_GPIOA_IMD_OFFSET) -#define KL_GPIOA_IEN (KL_GPIO_BASEOLD+KL_GPIOA_IEN_OFFSET) -#define KL_GPIOA_ISRC (KL_GPIO_BASEOLD+KL_GPIOA_ISRC_OFFSET) +#define KL_GPIOA_PMD (KL_GPIO_BASE+KL_GPIOA_PMD_OFFSET) +#define KL_GPIOA_OFFD (KL_GPIO_BASE+KL_GPIOA_OFFD_OFFSET) +#define KL_GPIOA_DOUT (KL_GPIO_BASE+KL_GPIOA_DOUT_OFFSET) +#define KL_GPIOA_DMASK (KL_GPIO_BASE+KL_GPIOA_DMASK_OFFSET) +#define KL_GPIOA_PIN (KL_GPIO_BASE+KL_GPIOA_PIN_OFFSET) +#define KL_GPIOA_DBEN (KL_GPIO_BASE+KL_GPIOA_DBEN_OFFSET) +#define KL_GPIOA_IMD (KL_GPIO_BASE+KL_GPIOA_IMD_OFFSET) +#define KL_GPIOA_IEN (KL_GPIO_BASE+KL_GPIOA_IEN_OFFSET) +#define KL_GPIOA_ISRC (KL_GPIO_BASE+KL_GPIOA_ISRC_OFFSET) /* GPIO port B control registers */ -#define KL_GPIOB_PMD (KL_GPIO_BASEOLD+KL_GPIOB_PMD_OFFSET) -#define KL_GPIOB_OFFD (KL_GPIO_BASEOLD+KL_GPIOB_OFFD_OFFSET) -#define KL_GPIOB_DOUT (KL_GPIO_BASEOLD+KL_GPIOB_DOUT_OFFSET) -#define KL_GPIOB_DMASK (KL_GPIO_BASEOLD+KL_GPIOB_DMASK_OFFSET) -#define KL_GPIOB_PIN (KL_GPIO_BASEOLD+KL_GPIOB_PIN_OFFSET) -#define KL_GPIOB_DBEN (KL_GPIO_BASEOLD+KL_GPIOB_DBEN_OFFSET) -#define KL_GPIOB_IMD (KL_GPIO_BASEOLD+KL_GPIOB_IMD_OFFSET) -#define KL_GPIOB_IEN (KL_GPIO_BASEOLD+KL_GPIOB_IEN_OFFSET) -#define KL_GPIOB_ISRC (KL_GPIO_BASEOLD+KL_GPIOB_ISRC_OFFSET) +#define KL_GPIOB_PMD (KL_GPIO_BASE+KL_GPIOB_PMD_OFFSET) +#define KL_GPIOB_OFFD (KL_GPIO_BASE+KL_GPIOB_OFFD_OFFSET) +#define KL_GPIOB_DOUT (KL_GPIO_BASE+KL_GPIOB_DOUT_OFFSET) +#define KL_GPIOB_DMASK (KL_GPIO_BASE+KL_GPIOB_DMASK_OFFSET) +#define KL_GPIOB_PIN (KL_GPIO_BASE+KL_GPIOB_PIN_OFFSET) +#define KL_GPIOB_DBEN (KL_GPIO_BASE+KL_GPIOB_DBEN_OFFSET) +#define KL_GPIOB_IMD (KL_GPIO_BASE+KL_GPIOB_IMD_OFFSET) +#define KL_GPIOB_IEN (KL_GPIO_BASE+KL_GPIOB_IEN_OFFSET) +#define KL_GPIOB_ISRC (KL_GPIO_BASE+KL_GPIOB_ISRC_OFFSET) /* GPIO port C control registers */ -#define KL_GPIOC_PMD (KL_GPIO_BASEOLD+KL_GPIOC_PMD_OFFSET) -#define KL_GPIOC_OFFD (KL_GPIO_BASEOLD+KL_GPIOC_OFFD_OFFSET) -#define KL_GPIOC_DOUT (KL_GPIO_BASEOLD+KL_GPIOC_DOUT_OFFSET) -#define KL_GPIOC_DMASK (KL_GPIO_BASEOLD+KL_GPIOC_DMASK_OFFSET) -#define KL_GPIOC_PIN (KL_GPIO_BASEOLD+KL_GPIOC_PIN_OFFSET) -#define KL_GPIOC_DBEN (KL_GPIO_BASEOLD+KL_GPIOC_DBEN_OFFSET) -#define KL_GPIOC_IMD (KL_GPIO_BASEOLD+KL_GPIOC_IMD_OFFSET) -#define KL_GPIOC_IEN (KL_GPIO_BASEOLD+KL_GPIOC_IEN_OFFSET) -#define KL_GPIOC_ISRC (KL_GPIO_BASEOLD+KL_GPIOC_ISRC_OFFSET) +#define KL_GPIOC_PMD (KL_GPIO_BASE+KL_GPIOC_PMD_OFFSET) +#define KL_GPIOC_OFFD (KL_GPIO_BASE+KL_GPIOC_OFFD_OFFSET) +#define KL_GPIOC_DOUT (KL_GPIO_BASE+KL_GPIOC_DOUT_OFFSET) +#define KL_GPIOC_DMASK (KL_GPIO_BASE+KL_GPIOC_DMASK_OFFSET) +#define KL_GPIOC_PIN (KL_GPIO_BASE+KL_GPIOC_PIN_OFFSET) +#define KL_GPIOC_DBEN (KL_GPIO_BASE+KL_GPIOC_DBEN_OFFSET) +#define KL_GPIOC_IMD (KL_GPIO_BASE+KL_GPIOC_IMD_OFFSET) +#define KL_GPIOC_IEN (KL_GPIO_BASE+KL_GPIOC_IEN_OFFSET) +#define KL_GPIOC_ISRC (KL_GPIO_BASE+KL_GPIOC_ISRC_OFFSET) /* GPIO port D control registers */ -#define KL_GPIOD_PMD (KL_GPIO_BASEOLD+KL_GPIOD_PMD_OFFSET) -#define KL_GPIOD_OFFD (KL_GPIO_BASEOLD+KL_GPIOD_OFFD_OFFSET) -#define KL_GPIOD_DOUT (KL_GPIO_BASEOLD+KL_GPIOD_DOUT_OFFSET) -#define KL_GPIOD_DMASK (KL_GPIO_BASEOLD+KL_GPIOD_DMASK_OFFSET) -#define KL_GPIOD_PIN (KL_GPIO_BASEOLD+KL_GPIOD_PIN_OFFSET) -#define KL_GPIOD_DBEN (KL_GPIO_BASEOLD+KL_GPIOD_DBEN_OFFSET) -#define KL_GPIOD_IMD (KL_GPIO_BASEOLD+KL_GPIOD_IMD_OFFSET) -#define KL_GPIOD_IEN (KL_GPIO_BASEOLD+KL_GPIOD_IEN_OFFSET) -#define KL_GPIOD_ISRC (KL_GPIO_BASEOLD+KL_GPIOD_ISRC_OFFSET) +#define KL_GPIOD_PMD (KL_GPIO_BASE+KL_GPIOD_PMD_OFFSET) +#define KL_GPIOD_OFFD (KL_GPIO_BASE+KL_GPIOD_OFFD_OFFSET) +#define KL_GPIOD_DOUT (KL_GPIO_BASE+KL_GPIOD_DOUT_OFFSET) +#define KL_GPIOD_DMASK (KL_GPIO_BASE+KL_GPIOD_DMASK_OFFSET) +#define KL_GPIOD_PIN (KL_GPIO_BASE+KL_GPIOD_PIN_OFFSET) +#define KL_GPIOD_DBEN (KL_GPIO_BASE+KL_GPIOD_DBEN_OFFSET) +#define KL_GPIOD_IMD (KL_GPIO_BASE+KL_GPIOD_IMD_OFFSET) +#define KL_GPIOD_IEN (KL_GPIO_BASE+KL_GPIOD_IEN_OFFSET) +#define KL_GPIOD_ISRC (KL_GPIO_BASE+KL_GPIOD_ISRC_OFFSET) /* GPIO port E control registers */ -#define KL_GPIOE_PMD (KL_GPIO_BASEOLD+KL_GPIOE_PMD_OFFSET) -#define KL_GPIOE_OFFD (KL_GPIO_BASEOLD+KL_GPIOE_OFFD_OFFSET) -#define KL_GPIOE_DOUT (KL_GPIO_BASEOLD+KL_GPIOE_DOUT_OFFSET) -#define KL_GPIOE_DMASK (KL_GPIO_BASEOLD+KL_GPIOE_DMASK_OFFSET) -#define KL_GPIOE_PIN (KL_GPIO_BASEOLD+KL_GPIOE_PIN_OFFSET) -#define KL_GPIOE_DBEN (KL_GPIO_BASEOLD+KL_GPIOE_DBEN_OFFSET) -#define KL_GPIOE_IMD (KL_GPIO_BASEOLD+KL_GPIOE_IMD_OFFSET) -#define KL_GPIOE_IEN (KL_GPIO_BASEOLD+KL_GPIOE_IEN_OFFSET) -#define KL_GPIOE_ISRC (KL_GPIO_BASEOLD+KL_GPIOE_ISRC_OFFSET) +#define KL_GPIOE_PMD (KL_GPIO_BASE+KL_GPIOE_PMD_OFFSET) +#define KL_GPIOE_OFFD (KL_GPIO_BASE+KL_GPIOE_OFFD_OFFSET) +#define KL_GPIOE_DOUT (KL_GPIO_BASE+KL_GPIOE_DOUT_OFFSET) +#define KL_GPIOE_DMASK (KL_GPIO_BASE+KL_GPIOE_DMASK_OFFSET) +#define KL_GPIOE_PIN (KL_GPIO_BASE+KL_GPIOE_PIN_OFFSET) +#define KL_GPIOE_DBEN (KL_GPIO_BASE+KL_GPIOE_DBEN_OFFSET) +#define KL_GPIOE_IMD (KL_GPIO_BASE+KL_GPIOE_IMD_OFFSET) +#define KL_GPIOE_IEN (KL_GPIO_BASE+KL_GPIOE_IEN_OFFSET) +#define KL_GPIOE_ISRC (KL_GPIO_BASE+KL_GPIOE_ISRC_OFFSET) /* Debounce control registers */ -#define KL_GPIO_DBNCECON (KL_GPIO_BASEOLD+KL_GPIO_DBNCECON_OFFSET) +#define KL_GPIO_DBNCECON (KL_GPIO_BASE+KL_GPIO_DBNCECON_OFFSET) /* GPIO port data I/O register offsets */ -#define KL_PORT_DATAIO_BASE(p) (KL_GPIO_BASEOLD+KL_PORT_DATAIO_OFFSET(p)) -# define KL_PORTA_DATAIO_BASE (KL_GPIO_BASEOLD+KL_PORTA_DATAIO_OFFSET) -# define KL_PORTB_DATAIO_BASE (KL_GPIO_BASEOLD+KL_PORTB_DATAIO_OFFSET) -# define KL_PORTC_DATAIO_BASE (KL_GPIO_BASEOLD+KL_PORTC_DATAIO_OFFSET) -# define KL_PORTD_DATAIO_BASE (KL_GPIO_BASEOLD+KL_PORTD_DATAIO_OFFSET) -# define KL_PORTE_DATAIO_BASE (KL_GPIO_BASEOLD+KL_PORTE_DATAIO_OFFSET) +#define KL_PORT_DATAIO_BASE(p) (KL_GPIO_BASE+KL_PORT_DATAIO_OFFSET(p)) +# define KL_PORTA_DATAIO_BASE (KL_GPIO_BASE+KL_PORTA_DATAIO_OFFSET) +# define KL_PORTB_DATAIO_BASE (KL_GPIO_BASE+KL_PORTB_DATAIO_OFFSET) +# define KL_PORTC_DATAIO_BASE (KL_GPIO_BASE+KL_PORTC_DATAIO_OFFSET) +# define KL_PORTD_DATAIO_BASE (KL_GPIO_BASE+KL_PORTD_DATAIO_OFFSET) +# define KL_PORTE_DATAIO_BASE (KL_GPIO_BASE+KL_PORTE_DATAIO_OFFSET) -#define KL_PORT_PDIO(p,n) (KL_GPIO_BASEOLD+KL_PORT_PDIO_OFFSET(p,n)) +#define KL_PORT_PDIO(p,n) (KL_GPIO_BASE+KL_PORT_PDIO_OFFSET(p,n)) /* GPIO PA Pin Data Input/Output */ -#define KL_PORTA_PDIO(n) (KL_GPIO_BASEOLD+KL_PORTA_PDIO_OFFSET(n)) -# define KL_PA1_PDIO (KL_GPIO_BASEOLD+KL_PA1_PDIO_OFFSET) -# define KL_PA2_PDIO (KL_GPIO_BASEOLD+KL_PA2_PDIO_OFFSET) -# define KL_PA3_PDIO (KL_GPIO_BASEOLD+KL_PA3_PDIO_OFFSET) -# define KL_PA4_PDIO (KL_GPIO_BASEOLD+KL_PA4_PDIO_OFFSET) -# define KL_PA5_PDIO (KL_GPIO_BASEOLD+KL_PA5_PDIO_OFFSET) -# define KL_PA6_PDIO (KL_GPIO_BASEOLD+KL_PA6_PDIO_OFFSET) -# define KL_PA7_PDIO (KL_GPIO_BASEOLD+KL_PA7_PDIO_OFFSET) -# define KL_PA8_PDIO (KL_GPIO_BASEOLD+KL_PA8_PDIO_OFFSET) -# define KL_PA9_PDIO (KL_GPIO_BASEOLD+KL_PA9_PDIO_OFFSET) -# define KL_PA10_PDIO (KL_GPIO_BASEOLD+KL_PA10_PDIO_OFFSET) -# define KL_PA11_PDIO (KL_GPIO_BASEOLD+KL_PA11_PDIO_OFFSET) -# define KL_PA12_PDIO (KL_GPIO_BASEOLD+KL_PA12_PDIO_OFFSET) -# define KL_PA13_PDIO (KL_GPIO_BASEOLD+KL_PA13_PDIO_OFFSET) -# define KL_PA14_PDIO (KL_GPIO_BASEOLD+KL_PA14_PDIO_OFFSET) -# define KL_PA15_PDIO (KL_GPIO_BASEOLD+KL_PA15_PDIO_OFFSET) +#define KL_PORTA_PDIO(n) (KL_GPIO_BASE+KL_PORTA_PDIO_OFFSET(n)) +# define KL_PA1_PDIO (KL_GPIO_BASE+KL_PA1_PDIO_OFFSET) +# define KL_PA2_PDIO (KL_GPIO_BASE+KL_PA2_PDIO_OFFSET) +# define KL_PA3_PDIO (KL_GPIO_BASE+KL_PA3_PDIO_OFFSET) +# define KL_PA4_PDIO (KL_GPIO_BASE+KL_PA4_PDIO_OFFSET) +# define KL_PA5_PDIO (KL_GPIO_BASE+KL_PA5_PDIO_OFFSET) +# define KL_PA6_PDIO (KL_GPIO_BASE+KL_PA6_PDIO_OFFSET) +# define KL_PA7_PDIO (KL_GPIO_BASE+KL_PA7_PDIO_OFFSET) +# define KL_PA8_PDIO (KL_GPIO_BASE+KL_PA8_PDIO_OFFSET) +# define KL_PA9_PDIO (KL_GPIO_BASE+KL_PA9_PDIO_OFFSET) +# define KL_PA10_PDIO (KL_GPIO_BASE+KL_PA10_PDIO_OFFSET) +# define KL_PA11_PDIO (KL_GPIO_BASE+KL_PA11_PDIO_OFFSET) +# define KL_PA12_PDIO (KL_GPIO_BASE+KL_PA12_PDIO_OFFSET) +# define KL_PA13_PDIO (KL_GPIO_BASE+KL_PA13_PDIO_OFFSET) +# define KL_PA14_PDIO (KL_GPIO_BASE+KL_PA14_PDIO_OFFSET) +# define KL_PA15_PDIO (KL_GPIO_BASE+KL_PA15_PDIO_OFFSET) /* GPIO PB Pin Data Input/Output */ -#define KL_PORTB_PDIO(n) (KL_GPIO_BASEOLD+KL_PORTB_PDIO_OFFSET(n)) -# define KL_PB1_PDIO (KL_GPIO_BASEOLD+KL_PB1_PDIO_OFFSET) -# define KL_PB2_PDIO (KL_GPIO_BASEOLD+KL_PB2_PDIO_OFFSET) -# define KL_PB3_PDIO (KL_GPIO_BASEOLD+KL_PB3_PDIO_OFFSET) -# define KL_PB4_PDIO (KL_GPIO_BASEOLD+KL_PB4_PDIO_OFFSET) -# define KL_PB5_PDIO (KL_GPIO_BASEOLD+KL_PB5_PDIO_OFFSET) -# define KL_PB6_PDIO (KL_GPIO_BASEOLD+KL_PB6_PDIO_OFFSET) -# define KL_PB7_PDIO (KL_GPIO_BASEOLD+KL_PB7_PDIO_OFFSET) -# define KL_PB8_PDIO (KL_GPIO_BASEOLD+KL_PB8_PDIO_OFFSET) -# define KL_PB9_PDIO (KL_GPIO_BASEOLD+KL_PB9_PDIO_OFFSET) -# define KL_PB10_PDIO (KL_GPIO_BASEOLD+KL_PB10_PDIO_OFFSET) -# define KL_PB11_PDIO (KL_GPIO_BASEOLD+KL_PB11_PDIO_OFFSET) -# define KL_PB12_PDIO (KL_GPIO_BASEOLD+KL_PB12_PDIO_OFFSET) -# define KL_PB13_PDIO (KL_GPIO_BASEOLD+KL_PB13_PDIO_OFFSET) -# define KL_PB14_PDIO (KL_GPIO_BASEOLD+KL_PB14_PDIO_OFFSET) -# define KL_PB15_PDIO (KL_GPIO_BASEOLD+KL_PB15_PDIO_OFFSET) +#define KL_PORTB_PDIO(n) (KL_GPIO_BASE+KL_PORTB_PDIO_OFFSET(n)) +# define KL_PB1_PDIO (KL_GPIO_BASE+KL_PB1_PDIO_OFFSET) +# define KL_PB2_PDIO (KL_GPIO_BASE+KL_PB2_PDIO_OFFSET) +# define KL_PB3_PDIO (KL_GPIO_BASE+KL_PB3_PDIO_OFFSET) +# define KL_PB4_PDIO (KL_GPIO_BASE+KL_PB4_PDIO_OFFSET) +# define KL_PB5_PDIO (KL_GPIO_BASE+KL_PB5_PDIO_OFFSET) +# define KL_PB6_PDIO (KL_GPIO_BASE+KL_PB6_PDIO_OFFSET) +# define KL_PB7_PDIO (KL_GPIO_BASE+KL_PB7_PDIO_OFFSET) +# define KL_PB8_PDIO (KL_GPIO_BASE+KL_PB8_PDIO_OFFSET) +# define KL_PB9_PDIO (KL_GPIO_BASE+KL_PB9_PDIO_OFFSET) +# define KL_PB10_PDIO (KL_GPIO_BASE+KL_PB10_PDIO_OFFSET) +# define KL_PB11_PDIO (KL_GPIO_BASE+KL_PB11_PDIO_OFFSET) +# define KL_PB12_PDIO (KL_GPIO_BASE+KL_PB12_PDIO_OFFSET) +# define KL_PB13_PDIO (KL_GPIO_BASE+KL_PB13_PDIO_OFFSET) +# define KL_PB14_PDIO (KL_GPIO_BASE+KL_PB14_PDIO_OFFSET) +# define KL_PB15_PDIO (KL_GPIO_BASE+KL_PB15_PDIO_OFFSET) /* GPIO PC Pin Data Input/Output */ -#define KL_PORTC_PDIO(n) (KL_GPIO_BASEOLD+KL_PORTC_PDIO_OFFSET(n)) -# define KL_PC1_PDIO (KL_GPIO_BASEOLD+KL_PC1_PDIO_OFFSET) -# define KL_PC2_PDIO (KL_GPIO_BASEOLD+KL_PC2_PDIO_OFFSET) -# define KL_PC3_PDIO (KL_GPIO_BASEOLD+KL_PC3_PDIO_OFFSET) -# define KL_PC4_PDIO (KL_GPIO_BASEOLD+KL_PC4_PDIO_OFFSET) -# define KL_PC5_PDIO (KL_GPIO_BASEOLD+KL_PC5_PDIO_OFFSET) -# define KL_PC6_PDIO (KL_GPIO_BASEOLD+KL_PC6_PDIO_OFFSET) -# define KL_PC7_PDIO (KL_GPIO_BASEOLD+KL_PC7_PDIO_OFFSET) -# define KL_PC8_PDIO (KL_GPIO_BASEOLD+KL_PC8_PDIO_OFFSET) -# define KL_PC9_PDIO (KL_GPIO_BASEOLD+KL_PC9_PDIO_OFFSET) -# define KL_PC10_PDIO (KL_GPIO_BASEOLD+KL_PC10_PDIO_OFFSET) -# define KL_PC11_PDIO (KL_GPIO_BASEOLD+KL_PC11_PDIO_OFFSET) -# define KL_PC12_PDIO (KL_GPIO_BASEOLD+KL_PC12_PDIO_OFFSET) -# define KL_PC13_PDIO (KL_GPIO_BASEOLD+KL_PC13_PDIO_OFFSET) -# define KL_PC14_PDIO (KL_GPIO_BASEOLD+KL_PC14_PDIO_OFFSET) -# define KL_PC15_PDIO (KL_GPIO_BASEOLD+KL_PC15_PDIO_OFFSET) +#define KL_PORTC_PDIO(n) (KL_GPIO_BASE+KL_PORTC_PDIO_OFFSET(n)) +# define KL_PC1_PDIO (KL_GPIO_BASE+KL_PC1_PDIO_OFFSET) +# define KL_PC2_PDIO (KL_GPIO_BASE+KL_PC2_PDIO_OFFSET) +# define KL_PC3_PDIO (KL_GPIO_BASE+KL_PC3_PDIO_OFFSET) +# define KL_PC4_PDIO (KL_GPIO_BASE+KL_PC4_PDIO_OFFSET) +# define KL_PC5_PDIO (KL_GPIO_BASE+KL_PC5_PDIO_OFFSET) +# define KL_PC6_PDIO (KL_GPIO_BASE+KL_PC6_PDIO_OFFSET) +# define KL_PC7_PDIO (KL_GPIO_BASE+KL_PC7_PDIO_OFFSET) +# define KL_PC8_PDIO (KL_GPIO_BASE+KL_PC8_PDIO_OFFSET) +# define KL_PC9_PDIO (KL_GPIO_BASE+KL_PC9_PDIO_OFFSET) +# define KL_PC10_PDIO (KL_GPIO_BASE+KL_PC10_PDIO_OFFSET) +# define KL_PC11_PDIO (KL_GPIO_BASE+KL_PC11_PDIO_OFFSET) +# define KL_PC12_PDIO (KL_GPIO_BASE+KL_PC12_PDIO_OFFSET) +# define KL_PC13_PDIO (KL_GPIO_BASE+KL_PC13_PDIO_OFFSET) +# define KL_PC14_PDIO (KL_GPIO_BASE+KL_PC14_PDIO_OFFSET) +# define KL_PC15_PDIO (KL_GPIO_BASE+KL_PC15_PDIO_OFFSET) /* GPIO PD Pin Data Input/Output */ -#define KL_PORTD_PDIO(n) (KL_GPIO_BASEOLD+KL_PORTD_PDIO_OFFSET(n)) -# define KL_PD1_PDIO (KL_GPIO_BASEOLD+KL_PD1_PDIO_OFFSET) -# define KL_PD2_PDIO (KL_GPIO_BASEOLD+KL_PD2_PDIO_OFFSET) -# define KL_PD3_PDIO (KL_GPIO_BASEOLD+KL_PD3_PDIO_OFFSET) -# define KL_PD4_PDIO (KL_GPIO_BASEOLD+KL_PD4_PDIO_OFFSET) -# define KL_PD5_PDIO (KL_GPIO_BASEOLD+KL_PD5_PDIO_OFFSET) -# define KL_PD6_PDIO (KL_GPIO_BASEOLD+KL_PD6_PDIO_OFFSET) -# define KL_PD7_PDIO (KL_GPIO_BASEOLD+KL_PD7_PDIO_OFFSET) -# define KL_PD8_PDIO (KL_GPIO_BASEOLD+KL_PD8_PDIO_OFFSET) -# define KL_PD9_PDIO (KL_GPIO_BASEOLD+KL_PD9_PDIO_OFFSET) -# define KL_PD10_PDIO (KL_GPIO_BASEOLD+KL_PD10_PDIO_OFFSET) -# define KL_PD11_PDIO (KL_GPIO_BASEOLD+KL_PD11_PDIO_OFFSET) -# define KL_PD12_PDIO (KL_GPIO_BASEOLD+KL_PD12_PDIO_OFFSET) -# define KL_PD13_PDIO (KL_GPIO_BASEOLD+KL_PD13_PDIO_OFFSET) -# define KL_PD14_PDIO (KL_GPIO_BASEOLD+KL_PD14_PDIO_OFFSET) -# define KL_PD15_PDIO (KL_GPIO_BASEOLD+KL_PD15_PDIO_OFFSET) +#define KL_PORTD_PDIO(n) (KL_GPIO_BASE+KL_PORTD_PDIO_OFFSET(n)) +# define KL_PD1_PDIO (KL_GPIO_BASE+KL_PD1_PDIO_OFFSET) +# define KL_PD2_PDIO (KL_GPIO_BASE+KL_PD2_PDIO_OFFSET) +# define KL_PD3_PDIO (KL_GPIO_BASE+KL_PD3_PDIO_OFFSET) +# define KL_PD4_PDIO (KL_GPIO_BASE+KL_PD4_PDIO_OFFSET) +# define KL_PD5_PDIO (KL_GPIO_BASE+KL_PD5_PDIO_OFFSET) +# define KL_PD6_PDIO (KL_GPIO_BASE+KL_PD6_PDIO_OFFSET) +# define KL_PD7_PDIO (KL_GPIO_BASE+KL_PD7_PDIO_OFFSET) +# define KL_PD8_PDIO (KL_GPIO_BASE+KL_PD8_PDIO_OFFSET) +# define KL_PD9_PDIO (KL_GPIO_BASE+KL_PD9_PDIO_OFFSET) +# define KL_PD10_PDIO (KL_GPIO_BASE+KL_PD10_PDIO_OFFSET) +# define KL_PD11_PDIO (KL_GPIO_BASE+KL_PD11_PDIO_OFFSET) +# define KL_PD12_PDIO (KL_GPIO_BASE+KL_PD12_PDIO_OFFSET) +# define KL_PD13_PDIO (KL_GPIO_BASE+KL_PD13_PDIO_OFFSET) +# define KL_PD14_PDIO (KL_GPIO_BASE+KL_PD14_PDIO_OFFSET) +# define KL_PD15_PDIO (KL_GPIO_BASE+KL_PD15_PDIO_OFFSET) /* GPIO PE Pin Data Input/Output */ -#define KL_PORTE_PDIO(n) (KL_GPIO_BASEOLD+KL_PORTE_PDIO_OFFSET(n)) -# define KL_PE5_PDIO (KL_GPIO_BASEOLD+KL_PE5_PDIO_OFFSET) +#define KL_PORTE_PDIO(n) (KL_GPIO_BASE+KL_PORTE_PDIO_OFFSET(n)) +# define KL_PE5_PDIO (KL_GPIO_BASE+KL_PE5_PDIO_OFFSET) /* Register bit-field definitions ***********************************************************/ diff --git a/nuttx/arch/arm/src/kl/chip/kl_memorymap.h b/nuttx/arch/arm/src/kl/chip/kl_memorymap.h index 76860696f..6978ae975 100644 --- a/nuttx/arch/arm/src/kl/chip/kl_memorymap.h +++ b/nuttx/arch/arm/src/kl/chip/kl_memorymap.h @@ -48,10 +48,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* from NUC memmap */ -#define KL_GPIO_BASEOLD 0x50004000 /* -0x50007fff: GPIO control registers */ -#define KL_GCR_BASE 0x50000000 /* -0x500001ff: System global control registers */ - /* Memory Map ***********************************************************************/ /* K40 Family * diff --git a/nuttx/arch/arm/src/kl/kl_timerisr.c b/nuttx/arch/arm/src/kl/kl_timerisr.c index 0df667016..409ccd063 100644 --- a/nuttx/arch/arm/src/kl/kl_timerisr.c +++ b/nuttx/arch/arm/src/kl/kl_timerisr.c @@ -51,7 +51,6 @@ #include "up_arch.h" #include "chip.h" -#include "chip/kl_gcr.h" /**************************************************************************** * Pre-processor Definitions |