Early bringup bugfixes

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2752 42af7a65-404d-4744-a932-0658087f49c3

4 files changed, 15 insertions, 23 deletions

diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
index bcb701407..9cc3ba353 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_allocateheap.c
@@ -77,25 +77,11 @@
 
 #ifdef LPC17_HAVE_BANK0
 #  if CONFIG_MM_REGIONS < 2
-#    warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank0 not included in HEAP"
+#    warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank(s) not included in HEAP"
 #  endif
 #else
 #  if CONFIG_MM_REGIONS > 1
-#    warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0"
-#    undef CONFIG_MM_REGIONS
-#    define CONFIG_MM_REGIONS 1
-#  endif
-#endif
-
-#ifdef LPC17_HAVE_BANK1
-#  if CONFIG_MM_REGIONS < 3
-#    warning "CONFIG_MM_REGIONS < 3: AHB SRAM Bank1 not included in HEAP"
-#  endif
-#else
-#  if CONFIG_MM_REGIONS > 2
-#    warning "CONFIG_MM_REGIONS > 2: This MCU has no AHB SRAM Bank1"
-#    undef CONFIG_MM_REGIONS
-#    define CONFIG_MM_REGIONS 2
+#    warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0/1"
 #  endif
 #endif
 
@@ -141,10 +127,16 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 #if CONFIG_MM_REGIONS > 1
 void up_addregion(void)
 {
-  mm_addregion((FAR void*)LPC17_HAVE_BANK0, 16*1024);
+  /* Banks 0 and 1 are each 16Kb.  If both are present, they occupy a
+   * contiguous 32Kb memory region.
+   */
 
-#if CONFIG_MM_REGIONS > 2
-  mm_addregion((FAR void*)LPC17_HAVE_BANK1, 16*1024);
+#ifdef LPC17_HAVE_BANK0
+# ifdef LPC17_HAVE_BANK1
+  mm_addregion((FAR void*)LPC17_SRAM_BANK0, 32*1024);
+# else
+  mm_addregion((FAR void*)LPC17_SRAM_BANK0, 16*1024);
+# endif
 #endif
 }
 #endif
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
index be538d85d..853028692 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_gpio.c
@@ -110,9 +110,9 @@ const uint32_t g_fiobase[GPIO_NPORTS] =
 
 const uint32_t g_intbase[GPIO_NPORTS] = 
 {
-  LPC17_GPIOINT0_OFFSET,
+  LPC17_GPIOINT0_BASE,
   0,
-  LPC17_GPIOINT2_OFFSET,
+  LPC17_GPIOINT2_BASE,
   0,
   0
 };
diff --git a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
index b56d35a8d..f331c958c 100755
--- a/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
+++ b/nuttx/arch/arm/src/lpc17xx/lpc17_memorymap.h
@@ -54,7 +54,7 @@
 #define LPC17_SRAM_BASE     0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */

 #define LPC17_ROM_BASE      0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */

 #define LPC17_AHBSRAM_BASE  0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */

-#  define LPC17_SRAM_BANK0  0x20070000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */

+#  define LPC17_SRAM_BANK0  0x2007c000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */

 #  define LPC17_SRAM_BANK1  0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank1 (devices 64Kb) */

 #define LPC17_GPIO_BASE     0x2009c000 /* -0x2009ffff: GPIO */

 #define LPC17_APB_BASE      0x40000000 /* -0x5fffffff: APB Peripherals */

diff --git a/nuttx/configs/nucleus2g/ostest/defconfig b/nuttx/configs/nucleus2g/ostest/defconfig
index 93a11c454..f2f075bb1 100755
--- a/nuttx/configs/nucleus2g/ostest/defconfig
+++ b/nuttx/configs/nucleus2g/ostest/defconfig
@@ -299,7 +299,7 @@ CONFIG_EXAMPLE=ostest
 CONFIG_DEBUG=n
 CONFIG_DEBUG_VERBOSE=n
 CONFIG_DEBUG_SYMBOLS=n
-CONFIG_MM_REGIONS=3
+CONFIG_MM_REGIONS=2
 CONFIG_ARCH_LOWPUTC=y
 CONFIG_RR_INTERVAL=200
 CONFIG_SCHED_INSTRUMENTATION=n