SAM4E: Update SAM3/4 GPBR, HSMCI, PWM, RSTC, RTC, RTT, SMC, and WDT register definition header files

9 files changed, 433 insertions, 164 deletions

diff --git a/nuttx/arch/arm/src/sam34/chip/sam_gpbr.h b/nuttx/arch/arm/src/sam34/chip/sam_gpbr.h
index f439be79a..d8997c0cf 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_gpbr.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_gpbr.h
@@ -1,7 +1,7 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_gpbr.h
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -51,15 +51,30 @@
 
 /* GPBR register offsets ****************************************************************/
 
-#define SAM_GPBR_OFFSET(n)  ((n)<<2) /* General purpose back-up registers */
-#define SAM_GPBR0_OFFSET    0x00
-#define SAM_GPBR1_OFFSET    0x04
-#define SAM_GPBR2_OFFSET    0x08
-#define SAM_GPBR3_OFFSET    0x0c
-#define SAM_GPBR4_OFFSET    0x10
-#define SAM_GPBR5_OFFSET    0x14
-#define SAM_GPBR6_OFFSET    0x18
-#define SAM_GPBR7_OFFSET    0x1c
+#define SAM_GPBR_OFFSET(n)   ((n)<<2) /* General purpose back-up registers */
+#define SAM_GPBR0_OFFSET     0x00
+#define SAM_GPBR1_OFFSET     0x04
+#define SAM_GPBR2_OFFSET     0x08
+#define SAM_GPBR3_OFFSET     0x0c
+#define SAM_GPBR4_OFFSET     0x10
+#define SAM_GPBR5_OFFSET     0x14
+#define SAM_GPBR6_OFFSET     0x18
+#define SAM_GPBR7_OFFSET     0x1c
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_GPBR8_OFFSET   0x20
+#  define SAM_GPBR9_OFFSET   0x24
+#  define SAM_GPBR10_OFFSET  0x28
+#  define SAM_GPBR11_OFFSET  0x2c
+#  define SAM_GPBR12_OFFSET  0x30
+#  define SAM_GPBR13_OFFSET  0x34
+#  define SAM_GPBR14_OFFSET  0x38
+#  define SAM_GPBR15_OFFSET  0x3c
+#  define SAM_GPBR16_OFFSET  0x40
+#  define SAM_GPBR17_OFFSET  0x44
+#  define SAM_GPBR18_OFFSET  0x48
+#  define SAM_GPBR19_OFFSET  0x4c
+#endif
 
 /* GPBR register adresses ***************************************************************/
 
@@ -73,8 +88,25 @@
 #define SAM_GPBR6           (SAM_GPBR_BASE+SAM_GPBR6_OFFSET)
 #define SAM_GPBR7           (SAM_GPBR_BASE+SAM_GPBR7_OFFSET)
 
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_GPBR8         (SAM_GPBR_BASE+SAM_GPBR8_OFFSET)
+#  define SAM_GPBR9         (SAM_GPBR_BASE+SAM_GPBR9_OFFSET)
+#  define SAM_GPBR10        (SAM_GPBR_BASE+SAM_GPBR10_OFFSET)
+#  define SAM_GPBR11        (SAM_GPBR_BASE+SAM_GPBR11_OFFSET)
+#  define SAM_GPBR12        (SAM_GPBR_BASE+SAM_GPBR12_OFFSET)
+#  define SAM_GPBR13        (SAM_GPBR_BASE+SAM_GPBR13_OFFSET)
+#  define SAM_GPBR14        (SAM_GPBR_BASE+SAM_GPBR14_OFFSET)
+#  define SAM_GPBR15        (SAM_GPBR_BASE+SAM_GPBR15_OFFSET)
+#  define SAM_GPBR16        (SAM_GPBR_BASE+SAM_GPBR16_OFFSET)
+#  define SAM_GPBR17        (SAM_GPBR_BASE+SAM_GPBR17_OFFSET)
+#  define SAM_GPBR18        (SAM_GPBR_BASE+SAM_GPBR18_OFFSET)
+#  define SAM_GPBR19        (SAM_GPBR_BASE+SAM_GPBR19_OFFSET)
+#endif
+
 /* GPBR register bit definitions ********************************************************/
 
+/* All 32-bit values */
+
 /****************************************************************************************
  * Public Types
  ****************************************************************************************/
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h
index 887d561ca..d05a1ac50 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_hsmci.h
@@ -1,7 +1,7 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_hsmci.h
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -127,15 +127,17 @@
 
 #define HSMCI_MR_CLKDIV_SHIFT         (0)       /* Bits 0-7: Clock Divider */
 #define HSMCI_MR_CLKDIV_MASK          (0xff << HSMCI_MR_CLKDIV_SHIFT)
+#  define HSMCI_MR_CLKDIV(n)          ((uint32_t)(n) << HSMCI_MR_CLKDIV_SHIFT)
 #define HSMCI_MR_PWSDIV_SHIFT         (8)       /* Bits 8-10: Power Saving Divider */
 #define HSMCI_MR_PWSDIV_MASK          (7 << HSMCI_MR_PWSDIV_SHIFT)
+#  define HSMCI_MR_PWSDIV(n)          ((uint32_t)(n) << HSMCI_MR_PWSDIV_SHIFT)
 #  define HSMCI_MR_PWSDIV_MAX         (7 << HSMCI_MR_PWSDIV_SHIFT)
 #define HSMCI_MR_RDPROOF              (1 << 11) /* Bit 11: Read Proof Enable */
 #define HSMCI_MR_WRPROOF              (1 << 12) /* Bit 12: Write Proof Enable */
 #define HSMCI_MR_FBYTE                (1 << 13) /* Bit 13: Force Byte Transfer */
 #define HSMCI_MR_PADV                 (1 << 14) /* Bit 14: Padding Value */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define HSMCI_MR_PDCMODE            (1 << 15) /* Bit 15: PDC-oriented Mode */
 #endif
 
@@ -144,10 +146,15 @@
 #  define HSMCI_MR_BLKLEN_MASK        (0xffff << HSMCI_MR_BLKLEN_SHIFT)
 #endif
 
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define HSMCI_MR_CLKODD             (1 << 16) /* Bit 16: Clock divider is odd */
+#endif
+
 /* HSMCI Data Timeout Register */
 
 #define HSMCI_DTOR_DTOCYC_SHIFT       (0)       /* Bits 0-3: Data Timeout Cycle Number */
 #define HSMCI_DTOR_DTOCYC_MASK        (15 << HSMCI_DTOR_DTOCYC_SHIFT)
+#  define HSMCI_DTOR_DTOCYC(n)        ((uint32_t)(n) << HSMCI_DTOR_DTOCYC_SHIFT)
 #  define HSMCI_DTOR_DTOCYC_MAX       (15 << HSMCI_DTOR_DTOCYC_SHIFT)
 #define HSMCI_DTOR_DTOMUL_SHIFT       (4)       /* Bits 4-6: Data Timeout Multiplier */
 #define HSMCI_DTOR_DTOMUL_MASK        (7 << HSMCI_DTOR_DTOMUL_SHIFT)
@@ -178,6 +185,7 @@
 
 #define HSMCI_CMDR_CMDNB_SHIFT        (0)       /* Bits 0-5: Command Number */
 #define HSMCI_CMDR_CMDNB_MASK         (63 << HSMCI_CMDR_CMDNB_SHIFT)
+#  define HSMCI_CMDR_CMDNB(n)         ((uint32_t)(n) << HSMCI_CMDR_CMDNB_SHIFT)
 #define HSMCI_CMDR_RSPTYP_SHIFT       (6)       /* Bits 6-7: Response Type */
 #define HSMCI_CMDR_RSPTYP_MASK        (3 << HSMCI_CMDR_RSPTYP_SHIFT)
 #  define HSMCI_CMDR_RSPTYP_NONE      (0 << HSMCI_CMDR_RSPTYP_SHIFT) /* No response */
@@ -223,13 +231,16 @@
 
 #define HSMCI_BLKR_BCNT_SHIFT         (0)       /* Bits 0-15: MMC/SDIO Block Count - SDIO Byte Count */
 #define HSMCI_BLKR_BCNT_MASK          (0xffff << HSMCI_BLKR_BCNT_SHIFT)
+#  define HSMCI_BLKR_BCNT(n)          ((uint32_t)(n) << HSMCI_BLKR_BCNT_SHIFT)
 #define HSMCI_BLKR_BLKLEN_SHIFT       (16)      /* Bits 16-31: Data Block Length */
 #define HSMCI_BLKR_BLKLEN_MASK        (0xffff << HSMCI_BLKR_BLKLEN_SHIFT)
+#  define HSMCI_BLKR_BLKLEN(n)        ((uint32_t)(n) << HSMCI_BLKR_BLKLEN_SHIFT)
 
 /* HSMCI Completion Signal Timeout Register */
 
 #define HSMCI_CSTOR_CSTOCYC_SHIFT     (0)       /* Bits 0-3: Completion Signal Timeout Cycle Number */
 #define HSMCI_CSTOR_CSTOCYC_MASK      (15 << HSMCI_CSTOR_CSTOCYC_SHIFT)
+#  define HSMCI_CSTOR_CSTOCYC(n)      ((uint32_t)(n) << HSMCI_CSTOR_CSTOCYC_SHIFT)
 #define HSMCI_CSTOR_CSTOMUL_SHIFT     (4)       /* Bits 4-6: Completion Signal Timeout Multiplier */
 #define HSMCI_CSTOR_CSTOMUL_MASK      (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
 #  define HSMCI_CSTOR_CSTOMUL_1       (0 << HSMCI_CSTOR_CSTOMUL_SHIFT)
@@ -256,7 +267,7 @@
 #define HSMCI_INT_DTIP                (1 << 4)  /* Bit 4:  Data Transfer in Progress */
 #define HSMCI_INT_NOTBUSY             (1 << 5)  /* Bit 6:  HSMCI Not Busy */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define HSMCI_INT_ENDRX             (1 << 6)  /* Bit 6:  End of RX Buffer */
 #  define HSMCI_INT_ENDTX             (1 << 7)  /* Bit 7:  End of TX Buffer */
 #endif
@@ -265,7 +276,7 @@
 #define HSMCI_INT_SDIOWAIT            (1 << 12) /* Bit 12: SDIO Read Wait Operation Status */
 #define HSMCI_INT_CSRCV               (1 << 13) /* Bit 13: CE-ATA Completion Signal Received */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define HSMCI_INT_RXBUFF            (1 << 14) /* Bit 14:  RXBUFF: RX Buffer Full */
 #  define HSMCI_INT_TXBUFE            (1 << 15) /* Bit 15:  TXBUFE: TX Buffer Empty */
 #endif
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_pwm.h b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h
index d18ca291c..79b9aa043 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_pwm.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_pwm.h
@@ -1,8 +1,8 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_pwm.h
- * Pulse Width Modulation Controller (PWM) definitions for the SAM3U and SAM4S
+ * Pulse Width Modulation Controller (PWM) definitions for the SAM3U, SAM4E and SAM4S
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -78,16 +78,31 @@
 #define SAM_PWM_FMR_OFFSET           0x05c /* PWM Fault Mode Register */
 #define SAM_PWM_FSR_OFFSET           0x060 /* PWM Fault Status Register */
 #define SAM_PWM_FCR_OFFSET           0x064 /* PWM Fault Clear Register */
-#define SAM_PWM_FPV_OFFSET           0x068 /* PWM Fault Protection Value Register */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWM_FPV1_OFFSET        0x068 /* PWM Fault Protection Value Register 1 */
+#else
+#  define SAM_PWM_FPV_OFFSET         0x068 /* PWM Fault Protection Value Register */
+#endif
+
 #define SAM_PWM_FPE_OFFSET           0x06c /* PWM Fault Protection Enable Register */
                                            /* 0x070-0x078: Reserved */
-#define SAM_PWM_EL0MR_OFFSET         0x07c /* PWM Event Line 0 Mode Register */
-#define SAM_PWM_EL1MR_OFFSET         0x080 /* PWM Event Line 1 Mode Register */
-                                           /* 0x084-0x0ac: Reserved */
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#define SAM_PWM_ELMR0_OFFSET         0x07c /* PWM Event Line 0 Mode Register */
+#define SAM_PWM_ELMR1_OFFSET         0x080 /* PWM Event Line 1 Mode Register */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWM_SSPR_OFFSET        0x0a0 /* PWM Spread Spectrum Register */
+#  define SAM_PWM_SSPUP_OFFSET       0x0a4 /* PWM Spread Spectrum Update Register */
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define SAM_PWM_SMMR_OFFSET        0x0b0 /* PWM Stepper Motor Mode Register */
 #endif
-                                           /* 0x0b4-0x0e0: Reserved */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWM_FPV2_OFFSET        0x0c0 /* PWM Fault Protection Value 2 Register */
+#endif
+
 #define SAM_PWM_WPCR_OFFSET          0x0e4 /* PWM Write Protect Control Register */
 #define SAM_PWM_WPSR_OFFSET          0x0e8 /* PWM Write Protect Status Register */
                                            /* 0x100-0x128: Reserved for PDC registers */
@@ -188,7 +203,30 @@
 #define SAM_PWMCH3_DT_OFFSET         0x278 /* PWM Channel 3 Dead Time Register */
 #define SAM_PWMCH3_DTUPD_OFFSET      0x27c /* PWM Channel 3 Dead Time Update Register */
 
-/* PWM register adresses ****************************************************************/
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWMCH_OFFSET2(n)       (0x400+((n)<< 5))
+#  define SAM_PWMCH_CMUPD_OFFSET     0x0000 /* PWM Channel Mode Update Register */
+#  define SAM_PWMCH_CAE_OFFSET       0x0004 /* PWM Channel Additional Edge Register */
+#  define SAM_PWMCH_CAEUPD_OFFSET    0x0008 /* PWM Channel Additional Edge Update Register */
+
+#  define SAM_PWMCH0_CMUPD_OFFSET    0x0400 /* PWM Channel 0 Mode Update Register */
+#  define SAM_PWMCH0_CAE_OFFSET      0x0404 /* PWM Channel 0 Additional Edge Register */
+#  define SAM_PWMCH0_CAEUPD_OFFSET   0x0408 /* PWM Channel 0 Additional Edge Update Register */
+
+#  define SAM_PWMCH1_CMUPD_OFFSET    0x0420 /* PWM Channel 1 Mode Update Register */
+#  define SAM_PWMCH1_CAE_OFFSET      0x0424 /* PWM Channel 1 Additional Edge Register */
+#  define SAM_PWMCH1_CAEUPD_OFFSET   0x0428 /* PWM Channel 1 Additional Edge Update Register */
+
+#  define SAM_PWMCH2_CMUPD_OFFSET    0x0440 /* PWM Channel 2 Mode Update Register */
+#  define SAM_PWMCH2_CAE_OFFSET      0x0444 /* PWM Channel 2 Additional Edge Register */
+#  define SAM_PWMCH2_CAEUPD_OFFSET   0x0448 /* PWM Channel 2 Additional Edge Update Register */
+
+#  define SAM_PWMCH3_CMUPD_OFFSET    0x0460 /* PWM Channel 3 Mode Update Register */
+#  define SAM_PWMCH3_CAE_OFFSET      0x0464 /* PWM Channel 3 Additional Edge Register */
+#  define SAM_PWMCH3_CAEUPD_OFFSET   0x0468 /* PWM Channel 3 Additional Edge Update Register */
+#endif
+
+/* PWM register addresses ***************************************************************/
 
 #define SAM_PWM_CLK                  (SAM_PWM_BASE+SAM_PWM_CLK_OFFSET)
 #define SAM_PWM_ENA                  (SAM_PWM_BASE+SAM_PWM_ENA_OFFSET)
@@ -215,14 +253,30 @@
 #define SAM_PWM_FMR                  (SAM_PWM_BASE+SAM_PWM_FMR_OFFSET)
 #define SAM_PWM_FSR                  (SAM_PWM_BASE+SAM_PWM_FSR_OFFSET)
 #define SAM_PWM_FCR                  (SAM_PWM_BASE+SAM_PWM_FCR_OFFSET)
-#define SAM_PWM_FPV                  (SAM_PWM_BASE+SAM_PWM_FPV_OFFSET)
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWM_FPV1               (SAM_PWM_BASE+SAM_PWM_FPV1_OFFSET)
+#else
+#  define SAM_PWM_FPV                (SAM_PWM_BASE+SAM_PWM_FPV_OFFSET)
+#endif
+
 #define SAM_PWM_FPE                  (SAM_PWM_BASE+SAM_PWM_FPE_OFFSET)
-#define SAM_PWM_EL0MR                (SAM_PWM_BASE+SAM_PWM_EL0MR_OFFSET)
-#define SAM_PWM_EL1MR                (SAM_PWM_BASE+SAM_PWM_EL1MR_OFFSET)
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
-#  define SAM_PWM_SMMR_OFFSET        0x0b0 /* PWM Stepper Motor Mode Register */
-#  define SAM_PWM_SMMR_OFFSET        0x0b0 /* PWM Stepper Motor Mode Register */
+#define SAM_PWM_ELMR0                (SAM_PWM_BASE+SAM_PWM_ELMR0_OFFSET)
+#define SAM_PWM_ELMR1                (SAM_PWM_BASE+SAM_PWM_ELMR1_OFFSET)
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWM_SSPR               (SAM_PWM_BASE+SAM_PWM_SSPR_OFFSET)
+#  define SAM_PWM_SSPUP              (SAM_PWM_BASE+SAM_PWM_SSPUP_OFFSET)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWM_SMMR               (SAM_PWM_BASE+SAM_PWM_SMMR_OFFSET)
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWM_FPV2               (SAM_PWM_BASE+SAM_PWM_FPV2_OFFSET)
 #endif
+
 #define SAM_PWM_WPCR                 (SAM_PWM_BASE+SAM_PWM_WPCR_OFFSET)
 #define SAM_PWM_WPSR                 (SAM_PWM_BASE+SAM_PWM_WPSR_OFFSET)
 
@@ -322,12 +376,43 @@
 #define SAM_PWMCH3_DT                (SAM_PWMCH3_BASE+SAM_PWMCH_DT_OFFSET)
 #define SAM_PWMCH3_DTUPD             (SAM_PWMCH3_BASE+SAM_PWMCH_DTUPD_OFFSET)
 
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define SAM_PWMCH_BASE2(n)         (SAM_PWM_BASE+SAM_PWMCH_OFFSET2(n))
+#  define SAM_PWMCH0_BASE2           (SAM_PWM_BASE+0x0400)
+#  define SAM_PWMCH1_BASE2           (SAM_PWM_BASE+0x0420)
+#  define SAM_PWMCH2_BASE2           (SAM_PWM_BASE+0x0440)
+#  define SAM_PWMCH3_BASE2           (SAM_PWM_BASE+0x0450)
+
+#  define SAM_PWMCH_CMUPD(n)         (SAM_PWMCH_BASE2(n)+SAM_PWMCH_CMUPD_OFFSET)
+#  define SAM_PWMCH_CAE(n)           (SAM_PWMCH_BASE2(n)+SAM_PWMCH_CAE_OFFSET)
+#  define SAM_PWMCH_CAEUPD(n)        (SAM_PWMCH_BASE2(n)+SAM_PWMCH_CAEUPD_OFFSET)
+
+#  define SAM_PWMCH0_CMUPD           (SAM_PWMCH0_BASE2+SAM_PWMCH0_CMUPD_OFFSET)
+#  define SAM_PWMCH0_CAE             (SAM_PWMCH0_BASE2+SAM_PWMCH0_CAE_OFFSET)
+#  define SAM_PWMCH0_CAEUPD          (SAM_PWMCH0_BASE2+SAM_PWMCH0_CAEUPD_OFFSET)
+
+#  define SAM_PWMCH1_CMUPD           (SAM_PWMCH1_BASE2+SAM_PWMCH0_CMUPD_OFFSET)
+#  define SAM_PWMCH1_CAE             (SAM_PWMCH1_BASE2+SAM_PWMCH0_CAE_OFFSET)
+#  define SAM_PWMCH1_CAEUPD          (SAM_PWMCH1_BASE2+SAM_PWMCH0_CAEUPD_OFFSET)
+
+#  define SAM_PWMCH2_CMUPD           (SAM_PWMCH2_BASE2+SAM_PWMCH0_CMUPD_OFFSET)
+#  define SAM_PWMCH2_CAE             (SAM_PWMCH2_BASE2+SAM_PWMCH0_CAE_OFFSET)
+#  define SAM_PWMCH2_CAEUPD          (SAM_PWMCH2_BASE2+SAM_PWMCH0_CAEUPD_OFFSET)
+
+#  define SAM_PWMCH3_CMUPD           (SAM_PWMCH3_BASE2+SAM_PWMCH0_CMUPD_OFFSET)
+#  define SAM_PWMCH3_CAE             (SAM_PWMCH3_BASE2+SAM_PWMCH0_CAE_OFFSET)
+#  define SAM_PWMCH3_CAEUPD          (SAM_PWMCH3_BASE2+SAM_PWMCH0_CAEUPD_OFFSET)
+#endif
+
 /* PWM register bit definitions *********************************************************/
 
 /* PWM Clock Register */
 
 #define PWM_CLK_DIVA_SHIFT           (0)       /* Bits 0-7: CLKA Divide Factor */
 #define PWM_CLK_DIVA_MASK            (0xff << PWM_CLK_DIVA_SHIFT)
+#  define PWM_CLK_DIVA_OFF           (0 << PWM_CLK_DIVA_SHIFT)
+#  define PWM_CLK_DIVA_NONE          (1 << PWM_CLK_DIVA_SHIFT)
+#  define PWM_CLK_DIVA(n)            ((uint32_t)(n) << PWM_CLK_DIVA_SHIFT)
 #define PWM_CLK_PREA_SHIFT           (8)       /* Bits 8-11: CLKA Source Clock Selection */
 #define PWM_CLK_PREA_MASK            (15 << PWM_CLK_PREA_SHIFT)
 #  define PWM_CLK_PREA_MCK           (0  << PWM_CLK_PREA_SHIFT) /* MCK */
@@ -343,6 +428,9 @@
 #  define PWM_CLK_PREA_MCKDIV1024    (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */
 #define PWM_CLK_DIVB_SHIFT           (16)      /* Bits 16-23: CLKB Divide Factor */
 #define PWM_CLK_DIVB_MASK            (0xff << PWM_CLK_DIVB_SHIFT)
+#  define PWM_CLK_DIVB_OFF           (0 << PWM_CLK_DIVB_SHIFT)
+#  define PWM_CLK_DIVB_NONE          (1 << PWM_CLK_DIVB_SHIFT)
+#  define PWM_CLK_DIVB(n)            ((uint32_t)(n) << PWM_CLK_DIVB_SHIFT)
 #define PWM_CLK_PREB_SHIFT           (24)      /* Bit 24-27: CLKB Source Clock Selection */
 #define PWM_CLK_PREB_MASK            (15 << PWM_CLK_PREB_SHIFT)
 #  define PWM_CLK_PREB_MCK           (0  << PWM_CLK_PREB_SHIFT) /* MCK */
@@ -360,33 +448,33 @@
 /* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */
 
 #define SAM_ENAB_CHID(n)             (1 << ((n))
-#define SAM_ENAB_CHID0               (1 << 0)  /* Bit 0:  Counter Event Channel 0 Interrupt */
-#define SAM_ENAB_CHID1               (1 << 1)  /* Bit 1:  Counter Event Channel 1 Interrupt */
-#define SAM_ENAB_CHID2               (1 << 2)  /* Bit 2:  Counter Event Channel 2 Interrupt */
-#define SAM_ENAB_CHID3               (1 << 3)  /* Bit 3:  Counter Event Channel 3 Interrupt */
+#  define SAM_ENAB_CHID0             (1 << 0)  /* Bit 0:  Counter Event Channel 0 Interrupt */
+#  define SAM_ENAB_CHID1             (1 << 1)  /* Bit 1:  Counter Event Channel 1 Interrupt */
+#  define SAM_ENAB_CHID2             (1 << 2)  /* Bit 2:  Counter Event Channel 2 Interrupt */
+#  define SAM_ENAB_CHID3             (1 << 3)  /* Bit 3:  Counter Event Channel 3 Interrupt */
 
 /* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt
  * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions
  */
 
 #define SAM_INT_CHID(n)              (1 << (n))
-#define SAM_INT_CHID0                (1 << 0)  /* Bit 0:  Counter Event Channel 0 Interrupt */
-#define SAM_INT_CHID1                (1 << 1)  /* Bit 1:  Counter Event Channel 1 Interrupt */
-#define SAM_INT_CHID2                (1 << 2)  /* Bit 2:  Counter Event Channel 2 Interrupt */
-#define SAM_INT_CHID3                (1 << 3)  /* Bit 3:  Counter Event Channel 3 Interrupt */
+#  define SAM_INT_CHID0              (1 << 0)  /* Bit 0:  Counter Event Channel 0 Interrupt */
+#  define SAM_INT_CHID1              (1 << 1)  /* Bit 1:  Counter Event Channel 1 Interrupt */
+#  define SAM_INT_CHID2              (1 << 2)  /* Bit 2:  Counter Event Channel 2 Interrupt */
+#  define SAM_INT_CHID3              (1 << 3)  /* Bit 3:  Counter Event Channel 3 Interrupt */
 #define SAM_INT_FCHID(n)             (1 << ((n)+16))
-#define SAM_INT_FCHID0               (1 << 16) /* Bit 16: Fault Protection Trigger Channel 0 Interrupt */
-#define SAM_INT_FCHID1               (1 << 17) /* Bit 17: Fault Protection Trigger Channel 1 Interrupt */
-#define SAM_INT_FCHID2               (1 << 18) /* Bit 18: Fault Protection Trigger Channel 2 Interrupt */
-#define SAM_INT_FCHID3               (1 << 19) /* Bit 19: Fault Protection Trigger Channel 3 Interrupt */
+#  define SAM_INT_FCHID0             (1 << 16) /* Bit 16: Fault Protection Trigger Channel 0 Interrupt */
+#  define SAM_INT_FCHID1             (1 << 17) /* Bit 17: Fault Protection Trigger Channel 1 Interrupt */
+#  define SAM_INT_FCHID2             (1 << 18) /* Bit 18: Fault Protection Trigger Channel 2 Interrupt */
+#  define SAM_INT_FCHID3             (1 << 19) /* Bit 19: Fault Protection Trigger Channel 3 Interrupt */
 
 /* PWM Sync Channels Mode Register */
 
 #define PWM_SCM_SYNC(n)              (1 << (n))
-#define PWM_SCM_SYNC0                (1 << 0)  /* Bit 0:  Synchronous Channel 0 */
-#define PWM_SCM_SYNC1                (1 << 1)  /* Bit 1:  Synchronous Channel 1 */
-#define PWM_SCM_SYNC2                (1 << 2)  /* Bit 2:  Synchronous Channel 2 */
-#define PWM_SCM_SYNC3                (1 << 3)  /* Bit 3:  Synchronous Channel 3 */
+#  define PWM_SCM_SYNC0              (1 << 0)  /* Bit 0:  Synchronous Channel 0 */
+#  define PWM_SCM_SYNC1              (1 << 1)  /* Bit 1:  Synchronous Channel 1 */
+#  define PWM_SCM_SYNC2              (1 << 2)  /* Bit 2:  Synchronous Channel 2 */
+#  define PWM_SCM_SYNC3              (1 << 3)  /* Bit 3:  Synchronous Channel 3 */
 #define PWM_SCM_UPDM_SHIFT           (16)      /* Bits 16-17: Synchronous Channels Update Mode */
 #define PWM_SCM_UPDM_MASK            (3 << PWM_SCM_UPDM_SHIFT)
 #  define PWM_SCM_UPDM_MANMAN        (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */
@@ -395,6 +483,7 @@
 #define PWM_SCM_PTRM                 (1 << 20) /* Bit 20: PDC Transfer Request Mode */
 #define PWM_SCM_PTRCS_SHIFT          (21)      /* Bits 21-23: PDC Transfer Request Comparison Selection */
 #define PWM_SCM_PTRCS_MASK           (7 << PWM_SCM_PTRCS_SHIFT)
+#  define PWM_SCM_PTRCS(n)           ((uint32_t)(n) << PWM_SCM_PTRCS_SHIFT)
 
 /* PWM Sync Channels Update Control Register */
 
@@ -404,13 +493,16 @@
 
 #define PWM_SCUP_UPR_SHIFT           (0)       /* Bits 0-3:  Update Period */
 #define PWM_SCUP_UPR_MASK            (15 << PWM_SCUP_UPR_MASK)
+#  define PWM_SCUP_UPR(n)            ((uint32_t)(n) << PWM_SCUP_UPR_MASK)
 #define PWM_SCUP_UPRCNT_SHIFT        (4)       /* Bits 4-7:  Update Period Counter */
 #define PWM_SCUP_UPRCNT_MASK         (15 << PWM_SCUP_UPRCNT_SHIFT)
+#  define PWM_SCUP_UPRCNT(n)         ((uint32_t)(n) << PWM_SCUP_UPRCNT_SHIFT)
 
 /* PWM Sync Channels Update Period Update Register */
 
 #define PWM_SCUPUPD_SHIFT            (0)       /* Bits 0-3: Update Period Update */
 #define PWM_SCUPUPD_MASK             (15 << PWM_SCUPUPD_SHIFT)
+#  define PWM_SCUPUPD(n)             ((uint32_t)(n) << PWM_SCUPUPD_SHIFT)
 
 /* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */
 
@@ -419,23 +511,23 @@
 #define SAM_INT_TXBUFE               (1 << 2)  /* Bit 2:  PDC TX Buffer Empty Interrupt */
 #define SAM_INT_UNRE                 (1 << 3)  /* Bit 3:  Synch Update Underrun Error Interrupt */
 #define SAM_INT_CMPM(n)              (1 << ((n)+8))
-#define SAM_INT_CMPM0                (1 << 8)  /* Bit 8:  Comparison 0 Match Interrupt */
-#define SAM_INT_CMPM1                (1 << 9)  /* Bit 9:  Comparison 1 Match Interrupt */
-#define SAM_INT_CMPM2                (1 << 10) /* Bit 10: Comparison 2 Match Interrupt */
-#define SAM_INT_CMPM3                (1 << 11) /* Bit 11: Comparison 3 Match Interrupt */
-#define SAM_INT_CMPM4                (1 << 12) /* Bit 12: Comparison 4 Match Interrupt */
-#define SAM_INT_CMPM5                (1 << 13) /* Bit 13: Comparison 5 Match Interrupt */
-#define SAM_INT_CMPM6                (1 << 14) /* Bit 14: Comparison 6 Match Interrupt */
-#define SAM_INT_CMPM7                (1 << 15) /* Bit 15: Comparison 7 Match Interrupt */
+#  define SAM_INT_CMPM0              (1 << 8)  /* Bit 8:  Comparison 0 Match Interrupt */
+#  define SAM_INT_CMPM1              (1 << 9)  /* Bit 9:  Comparison 1 Match Interrupt */
+#  define SAM_INT_CMPM2              (1 << 10) /* Bit 10: Comparison 2 Match Interrupt */
+#  define SAM_INT_CMPM3              (1 << 11) /* Bit 11: Comparison 3 Match Interrupt */
+#  define SAM_INT_CMPM4              (1 << 12) /* Bit 12: Comparison 4 Match Interrupt */
+#  define SAM_INT_CMPM5              (1 << 13) /* Bit 13: Comparison 5 Match Interrupt */
+#  define SAM_INT_CMPM6              (1 << 14) /* Bit 14: Comparison 6 Match Interrupt */
+#  define SAM_INT_CMPM7              (1 << 15) /* Bit 15: Comparison 7 Match Interrupt */
 #define SAM_INT_CMPU(n)              (1 << ((n)+16))
-#define SAM_INT_CMPU0                (1 << 16) /* Bit 16: Comparison o Update Interrupt */
-#define SAM_INT_CMPU1                (1 << 17) /* Bit 17: Comparison 1 Update Interrupt */
-#define SAM_INT_CMPU2                (1 << 18) /* Bit 18: Comparison 2 Update Interrupt */
-#define SAM_INT_CMPU3                (1 << 19) /* Bit 19: Comparison 3 Update Interrupt */
-#define SAM_INT_CMPU4                (1 << 20) /* Bit 20: Comparison 4 Update Interrupt */
-#define SAM_INT_CMPU5                (1 << 21) /* Bit 21: Comparison 5 Update Interrupt */
-#define SAM_INT_CMPU6                (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */
-#define SAM_INT_CMPU7                (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */
+#  define SAM_INT_CMPU0              (1 << 16) /* Bit 16: Comparison o Update Interrupt */
+#  define SAM_INT_CMPU1              (1 << 17) /* Bit 17: Comparison 1 Update Interrupt */
+#  define SAM_INT_CMPU2              (1 << 18) /* Bit 18: Comparison 2 Update Interrupt */
+#  define SAM_INT_CMPU3              (1 << 19) /* Bit 19: Comparison 3 Update Interrupt */
+#  define SAM_INT_CMPU4              (1 << 20) /* Bit 20: Comparison 4 Update Interrupt */
+#  define SAM_INT_CMPU5              (1 << 21) /* Bit 21: Comparison 5 Update Interrupt */
+#  define SAM_INT_CMPU6              (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */
+#  define SAM_INT_CMPU7              (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */
 
 /* PWM Output Override Value Register, PWM Output Selection Register, PWM Output
  * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection
@@ -444,125 +536,203 @@
  */
 
 #define PWM_OUT_OH(n)                (1 << (n))
-#define PWM_OUT_OH0                  (1 << 0)  /* Bit 0:  Value for PWMH output of the channel 0 */
-#define PWM_OUT_OH1                  (1 << 1)  /* Bit 1:  Value for PWMH output of the channel 1 */
-#define PWM_OUT_OH2                  (1 << 2)  /* Bit 2:  Value for PWMH output of the channel 2 */
-#define PWM_OUT_OH3                  (1 << 3)  /* Bit 3:  Value for PWMH output of the channel 3 */
+#  define PWM_OUT_OH0                (1 << 0)  /* Bit 0:  Value for PWMH output of the channel 0 */
+#  define PWM_OUT_OH1                (1 << 1)  /* Bit 1:  Value for PWMH output of the channel 1 */
+#  define PWM_OUT_OH2                (1 << 2)  /* Bit 2:  Value for PWMH output of the channel 2 */
+#  define PWM_OUT_OH3                (1 << 3)  /* Bit 3:  Value for PWMH output of the channel 3 */
 #define PWM_OUT_OL(n)                (1 << ((n)+16))
-#define PWM_OUT_OL0                  (1 << 16) /* Bit 16: Value for PWML output of the channel 0 */
-#define PWM_OUT_OL1                  (1 << 17) /* Bit 17: Value for PWML output of the channel 1 */
-#define PWM_OUT_OL2                  (1 << 18) /* Bit 18: Value for PWML output of the channel 2 */
-#define PWM_OUT_OL3                  (1 << 19) /* Bit 19: Value for PWML output of the channel 3 */
+#  define PWM_OUT_OL0                (1 << 16) /* Bit 16: Value for PWML output of the channel 0 */
+#  define PWM_OUT_OL1                (1 << 17) /* Bit 17: Value for PWML output of the channel 1 */
+#  define PWM_OUT_OL2                (1 << 18) /* Bit 18: Value for PWML output of the channel 2 */
+#  define PWM_OUT_OL3                (1 << 19) /* Bit 19: Value for PWML output of the channel 3 */
 
 /* PWM Fault Mode Register */
 
 #define PWM_FMR_FPOL(n)              (1 << (n))
-#define PWM_FMR_FPOL0                (1 << 0)  /* Bit 0:  Fault 0 Polarity */
-#define PWM_FMR_FPOL1                (1 << 1)  /* Bit 1:  Fault 1 Polarity */
-#define PWM_FMR_FPOL2                (1 << 2)  /* Bit 2:  Fault 2 Polarity */
-#define PWM_FMR_FPOL3                (1 << 3)  /* Bit 3:  Fault 3 Polarity */
+#  define PWM_FMR_FPOL0              (1 << 0)  /* Bit 0:  Fault 0 Polarity */
+#  define PWM_FMR_FPOL1              (1 << 1)  /* Bit 1:  Fault 1 Polarity */
+#  define PWM_FMR_FPOL2              (1 << 2)  /* Bit 2:  Fault 2 Polarity */
+#  define PWM_FMR_FPOL3              (1 << 3)  /* Bit 3:  Fault 3 Polarity */
+#  define PWM_FMR_FPOL4              (1 << 4)  /* Bit 4:  Fault 4 Polarity */
+#  define PWM_FMR_FPOL5              (1 << 5)  /* Bit 5:  Fault 5 Polarity */
+#  define PWM_FMR_FPOL6              (1 << 6)  /* Bit 6:  Fault 6 Polarity */
+#  define PWM_FMR_FPOL7              (1 << 7)  /* Bit 7:  Fault 7 Polarity */
 #define PWM_FMR_FMOD(n)              (1 << ((n)+8))
-#define PWM_FMR_FMOD0                (1 << 8)  /* Bit 8:  Fault 0 Activation Mode */
-#define PWM_FMR_FMOD1                (1 << 9)  /* Bit 9:  Fault 1 Activation Mode */
-#define PWM_FMR_FMOD2                (1 << 10) /* Bit 10: Fault 2 Activation Mode */
-#define PWM_FMR_FMOD3                (1 << 11) /* Bit 11: Fault 3 Activation Mode */
+#  define PWM_FMR_FMOD0              (1 << 8)  /* Bit 8:  Fault 0 Activation Mode */
+#  define PWM_FMR_FMOD1              (1 << 9)  /* Bit 9:  Fault 1 Activation Mode */
+#  define PWM_FMR_FMOD2              (1 << 10) /* Bit 10: Fault 2 Activation Mode */
+#  define PWM_FMR_FMOD3              (1 << 11) /* Bit 11: Fault 3 Activation Mode */
+#  define PWM_FMR_FMOD4              (1 << 12) /* Bit 12: Fault 4 Activation Mode */
+#  define PWM_FMR_FMOD5              (1 << 13) /* Bit 13: Fault 5 Activation Mode */
+#  define PWM_FMR_FMOD6              (1 << 14) /* Bit 14: Fault 6 Activation Mode */
+#  define PWM_FMR_FMOD7              (1 << 15) /* Bit 15: Fault 7 Activation Mode */
 #define PWM_FMR_FFIL(n)              (1 << ((n)+16))
 #define PWM_FMR_FFIL0                (1 << 16) /* Bit 16: Fault 0 Filter */
 #define PWM_FMR_FFIL1                (1 << 17) /* Bit 17: Fault 1 Filter */
 #define PWM_FMR_FFIL2                (1 << 18) /* Bit 18: Fault 2 Filter */
 #define PWM_FMR_FFIL3                (1 << 19) /* Bit 19: Fault 3 Filter */
+#define PWM_FMR_FFIL4                (1 << 20) /* Bit 20: Fault 4 Filter */
+#define PWM_FMR_FFIL5                (1 << 21) /* Bit 21: Fault 5 Filter */
+#define PWM_FMR_FFIL6                (1 << 22) /* Bit 22: Fault 6 Filter */
+#define PWM_FMR_FFIL7                (1 << 23) /* Bit 23: Fault 7 Filter */
 
 /* PWM Fault Status Register */
 
 #define PWM_FSR_FIV(n)               (1 << (n))
-#define PWM_FSR_FIV0                 (1 << 0)  /* Bit 0:  Fault Input 0 Value */
-#define PWM_FSR_FIV1                 (1 << 1)  /* Bit 1:  Fault Input 1 Value */
-#define PWM_FSR_FIV2                 (1 << 2)  /* Bit 2:  Fault Input 2 Value */
-#define PWM_FSR_FIV3                 (1 << 3)  /* Bit 3:  Fault Input 3 Value */
+#  define PWM_FSR_FIV0               (1 << 0)  /* Bit 0:  Fault Input 0 Value */
+#  define PWM_FSR_FIV1               (1 << 1)  /* Bit 1:  Fault Input 1 Value */
+#  define PWM_FSR_FIV2               (1 << 2)  /* Bit 2:  Fault Input 2 Value */
+#  define PWM_FSR_FIV3               (1 << 3)  /* Bit 3:  Fault Input 3 Value */
+#  define PWM_FSR_FIV4               (1 << 4)  /* Bit 4:  Fault Input 4 Value */
+#  define PWM_FSR_FIV5               (1 << 5)  /* Bit 5:  Fault Input 5 Value */
+#  define PWM_FSR_FIV6               (1 << 6)  /* Bit 6:  Fault Input 6 Value */
+#  define PWM_FSR_FIV7               (1 << 7)  /* Bit 7:  Fault Input 7 Value */
 #define PWM_FSR_FS(n)                (1 << ((n)+8))
-#define PWM_FSR_FS0                  (1 << 8)  /* Bit 8:  Fault 0 Status */
-#define PWM_FSR_FS1                  (1 << 9)  /* Bit 9:  Fault 1 Status */
-#define PWM_FSR_FS2                  (1 << 10) /* Bit 10: Fault 2 Status */
-#define PWM_FSR_FS3                  (1 << 11) /* Bit 11: Fault 3 Status */
+#  define PWM_FSR_FS0                (1 << 8)  /* Bit 8:  Fault 0 Status */
+#  define PWM_FSR_FS1                (1 << 9)  /* Bit 9:  Fault 1 Status */
+#  define PWM_FSR_FS2                (1 << 10) /* Bit 10: Fault 2 Status */
+#  define PWM_FSR_FS3                (1 << 11) /* Bit 11: Fault 3 Status */
+#  define PWM_FSR_FS4                (1 << 12) /* Bit 12: Fault 4 Status */
+#  define PWM_FSR_FS5                (1 << 13) /* Bit 13: Fault 5 Status */
+#  define PWM_FSR_FS6                (1 << 14) /* Bit 14: Fault 6 Status */
+#  define PWM_FSR_FS7                (1 << 15) /* Bit 15: Fault 7 Status */
 
 /* PWM Fault Clear Register */
 
 #define PWM_FCR_FCLR(n)              (1 << (n))
-#define PWM_FCR_FCLR0                (1 << 0)  /* Bit 0:  Fault 0 Clear */
-#define PWM_FCR_FCLR1                (1 << 1)  /* Bit 1:  Fault 1 Clear */
-#define PWM_FCR_FCLR2                (1 << 2)  /* Bit 2:  Fault 2 Clear */
-#define PWM_FCR_FCLR3                (1 << 3)  /* Bit 3:  Fault 3 Clear */
-
+#  define PWM_FCR_FCLR0              (1 << 0)  /* Bit 0:  Fault 0 Clear */
+#  define PWM_FCR_FCLR1              (1 << 1)  /* Bit 1:  Fault 1 Clear */
+#  define PWM_FCR_FCLR2              (1 << 2)  /* Bit 2:  Fault 2 Clear */
+#  define PWM_FCR_FCLR3              (1 << 3)  /* Bit 3:  Fault 3 Clear */
+#  define PWM_FCR_FCLR4              (1 << 4)  /* Bit 4:  Fault 4 Clear */
+#  define PWM_FCR_FCLR5              (1 << 5)  /* Bit 5:  Fault 5 Clear */
+#  define PWM_FCR_FCLR6              (1 << 6)  /* Bit 6:  Fault 6 Clear */
+#  define PWM_FCR_FCLR7              (1 << 7)  /* Bit 7:  Fault 7 Clear */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+/* PWM Fault Protection Value Register 1 */
+
+#  define PWM_FPV1_FPVH(n)           (1 << (n))
+#    define PWM_FPV1_FPVH0           (1 << 0)  /* Bit 0:  Fault Protection Value PWMH output channel 0 */
+#    define PWM_FPV1_FPVH1           (1 << 1)  /* Bit 1:  Fault Protection Value PWMH output channel 1 */
+#    define PWM_FPV1_FPVH2           (1 << 2)  /* Bit 2:  Fault Protection Value PWMH output channel 2 */
+#    define PWM_FPV1_FPVH3           (1 << 3)  /* Bit 3:  Fault Protection Value PWMH output channel 3 */
+#  define PWM_FPV1_FPVL(n)           (1 << ((n)+16))
+#    define PWM_FPV1_FPVL0           (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */
+#    define PWM_FPV1_FPVL1           (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */
+#    define PWM_FPV1_FPVL2           (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */
+#    define PWM_FPV1_FPVL3           (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */
+
+#else
 /* PWM Fault Protection Value Register */
 
-#define PWM_FPV_FPVH(n)              (1 << (n))
-#define PWM_FPV_FPVH0                (1 << 0)  /* Bit 0:  Fault Protection Value PWMH output channel 0 */
-#define PWM_FPV_FPVH1                (1 << 1)  /* Bit 1:  Fault Protection Value PWMH output channel 1 */
-#define PWM_FPV_FPVH2                (1 << 2)  /* Bit 2:  Fault Protection Value PWMH output channel 2 */
-#define PWM_FPV_FPVH3                (1 << 3)  /* Bit 3:  Fault Protection Value PWMH output channel 3 */
-#define PWM_FPV_FPVL(n)              (1 << ((n)+16))
-#define PWM_FPV_FPVL0                (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */
-#define PWM_FPV_FPVL1                (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */
-#define PWM_FPV_FPVL2                (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */
-#define PWM_FPV_FPVL3                (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */
+#  define PWM_FPV_FPVH(n)            (1 << (n))
+#    define PWM_FPV_FPVH0            (1 << 0)  /* Bit 0:  Fault Protection Value PWMH output channel 0 */
+#    define PWM_FPV_FPVH1            (1 << 1)  /* Bit 1:  Fault Protection Value PWMH output channel 1 */
+#    define PWM_FPV_FPVH2            (1 << 2)  /* Bit 2:  Fault Protection Value PWMH output channel 2 */
+#    define PWM_FPV_FPVH3            (1 << 3)  /* Bit 3:  Fault Protection Value PWMH output channel 3 */
+#  define PWM_FPV_FPVL(n)            (1 << ((n)+16))
+#    define PWM_FPV_FPVL0            (1 << 16) /* Bit 16: Fault Protection Value PWML output channel 0 */
+#    define PWM_FPV_FPVL1            (1 << 17) /* Bit 17: Fault Protection Value PWML output channel 1 */
+#    define PWM_FPV_FPVL2            (1 << 18) /* Bit 18: Fault Protection Value PWML output channel 2 */
+#    define PWM_FPV_FPVL3            (1 << 19) /* Bit 19: Fault Protection Value PWML output channel 3 */
+#endif
 
 /* PWM Fault Protection Enable Register */
 
 #define PWM_FPE_FPEN(n,y)            (1 << (((n)<<8)+y))
-#define PWM_FPE_FPE0(y)              (1 << (y))      /* Bits 0-7:   Fault Protection Enable Fault=y chan=0 */
-#define PWM_FPE_FPE1(y)              (1 << ((y)+8))  /* Bits 8-15:  Fault Protection Enable Fault=y chan=1 */
-#define PWM_FPE_FPE2(y)              (1 << ((y)+16)) /* Bits 16-23: Fault Protection Enable Fault=y chan=2 */
-#define PWM_FPE_FPE3(y)              (1 << ((y)+24)  /* Bits 24-31: Fault Protection Enable Fault=y chan=3 */
+#  define PWM_FPE_FPE0(y)            (1 << (y))      /* Bits 0-7:   Fault Protection Enable Fault=y chan=0 */
+#  define PWM_FPE_FPE1(y)            (1 << ((y)+8))  /* Bits 8-15:  Fault Protection Enable Fault=y chan=1 */
+#  define PWM_FPE_FPE2(y)            (1 << ((y)+16)) /* Bits 16-23: Fault Protection Enable Fault=y chan=2 */
+#  define PWM_FPE_FPE3(y)            (1 << ((y)+24)  /* Bits 24-31: Fault Protection Enable Fault=y chan=3 */
 
 /* PWM Event Line 1/2 Register */
 
 #define PWM_ELMR_CSEL(n)             (1 << (n))
-#define PWM_ELMR_CSEL0               (1 << 0)  /* Bit 0:  Comparison 0 Selection */
-#define PWM_ELMR_CSEL1               (1 << 1)  /* Bit 1:  Comparison 1 Selection */
-#define PWM_ELMR_CSEL2               (1 << 2)  /* Bit 2:  Comparison 2 Selection */
-#define PWM_ELMR_CSEL3               (1 << 3)  /* Bit 3:  Comparison 3 Selection */
-#define PWM_ELMR_CSEL4               (1 << 4)  /* Bit 4:  Comparison 4 Selection */
-#define PWM_ELMR_CSEL5               (1 << 5)  /* Bit 5:  Comparison 5 Selection */
-#define PWM_ELMR_CSEL6               (1 << 6)  /* Bit 6:  Comparison 6 Selection */
-#define PWM_ELMR_CSEL7               (1 << 7)  /* Bit 7:  Comparison 7 Selection */
+#  define PWM_ELMR_CSEL0             (1 << 0)  /* Bit 0:  Comparison 0 Selection */
+#  define PWM_ELMR_CSEL1             (1 << 1)  /* Bit 1:  Comparison 1 Selection */
+#  define PWM_ELMR_CSEL2             (1 << 2)  /* Bit 2:  Comparison 2 Selection */
+#  define PWM_ELMR_CSEL3             (1 << 3)  /* Bit 3:  Comparison 3 Selection */
+#  define PWM_ELMR_CSEL4             (1 << 4)  /* Bit 4:  Comparison 4 Selection */
+#  define PWM_ELMR_CSEL5             (1 << 5)  /* Bit 5:  Comparison 5 Selection */
+#  define PWM_ELMR_CSEL6             (1 << 6)  /* Bit 6:  Comparison 6 Selection */
+#  define PWM_ELMR_CSEL7             (1 << 7)  /* Bit 7:  Comparison 7 Selection */
+
+/* PWM Spread Spectrum Register */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define PWM_SSPR_SPRD_SHIFT        (0)       /* Bits 0-23: Spread Spectrum Limit Value */
+#  define PWM_SSPR_SPRD_MASK         (0x00ffffff << PWM_SSPR_SPRD_SHIFT)
+#    define PWM_SSPR_SPRD(n)         ((uint32_t)(n) << PWM_SSPR_SPRD_SHIFT)
+#  define PWM_SSPR_SPRDM             (1 << 24) /* Bit 24: Spread Spectrum Counter Mode */
+#endif
+
+/* PWM Spread Spectrum Update Register */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define PWM_SSPUP_MASK             (0x00ffffff)  /* Bits 0-23: Spread Spectrum Limit Value Update */
+#endif
 
 /* PWM Stepper Motor Mode Register */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
-# warning SAM4S not yet integrated
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define PWM_SMMR_GCEN_SHIFT        (0)       /* Bits 0-1: Gray Count ENable */
+#  define PWM_SMMR_GCEN_MASK         (3 << PWM_SMMR_GCEN_SHIFT)
+#    define PWM_SMMR_GCEN0           (1 << 0)  /* Bit 0: Gray Count ENable on PWML/H 0/1 */
+#    define PWM_SMMR_GCEN1           (1 << 1)  /* Bit 1:  Gray Count ENable on PWML/H 2/3 */
+#  define PWM_SMMR_DOWN_SHIFT        (16)      /* Bits 16-17: DOWN Count */
+#  define PWM_SMMR_DOWN_MASK         (3 << PWM_SMMR_DOWN_SHIFT)
+#    define PWM_SMMR_DOWN0           (1 << 16) /* Bit 16: DOWN Counter on PWML/H 0/1 */
+#    define PWM_SMMR_DOWN1           (1 << 17) /* Bit 17: DOWN Counter on PWML/H 2/3 */
+#endif
+
+/* PWM Fault Protection Value 2 Register */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define PWM_FPV2_FPVH(n)           (1 << (n))
+#    define PWM_FPV2_FPZH0           (1 << 0)  /* Bit 0:  Fault Protection to Hi-Z PWMH output channel 0 */
+#    define PWM_FPV2_FPZH1           (1 << 1)  /* Bit 1:  Fault Protection to Hi-Z PWMH output channel 1 */
+#    define PWM_FPV2_FPZH2           (1 << 2)  /* Bit 2:  Fault Protection to Hi-Z PWMH output channel 2 */
+#    define PWM_FPV2_FPZH3           (1 << 3)  /* Bit 3:  Fault Protection to Hi-Z PWMH output channel 3 */
+#  define PWM_FPV2_FPVL(n)           (1 << ((n)+16))
+#    define PWM_FPV2_FPZL0           (1 << 16) /* Bit 16: Fault Protection to Hi-Z PWML output channel 0 */
+#    define PWM_FPV2_FPZL1           (1 << 17) /* Bit 17: Fault Protection to Hi-Z PWML output channel 1 */
+#    define PWM_FPV2_FPZL2           (1 << 18) /* Bit 18: Fault Protection to Hi-Z PWML output channel 2 */
+#    define PWM_FPV2_FPZL3           (1 << 19) /* Bit 19: Fault Protection to Hi-Z PWML output channel 3 */
 #endif
 
 /* PWM Write Protect Control Register */
 
 #define PWM_WPCR_WPCMD_SHIFT         (0)       /* Bits 0-1: Write Protect Command */
 #define PWM_WPCR_WPCMD_MASK          (3 << PWM_WPCR_WPCMD_SHIFT)
-#define PWM_WPCR_WPRG(n)             (1 << ((n)+2))
-#define PWM_WPCR_WPRG0               (1 << 2)  /* Bit 2:  Write Protect Register Group 0 */
-#define PWM_WPCR_WPRG1               (1 << 3)  /* Bit 3:  Write Protect Register Group 1 */
-#define PWM_WPCR_WPRG2               (1 << 4)  /* Bit 4:  Write Protect Register Group 2 */
-#define PWM_WPCR_WPRG3               (1 << 5)  /* Bit 5:  Write Protect Register Group 3 */
-#define PWM_WPCR_WPRG4               (1 << 6)  /* Bit 6:  Write Protect Register Group 4 */
-#define PWM_WPCR_WPRG5               (1 << 7)  /* Bit 7:  Write Protect Register Group 5 */
+#  define PWM_WPCR_WPRG(n)           (1 << ((n)+2))
+#  define PWM_WPCR_WPRG0             (1 << 2)  /* Bit 2:  Write Protect Register Group 0 */
+#  define PWM_WPCR_WPRG1             (1 << 3)  /* Bit 3:  Write Protect Register Group 1 */
+#  define PWM_WPCR_WPRG2             (1 << 4)  /* Bit 4:  Write Protect Register Group 2 */
+#  define PWM_WPCR_WPRG3             (1 << 5)  /* Bit 5:  Write Protect Register Group 3 */
+#  define PWM_WPCR_WPRG4             (1 << 6)  /* Bit 6:  Write Protect Register Group 4 */
+#  define PWM_WPCR_WPRG5             (1 << 7)  /* Bit 7:  Write Protect Register Group 5 */
 #define PWM_WPCR_WPKEY_SHIFT         (8)       /* Bits 8-31:  Write Protect Key */
 #define PWM_WPCR_WPKEY_MASK          (0x00ffffff << PWM_WPCR_WPKEY_SHIFT)
+#  define PWM_WPCR_WPKEY             (0x0050574d << PWM_WPCR_WPKEY_SHIFT)
 
 /* PWM Write Protect Status Register */
 
 #define PWM_WPSR_WPSWS(n)            (1 << (n))
-#define PWM_WPSR_WPSWS0              (1 << 0)  /* Bit 0:  Write Protect SW Status */
-#define PWM_WPSR_WPSWS1              (1 << 1)  /* Bit 1:  Write Protect SW Status */
-#define PWM_WPSR_WPSWS2              (1 << 2)  /* Bit 2:  Write Protect SW Status */
-#define PWM_WPSR_WPSWS3              (1 << 3)  /* Bit 3:  Write Protect SW Status */
-#define PWM_WPSR_WPSWS4              (1 << 4)  /* Bit 4:  Write Protect SW Status */
-#define PWM_WPSR_WPSWS5              (1 << 5)  /* Bit 5:  Write Protect SW Status */
+#  define PWM_WPSR_WPSWS0            (1 << 0)  /* Bit 0:  Write Protect SW Status */
+#  define PWM_WPSR_WPSWS1            (1 << 1)  /* Bit 1:  Write Protect SW Status */
+#  define PWM_WPSR_WPSWS2            (1 << 2)  /* Bit 2:  Write Protect SW Status */
+#  define PWM_WPSR_WPSWS3            (1 << 3)  /* Bit 3:  Write Protect SW Status */
+#  define PWM_WPSR_WPSWS4            (1 << 4)  /* Bit 4:  Write Protect SW Status */
+#  define PWM_WPSR_WPSWS5            (1 << 5)  /* Bit 5:  Write Protect SW Status */
 #define PWM_WPSR_WPVS                (1 << 7)  /* Bit 7:  Write Protect Violation Status */
 #define PWM_WPSR_WPHWS(n)            (1 << ((n)+8))
-#define PWM_WPSR_WPHWS0              (1 << 8)  /* Bit 8:  Write Protect HW Status */
-#define PWM_WPSR_WPHWS1              (1 << 9)  /* Bit 9:  Write Protect HW Status */
-#define PWM_WPSR_WPHWS2              (1 << 10) /* Bit 10: Write Protect HW Status */
-#define PWM_WPSR_WPHWS3              (1 << 11) /* Bit 11: Write Protect HW Status */
-#define PWM_WPSR_WPHWS4              (1 << 12) /* Bit 12: Write Protect HW Status */
-#define PWM_WPSR_WPHWS5              (1 << 13) /* Bit 13: Write Protect HW Status */
+#  define PWM_WPSR_WPHWS0            (1 << 8)  /* Bit 8:  Write Protect HW Status */
+#  define PWM_WPSR_WPHWS1            (1 << 9)  /* Bit 9:  Write Protect HW Status */
+#  define PWM_WPSR_WPHWS2            (1 << 10) /* Bit 10: Write Protect HW Status */
+#  define PWM_WPSR_WPHWS3            (1 << 11) /* Bit 11: Write Protect HW Status */
+#  define PWM_WPSR_WPHWS4            (1 << 12) /* Bit 12: Write Protect HW Status */
+#  define PWM_WPSR_WPHWS5            (1 << 13) /* Bit 13: Write Protect HW Status */
 #define PWM_WPSR_WPVSRC_SHIFT        (16)      /* Bits 16-31: Write Protect Violation Source */
 #define PWM_WPSR_WPVSRC_MASK         (0xffff << PWM_WPSR_WPVSRC_SHIFT)
 
@@ -577,14 +747,19 @@
 #define PWMCMP_CEN                   (1 << 0)  /* Bit 0:  Comparison x Enable */
 #define PWMCMP_CTR_SHIFT             (4)       /* Bits 4-7: Comparison x Trigger */
 #define PWMCMP_CTR_MASK              (15 << PWMCMP_CTR_SHIFT)
+#  define PWMCMP_CTR(n)              ((uint32_t)(n) << PWMCMP_CTR_SHIFT)
 #define PWMCMP_CPR_SHIFT             (8)       /* Bits 8-11: Comparison x Period */
 #define PWMCMP_CPR_MASK              (15 << PWMCMP_CPR_SHIFT)
+#  define PWMCMP_CPR(n)              ((uint32_t)(n) << PWMCMP_CPR_SHIFT)
 #define PWMCMP_M_CPRCNT_SHIFT        (12)      /* Bits 12-15: Comparison x Period Count (M only) */
 #define PWMCMP_M_CPRCNT_MASK         (15 << PWMCMP_M_CPRCNT_SHIFT)
+#  define PWMCMP_M_CPRCNT(n)         ((uint32_t)(n) << PWMCMP_M_CPRCNT_SHIFT)
 #define PWMCMP_CUPR_SHIFT            (16)      /* Bits 16-19: Comparison x Update Period */
 #define PWMCMP_CUPR_MASK             (15 << PWMCMP_CUPR_SHIFT)
+#  define PWMCMP_CUPR(n)             ((uint32_t)(n) << PWMCMP_CUPR_SHIFT)
 #define PWMCMP_M_CUPRCNT_SHIFT       (20)      /* Bits 20-23: Comparison x Update Period Counter (M only) */
 #define PWMCMP_M_CUPRCNT_MASK        (15 << PWMCMP_M_CUPRCNT_SHIFT)
+#  define PWMCMP_M_CUPRCNT(n)        ((uint32_t)(n) << PWMCMP_M_CUPRCNT_SHIFT)
 
 /* PWM Channel Mode Register */
 
@@ -606,6 +781,11 @@
 #define PWMCH_MR_CALG                (1 << 8)  /* Bit 8:  Channel Alignment */
 #define PWMCH_MR_CPOL                (1 << 9)  /* Bit 9:  Channel Polarity */
 #define PWMCH_MR_CES                 (1 << 10) /* Bit 10:  Counter Event Selection */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define PWMCH_MR_UPDS              (1 << 11) /* Bit 11: Update Selection */
+#endif
+
 #define PWMCH_MR_DTE                 (1 << 16) /* Bit 16: Dead-Time Generator Enable */
 #define PWMCH_MR_DTHI                (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */
 #define PWMCH_MR_DTLI                (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */
@@ -629,8 +809,30 @@
 
 #define PWMCH_DTH_SHIFT              (0)       /* Bits 0-15: Dead-Time Value for PWMHx Output */
 #define PWMCH_DTH_MASK               (0xffff << PWMCH_DTH_SHIFT)
+#  define PWMCH_DTH(n)               ((uint32_t)(n) << PWMCH_DTH_SHIFT)
 #define PWMCH_DTL_SHIFT              (16)      /* Bits 16-31: Dead-Time Value for PWMLx Output */
 #define PWMCH_DTL_MASK               (0xffff << PWMCH_DTL_SHIFT)
+#  define PWMCH_DTL(n)               ((uint32_t)(n) << PWMCH_DTL_SHIFT)
+
+/* PWM Channel Mode Update Register */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define PWMCH_CMUPD_CPOLUP         (1 << 9)  /* Bit 9:  Channel Polarity Update */
+#  define PWMCH_CMUPD_CPOLINVUP      (1 << 13) /* Bit 13: Channel Polarity Inversion Update */
+#endif
+
+/* PWM Channel Additional Edge Register and PWM Channel Additional Edge Update Register */
+
+#if defined(CONFIG_ARCH_CHIP_SAM4E)
+#  define PWMCH_CAE_ADEDGV_SHIFT     (0)       /* Bits 0-23: Channel Additional Edge Value */
+#  define PWMCH_CAE_ADEDGV_MASK      (0x00ffffff << PWMCH_CAE_ADEDGV_SHIFT)
+#    define PWMCH_CAE_ADEDGV(n)      ((uint32_t)(n) << PWMCH_CAE_ADEDGV_SHIFT)
+#  define PWMCH_CAE_ADEDGM_SHIFT     (24)      /* Bits 24-25: Channel Additional Edge Mode */
+#  define PWMCH_CAE_ADEDGM_MASK      (3 << PWMCH_CAE_ADEDGM_SHIFT)
+#    define PWMCH_CAE_ADEDGM_INC     (0 << PWMCH_CAE_ADEDGM_SHIFT)
+#    define PWMCH_CAE_ADEDGM_DEC     (1 << PWMCH_CAE_ADEDGM_SHIFT)
+#    define PWMCH_CAE_ADEDGM_BOTH    (2 << PWMCH_CAE_ADEDGM_SHIFT)
+#endif
 
 /****************************************************************************************
  * Public Types
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h
index 3b278d45f..fb16c7fde 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_rstc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_rstc.h
@@ -1,8 +1,8 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_rstc.h
- * Reset Controller (RSTC) definitions for the SAM3U and SAM4S
+ * Reset Controller (RSTC) definitions for the SAM3U, SAM4E, and SAM4S
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -64,6 +64,8 @@
 
 /* RSTC register bit definitions ********************************************************/
 
+/* Reset Controller Control Register */
+
 #define RSTC_CR_PROCRST         (1 << 0)  /* Bit 0:  Processor Reset */
 #define RSTC_CR_PERRST          (1 << 2)  /* Bit 2:  Peripheral Reset */
 #define RSTC_CR_EXTRST          (1 << 3)  /* Bit 3:  External Reset */
@@ -71,6 +73,8 @@
 #define RSTC_CR_KEY_MASK        (0xff << RSTC_CR_KEY_SHIFT)
 #  define RSTC_CR_KEY           (0xa5 << RSTC_CR_KEY_SHIFT)
 
+/* Reset Controller Status Register */
+
 #define RSTC_SR_URSTS           (1 << 0)  /* Bit 0:  User Reset Status */
 #define RSTC_SR_RSTTYP_SHIFT    (8)       /* Bits 8-10:  Reset Type */
 #define RSTC_SR_RSTTYP_MASK     (7 << RSTC_SR_RSTTYP_SHIFT)
@@ -82,10 +86,13 @@
 #define RSTC_SR_NRSTL           (1 << 16) /* Bit 16:  NRST Pin Level */
 #define RSTC_SR_SRCMP           (1 << 17) /* Bit 17:  Software Reset Command in Progress */
 
+/* Reset Controller Mode Register */
+
 #define RSTC_MR_URSTEN          (1 << 0)  /* Bit 0:  User Reset Enable */
 #define RSTC_MR_URSTIEN         (1 << 4)  /* Bit 4:  User Reset Interrupt Enable */
 #define RSTC_MR_ERSTL_SHIFT     (8)       /* Bits 8-11:  External Reset Length */
 #define RSTC_MR_ERSTL_MASK      (15 << RSTC_MR_ERSTL_SHIFT)
+#  define RSTC_MR_ERSTL(n)      ((uint32_t)(n) << RSTC_MR_ERSTL_SHIFT)
 #define RSTC_MR_KEY_SHIFT       (24)      /* Bits 24-31:  Password */
 #define RSTC_MR_KEY_MASK        (0xff << RSTC_CR_KEY_SHIFT)
 #  define RSTC_MR_KEY           (0xa5 << RSTC_CR_KEY_SHIFT)
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtc.h b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h
index 8f8d49ff7..a352bf231 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_rtc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_rtc.h
@@ -1,8 +1,8 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_rtc.h
- * Real-time Clock (RTC) definitions for the SAM3U and SAM4S
+ * Real-time Clock (RTC) definitions for the SAM3U, SAM4E, and SAM4S
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -102,11 +102,12 @@
 
 #define RTC_MR_HRMOD                 (1 << 0)  /* Bit 0:  12-/24-hour Mode */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define RTC_MR_PERSIAN             (1 << 1)  /* Bit 1:  PERSIAN Calendar */
 #  define RTC_MR_NEGPPM              (1 << 4)  /* Bit 4:  Negative PPM Correction */
 #  define RTC_MR_CORRECTION_SHIFT    (8)       /* Bits 8-14: Slow Clock Correction */
-#  define RTC_MR_CORRECTION_
+#  define RTC_MR_CORRECTION_MASK     (0x7f << RTC_MR_CORRECTION_SHIFT)
+#    define RTC_MR_CORRECTION(n)     ((uint32_t)(n) << RTC_MR_CORRECTION_SHIFT)
 #  define RTC_MR_HIGHPPM             (1 << 15) /* Bit 15: HIGH PPM Correction */
 #  define RTC_MR_OUT0_SHIFT          (16)      /* Bits 16-18: RTCOUT0 Output Source Selection */
 #  define RTC_MR_OUT0_MASK           (7 << RTC_MR_OUT0_SHIFT)
@@ -130,55 +131,66 @@
 #    define RTC_MR_OUT1_PROG_PULSE   (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */
 #  define RTC_MR_THIGH_SHIFT         (24)      /* Bits 24-26: High Duration of the Output Pulse */
 #  define RTC_MR_THIGH_MASK          (7 << RTC_MR_THIGH_SHIFT)
-#    define RTC_MR_THIGH_ 31MS       (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
-#    define RTC_MR_THIGH_ 16MS       (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
-#    define RTC_MR_THIGH_ 4MS        (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
-#    define RTC_MR_THIGH_ 976US      (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
-#    define RTC_MR_THIGH_ 488US      (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
-#    define RTC_MR_THIGH_ 22US       (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
-#    define RTC_MR_THIGH_ 0US        (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
-#    define RTC_MR_THIGH_ 15US       (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
+#    define RTC_MR_THIGH_31MS        (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
+#    define RTC_MR_THIGH_16MS        (1 << RTC_MR_THIGH_SHIFT) /* 15.6 ms */
+#    define RTC_MR_THIGH_4MS         (2 << RTC_MR_THIGH_SHIFT) /* 3.91 ms */
+#    define RTC_MR_THIGH_976US       (3 << RTC_MR_THIGH_SHIFT) /* 976 µs */
+#    define RTC_MR_THIGH_488US       (4 << RTC_MR_THIGH_SHIFT) /* 488 µs */
+#    define RTC_MR_THIGH_22US        (5 << RTC_MR_THIGH_SHIFT) /* 122 µs */
+#    define RTC_MR_THIGH_0US         (6 << RTC_MR_THIGH_SHIFT) /* 30.5 µs */
+#    define RTC_MR_THIGH_15US        (7 << RTC_MR_THIGH_SHIFT) /* 15.2 µs */
 #  define RTC_MR_TPERIOD_SHIFT       (28)      /* Bits 28-29: Period of the Output Pulse */
 #  define RTC_MR_TPERIOD_MASK        (3 << RTC_MR_TPERIOD_SHIFT)
-#    define RTC_MR_TPERIOD_ 1S       (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
-#    define RTC_MR_TPERIOD_ 500MS    (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */
-#    define RTC_MR_TPERIOD_ 250MS    (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */
-#    define RTC_MR_TPERIOD_ 125MS    (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */
+#    define RTC_MR_TPERIOD_1S        (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
+#    define RTC_MR_TPERIOD_500MS     (1 << RTC_MR_TPERIOD_SHIFT) /* 500 ms */
+#    define RTC_MR_TPERIOD_250MS     (2 << RTC_MR_TPERIOD_SHIFT) /* 250 ms */
+#    define RTC_MR_TPERIOD_125MS     (3 << RTC_MR_TPERIOD_SHIFT) /* 125 ms */
 #endif
 
 /* RTC Time Register */
 
 #define RTC_TIMR_SEC_SHIFT           (0)       /* Bits 0-6:  Current Second */
 #define RTC_TIMR_SEC_MASK            (0x7f << RTC_TIMR_SEC_SHIFT)
+#  define RTC_TIMR_SEC(n)            ((uint32_t)(n) << RTC_TIMR_SEC_SHIFT)
 #define RTC_TIMR_MIN_SHIFT           (8)       /* Bits 8-14:  Current Minute */
 #define RTC_TIMR_MIN_MASK            (0x7f <<  RTC_TIMR_MIN_SHIFT)
+#  define RTC_TIMR_MIN(n)            ((uint32_t)(n) <<  RTC_TIMR_MIN_SHIFT)
 #define RTC_TIMR_HOUR_SHIFT          (16)      /* Bits 16-21: Current Hour */
 #define RTC_TIMR_HOUR_MASK           (0x3f << RTC_TIMR_HOUR_SHIFT)
+#  define RTC_TIMR_HOUR(n)           ((uint32_t)(n) << RTC_TIMR_HOUR_SHIFT)
 #define RTC_TIMR_AMPM                (1 << 22) /* Bit 22: Ante Meridiem Post Meridiem Indicator */
 
 /* RTC Calendar Register */
 
 #define RTC_CALR_CENT_SHIFT          (0)       /* Bits 0-6:  Current Century */
 #define RTC_CALR_CENT_MASK           (0x7f << RTC_CALR_CENT_SHIFT)
+#  define RTC_CALR_CENT(n)           ((uint32_t)(n) << RTC_CALR_CENT_SHIFT)
 #define RTC_CALR_YEAR_SHIFT          (8)       /* Bits 8-15:  Current Year */
 #define RTC_CALR_YEAR_MASK           (0xff << RTC_CALR_YEAR_SHIFT)
+#  define RTC_CALR_YEAR(n)           ((uint32_t)(n) << RTC_CALR_YEAR_SHIFT)
 #define RTC_CALR_MONTH_SHIFT         (16)      /* Bits 16-20: Current Month */
 #define RTC_CALR_MONTH_MASK          (0x1f << RTC_CALR_MONTH_SHIFT)
+#  define RTC_CALR_MONTH(n)           ((uint32_t)(n) << RTC_CALR_MONTH_SHIFT)
 #define RTC_CALR_DAY_SHIFT           (21)      /* Bits 21-23: Current Day in Current Week */
 #define RTC_CALR_DAY_MASK            (7 << RTC_CALR_DAY_SHIFT)
+#  define RTC_CALR_DAY(n)            ((uint32_t)(n)7 << RTC_CALR_DAY_SHIFT)
 #define RTC_CALR_DATE_SHIFT          (24)      /* Bits 24-29: Current Day in Current Month */
 #define RTC_CALR_DATE_MASK           (0x3f << RTC_CALR_DATE_SHIFT)
+#  define RTC_CALR_DATE(n)           ((uint32_t)(n) << RTC_CALR_DATE_SHIFT)
 
 /* RTC Time Alarm Register */
 
 #define RTC_TIMALR_SEC_SHIFT         (0)       /* Bits 0-6:  Second Alarm */
 #define RTC_TIMALR_SEC_MASK          (0x7f << RTC_TIMALR_SEC_SHIFT)
+#  define RTC_TIMALR_SEC(n)          ((uint32_t)(n) << RTC_TIMALR_SEC_SHIFT)
 #define RTC_TIMALR_SECEN             (1 << 7)  /* Bit 7:  Second Alarm Enable */
 #define RTC_TIMALR_MIN_SHIFT         (8)       /* Bits 8-14:  Minute Alarm */
 #define RTC_TIMALR_MIN_MASK          (0x7f << RTC_TIMALR_MIN_SHIFT)
+#  define RTC_TIMALR_MIN(n)          ((uint32_t)(n) << RTC_TIMALR_MIN_SHIFT)
 #define RTC_TIMALR_MINEN             (1 << 15) /* Bit 15: Minute Alarm Enable */
 #define RTC_TIMALR_HOUR_SHIFT        (16)      /* Bits 16-21:  Hour Alarm */
 #define RTC_TIMALR_HOUR_MASK         (0x3f << RTC_TIMALR_HOUR_SHIFT)
+#  define RTC_TIMALR_HOUR(n)         ((uint32_t)(n) << RTC_TIMALR_HOUR_SHIFT)
 #define RTC_TIMALR_AMPM              (1 << 22) /* Bit 22: AM/PM Indicator */
 #define RTC_TIMALR_HOUREN            (1 << 23) /* Bit 23: Hour Alarm Enable */
 
@@ -186,9 +198,11 @@
 
 #define RTC_CALALR_MONTH_SHIFT       (16)      /* Bits 16-20:  Month Alarm */
 #define RTC_CALALR_MONTH_MASK        (0x1f << RTC_CALALR_MONTH_SHIFT)
+#  define RTC_CALALR_MONTH(n)        ((uint32_t)(n) << RTC_CALALR_MONTH_SHIFT)
 #define RTC_CALALR_MTHEN             (1 << 23) /* Bit 23: Month Alarm Enable */
 #define RTC_CALALR_DATE_SHIFT        (24)      /* Bits 24-29:  Date Alarm */
 #define RTC_CALALR_DATE_MASK         (0x3f << RTC_CALALR_DATE_SHIFT)
+#  define RTC_CALALR_DATE(n)         ((uint32_t)(n) << RTC_CALALR_DATE_SHIFT)
 #define RTC_CALALR_DATEEN            (1 << 31) /* Bit 31: Date Alarm Enable */
 
 /* RTC Status Register */
@@ -199,7 +213,7 @@
 #define RTC_SR_TIMEV                 (1 << 3)  /* Bit 3:  Time Event */
 #define RTC_SR_CALEV                 (1 << 4)  /* Bit 4:  Calendar Event */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define RTC_SR_TDERR               (1 << 5)  /* Bit 5:  Time and/or Date Free Running Error */
 #endif
 
@@ -211,7 +225,7 @@
 #define RTC_SCCR_TIMCLR              (1 << 3)  /* Bit 3:  Time Clear */
 #define RTC_SCCR_CALCLR              (1 << 4)  /* Bit 4:  Calendar Clear */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define RTC_SR_TDERRCLR            (1 << 5)  /* Bit 5:  Time and/or Date Free Running Error Clear */
 #endif
 
@@ -223,7 +237,7 @@
 #define RTC_IER_TIMEN                (1 << 3)  /* Bit 3:  Time Event Interrupt Enable */
 #define RTC_IER_CALEN                (1 << 4)  /* Bit 4:  Calendar Event Interrupt Enable */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define RTC_SR_TDERREN             (1 << 5)  /* Bit 5:  Time and/or Date Error Interrupt Enable */
 #endif
 
@@ -235,7 +249,7 @@
 #define RTC_IDR_TIMDIS               (1 << 3)  /* Bit 3:  Time Event Interrupt Disable */
 #define RTC_IDR_CALDIS               (1 << 4)  /* Bit 4:  Calendar Event Interrupt Disable */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define RTC_SR_TDERRDIS            (1 << 5)  /* Bit 5:  Time and/or Date Error Interrupt Disable */
 #endif
 
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_rtt.h b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h
index bd34ca814..c64933e88 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_rtt.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_rtt.h
@@ -1,8 +1,8 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_rtt.h
- * Real-time Timer (RTT) definitions for the SAM3U and SAM4S
+ * Real-time Timer (RTT) definitions for the SAM3U, SAM4E, and SAM4S
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -69,12 +69,13 @@
 /* Real-time Timer Mode Register */
 
 #define RTT_MR_RTPRES_SHIFT    (0)       /* Bits 0-15:  Real-time Timer Prescaler Value */
-#define RTT_MR_RTPRES__MASK    (0xffff << RTT_MR_RTPRES_SHIFT)
+#define RTT_MR_RTPRES_MASK     (0xffff << RTT_MR_RTPRES_SHIFT)
+#  define RTT_MR_RTPRES(n)     ((uint32_t)(n) << RTT_MR_RTPRES_SHIFT)
 #define RTT_MR_ALMIEN          (1 << 16) /* Bit 16: Alarm Interrupt Enable */
 #define RTT_MR_RTTINCIEN       (1 << 17) /* Bit 17: Real-time Timer Increment Int Enable */
 #define RTT_MR_RTTRST          (1 << 18) /* Bit 18: Real-time Timer Restart */
 
-#if defined(CONFIG_ARCH_CHIP_SAM4S)
+#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
 #  define RTT_MR_RTTDIS        (1 << 20) /* Bit 20: Real-time Timer Disable */
 #  define RTT_MR_RTC1HZ        (1 << 24) /* Bit 24: Real-Time Clock 1Hz Clock Selection */
 #endif
diff --git a/nuttx/arch/arm/src/sam34/chip/sam_smc.h b/nuttx/arch/arm/src/sam34/chip/sam_smc.h
index 7444aeb22..22bdf0397 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam_smc.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_smc.h
@@ -1,6 +1,6 @@
 /****************************************************************************************
  * arch/arm/src/sam34/chip/sam_smc.h
- * Static Memory Controller (SMC) definitions for the SAM3U and SAM4S
+ * Static Memory Controller (SMC) definitions for the SAM3U, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h b/nuttx/arch/arm/src/sam34/chip/sam_wdt.h
index d62398972..a43a065fc 100644
--- a/nuttx/arch/arm/src/sam34/chip/sam3u_wdt.h
+++ b/nuttx/arch/arm/src/sam34/chip/sam_wdt.h
@@ -1,8 +1,8 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam3u_wdt.h
- * Watchdog Timer (WDT) definitions for the SAM3U, SAM3X, SAM3A, and SAM4S
+ * arch/arm/src/sam34/chip/sam_wdt.h
+ * Watchdog Timer (WDT) definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
  *
- *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -74,12 +74,14 @@
 
 #define WDT_MR_WDV_SHIFT          (0)       /* Bits 0-11:  Watchdog Counter Value */
 #define WDT_MR_WDV_MASK           (0xfff << WDT_MR_WDV_SHIFT)
+#  define WDT_MR_WDV(n)           ((uint32_t)(n) << WDT_MR_WDV_SHIFT)
 #define WDT_MR_WDFIEN             (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
 #define WDT_MR_WDRSTEN            (1 << 13) /* Bit 13: Watchdog Reset Enable */
 #define WDT_MR_WDRPROC            (1 << 14) /* Bit 14: Watchdog Reset Processor */
 #define WDT_MR_WDDIS              (1 << 15) /* Bit 15: Watchdog Disable */
 #define WDT_MR_WDD_SHIFT          (16)      /* Bits 16-27:  Watchdog Delta Value */
 #define WDT_MR_WDD_MASK           (0xfff << WDT_MR_WDD_SHIFT)
+#  define WDT_MR_WDD(n)           ((uint32_t)(n) << WDT_MR_WDD_SHIFT)
 #define WDT_MR_WDDBGHLT           (1 << 28) /* Bit 28: Watchdog Debug Halt */
 #define WDT_MR_WDIDLEHLT          (1 << 29) /* Bit 29: Watchdog Idle Halt */
 
diff --git a/nuttx/arch/arm/src/sam34/sam_clockconfig.c b/nuttx/arch/arm/src/sam34/sam_clockconfig.c
index 8148e4fb9..28e2b9194 100644
--- a/nuttx/arch/arm/src/sam34/sam_clockconfig.c
+++ b/nuttx/arch/arm/src/sam34/sam_clockconfig.c
@@ -51,7 +51,7 @@
 #include "sam_clockconfig.h"
 #include "chip/sam_pmc.h"
 #include "chip/sam_eefc.h"
-#include "chip/sam3u_wdt.h"
+#include "chip/sam_wdt.h"
 #include "chip/sam_supc.h"
 #include "chip/sam_matrix.h"