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authorGregory Nutt <gnutt@nuttx.org>2015-03-29 15:39:08 -0600
committerGregory Nutt <gnutt@nuttx.org>2015-03-29 15:39:08 -0600
commitc675fa39c22cece6d9653c65f211fec19415951c (patch)
tree18bbf9d32cf10a012dad23de382b3d6bd63533e8 /nuttx
parent79a68f1bd62fdea08b88bc0cd75fcb275bf108f7 (diff)
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Update ChangeLog
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not fully functional. From Kristopher Tate (2015-030-29).
* arch/arm/src/armv7-m: Add configuration option and logic to support
the D-Cache in write-through mode (2015-03-29).
-
+ * arch/arm/src/stm32/Kconfig, stm32_lse.c, stm32_lsi.c, stm32_rtc.c/.h,
+ stm32_rtcc.c, stm32_rtcounter.c, and stm32f*_rcc.c: The
+ STM32F4Discovery board doesn't come with a Low speed external
+ oscillator so the default LSE source for the RTC doesn't work. In
+ stm32_rtcc.c the up_rtcinitialize() logic doesn't work with the LSI.
+ The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call
+ that rightfully enables the lsi clock; but the next times, when the
+ rtc is already setup, the rtc_resume() call does NOT start the lsi
+ clock! The right place to put LSE/LSI initialisation is inside
+ stm32_stdclockconfig() in stm32fxxxxx_rcc.c. Doing this I checked
+ the possible uses of the LSI and the LSE sources: the LSI can be used
+ for RTC and/or the IWDG, while the LSE only for the RTC (and to output
+ the MCO1 pin). This change is not verifed for any other platforms.
+ From Leo Aloe3132