diff options
| -rw-r--r-- | apps/ChangeLog.txt | 2 | ||||
| -rw-r--r-- | apps/system/Kconfig | 4 | ||||
| -rw-r--r-- | apps/system/Make.defs | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc31xx/Kconfig | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/Kconfig | 8 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h | 86 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam_smc.h | 61 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_gpio.c | 4 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/sam4s_gpio.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/sam_allocateheap.c | 154 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_ccm.c | 2 | ||||
| -rwxr-xr-x | nuttx/arch/arm/src/stm32/stm32_ccm.h | 2 | ||||
| -rw-r--r-- | nuttx/configs/sam4s-xplained/README.txt | 67 | ||||
| -rw-r--r-- | nuttx/configs/sam4s-xplained/nsh/defconfig | 16 | ||||
| -rwxr-xr-x | nuttx/configs/sam4s-xplained/nsh/setenv.sh | 14 | ||||
| -rw-r--r-- | nuttx/configs/sam4s-xplained/ostest/defconfig | 2 | ||||
| -rw-r--r-- | nuttx/configs/sam4s-xplained/src/Makefile | 4 | ||||
| -rw-r--r-- | nuttx/configs/sam4s-xplained/src/sam4s-xplained.h | 35 | ||||
| -rw-r--r-- | nuttx/configs/sam4s-xplained/src/sam_boot.c | 8 | ||||
| -rw-r--r-- | nuttx/configs/sure-pic32mx/README.txt | 26 |
20 files changed, 414 insertions, 89 deletions
diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index bbe571785..36e28f1cb 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -596,4 +596,6 @@ for a long time (2013-6-23). * apps/examplex/nxhello: Correct default colors when in Y1 code mode. (2013-6-24). + * system/Make.defs and Kconfig: The RAM test was not correctly built + into the configuration and build system. diff --git a/apps/system/Kconfig b/apps/system/Kconfig index 9ba734250..f683ac00a 100644 --- a/apps/system/Kconfig +++ b/apps/system/Kconfig @@ -19,6 +19,10 @@ menu "FLASH Erase-all Command" source "$APPSDIR/system/flash_eraseall/Kconfig" endmenu +menu "RAM test" +source "$APPSDIR/system/ramtest/Kconfig" +endmenu + menu "readline()" source "$APPSDIR/system/readline/Kconfig" endmenu diff --git a/apps/system/Make.defs b/apps/system/Make.defs index d68953387..d27479599 100644 --- a/apps/system/Make.defs +++ b/apps/system/Make.defs @@ -50,6 +50,10 @@ ifeq ($(CONFIG_SYSTEM_FLASH_ERASEALL),y) CONFIGURED_APPS += system/flash_eraseall endif +ifeq ($(CONFIG_SYSTEM_RAMTEST),y) +CONFIGURED_APPS += system/ramtest +endif + ifeq ($(CONFIG_SYSTEM_READLINE),y) CONFIGURED_APPS += system/readline endif diff --git a/nuttx/arch/arm/src/lpc31xx/Kconfig b/nuttx/arch/arm/src/lpc31xx/Kconfig index 531cea0af..1022cfe60 100644 --- a/nuttx/arch/arm/src/lpc31xx/Kconfig +++ b/nuttx/arch/arm/src/lpc31xx/Kconfig @@ -12,7 +12,7 @@ choice config ARCH_CHIP_LPC3130 bool "LPC3130" - select ARCH_HAVE_EXTNAN + select ARCH_HAVE_EXTNAND select ARCH_HAVE_EXTSRAM0 select ARCH_HAVE_EXTSRAM1 select ARCH_HAVE_EXTDRAM diff --git a/nuttx/arch/arm/src/sam34/Kconfig b/nuttx/arch/arm/src/sam34/Kconfig index 8bb2e6279..927a6619d 100644 --- a/nuttx/arch/arm/src/sam34/Kconfig +++ b/nuttx/arch/arm/src/sam34/Kconfig @@ -130,6 +130,10 @@ endchoice config ARCH_CHIP_SAM3U bool default n + select ARCH_HAVE_EXTNOR + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 config ARCH_CHIP_SAM4L bool @@ -139,6 +143,10 @@ config ARCH_CHIP_SAM4L config ARCH_CHIP_SAM4S bool default n + select ARCH_HAVE_EXTNOR + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 menu "AT91SAM3/4 Peripheral Support" diff --git a/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h index cb6d7eb18..91779aecb 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h +++ b/nuttx/arch/arm/src/sam34/chip/sam4s_pinmap.h @@ -154,49 +154,49 @@ /* Static Memory Controller (SMC) */ -#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) -#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) -#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) -#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) -#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) -#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) -#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) -#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) -#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) -#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) -#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) -#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) -#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) -#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) -#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) -#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) -#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) -#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) -#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) -#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) -#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) -#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) -#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) -#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN8) /* Serial Peripheral Interface (SPI) */ diff --git a/nuttx/arch/arm/src/sam34/chip/sam_smc.h b/nuttx/arch/arm/src/sam34/chip/sam_smc.h index e729c1519..f099132f0 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam_smc.h +++ b/nuttx/arch/arm/src/sam34/chip/sam_smc.h @@ -83,6 +83,11 @@ # define SAM_SMC_ECCPR15_OFFSET 0x006c /* SMC ECC parity 15 Register */ # define SAM_SMCCS_OFFSET(n) (0x0070+((n)*0x014)) +# define SAM_SMCCS0_OFFSET 0x0070 /* SMC CS0 offset */ +# define SAM_SMCCS1_OFFSET 0x0084 /* SMC CS1 offset */ +# define SAM_SMCCS2_OFFSET 0x0098 /* SMC CS2 offset */ +# define SAM_SMCCS3_OFFSET 0x00ac /* SMC CS3 offset */ + # define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup register */ # define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ # define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ @@ -97,6 +102,11 @@ #elif defined(CONFIG_ARCH_CHIP_SAM4S) # define SAM_SMCCS_OFFSET(n) ((n) << 4) +# define SAM_SMCCS0_OFFSET 0x0000 /* SMC CS0 offset */ +# define SAM_SMCCS1_OFFSET 0x0010 /* SMC CS1 offset */ +# define SAM_SMCCS2_OFFSET 0x0020 /* SMC CS2 offset */ +# define SAM_SMCCS3_OFFSET 0x0030 /* SMC CS3 offset */ + # define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup Register */ # define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ # define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ @@ -146,10 +156,11 @@ #endif #define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) -# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0)) -# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1)) -# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2)) -# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3)) +# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS0_OFFSET) +# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS1_OFFSET) +# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS2_OFFSET) +# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS3_OFFSET) + #define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET) #define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET) #define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET) @@ -158,6 +169,38 @@ #endif #define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET) +# define SAM_SMCCS0_SETUP (SAM_SMC_CS0_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS0_PULSE (SAM_SMC_CS0_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS0_CYCLE (SAM_SMC_CS0_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS0_TIMINGS (SAM_SMC_CS0_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS0_MODE (SAM_SMC_CS0_BASE+SAM_SMCCS_MODE_OFFSET) + +# define SAM_SMCCS1_SETUP (SAM_SMC_CS1_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS1_PULSE (SAM_SMC_CS1_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS1_CYCLE (SAM_SMC_CS1_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS1_TIMINGS (SAM_SMC_CS1_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS1_MODE (SAM_SMC_CS1_BASE+SAM_SMCCS_MODE_OFFSET) + +# define SAM_SMCCS2_SETUP (SAM_SMC_CS2_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS2_PULSE (SAM_SMC_CS2_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS2_CYCLE (SAM_SMC_CS2_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS2_TIMINGS (SAM_SMC_CS2_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS2_MODE (SAM_SMC_CS2_BASE+SAM_SMCCS_MODE_OFFSET) + +# define SAM_SMCCS3_SETUP (SAM_SMC_CS3_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS3_PULSE (SAM_SMC_CS3_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS3_CYCLE (SAM_SMC_CS3_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS3_TIMINGS (SAM_SMC_CS3_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS3_MODE (SAM_SMC_CS3_BASE+SAM_SMCCS_MODE_OFFSET) + #define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET) #define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET) #define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET) @@ -374,30 +417,40 @@ #define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ #define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) +# define SMCCS_SETUP_NWESETUP(n) ((n) << SMCCS_SETUP_NWESETUP_SHIFT) #define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ #define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) +# define SMCCS_SETUP_NCSWRSETUP(n) ((n) << SMCCS_SETUP_NCSWRSETUP_SHIFT) #define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ #define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) +# define SMCCS_SETUP_NRDSETUP(n) ((n) << SMCCS_SETUP_NRDSETUP_SHIFT) #define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ #define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) +# define SMCCS_SETUP_NCSRDSETUP(n) ((n) << SMCCS_SETUP_NCSRDSETUP_SHIFT) /* SMC Pulse Register */ #define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ #define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) +# define SMCCS_PULSE_NWEPULSE(n) ((n) << SMCCS_PULSE_NWEPULSE_SHIFT) #define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ #define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) +# define SMCCS_PULSE_NCSWRPULSE(n) ((n) << SMCCS_PULSE_NCSWRPULSE_SHIFT) #define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ #define SMCCS_PULSE_NRDPULSE_MASK (63 << SMCCS_PULSE_NRDPULSE_SHIFT) +# define SMCCS_PULSE_NRDPULSE(n) ((n) << SMCCS_PULSE_NRDPULSE_SHIFT) #define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ #define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) +# define SMCCS_PULSE_NCSRDPULSE(n) ((n) << SMCCS_PULSE_NCSRDPULSE_SHIFT) /* SMC Cycle Register */ #define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ #define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) +# define SMCCS_CYCLE_NWECYCLE(n) ((n) << SMCCS_CYCLE_NWECYCLE_SHIFT) #define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ #define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) +# define SMCCS_CYCLE_NRDCYCLE(n) ((n) << SMCCS_CYCLE_NRDCYCLE_SHIFT) /* SMC Timings Register */ diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c index a59878a3d..d00e54ba5 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.c @@ -388,6 +388,10 @@ int sam_configgpio(gpio_pinset_t cfgset) case GPIO_PERIPHA: case GPIO_PERIPHB: +#ifdef GPIO_HAVE_PERIPHCD + case GPIO_PERIPHC: + case GPIO_PERIPHD: +#endif ret = sam_configperiph(base, pin, cfgset); break; diff --git a/nuttx/arch/arm/src/sam34/sam4s_gpio.h b/nuttx/arch/arm/src/sam34/sam4s_gpio.h index 2217a1648..1d5ee82f2 100644 --- a/nuttx/arch/arm/src/sam34/sam4s_gpio.h +++ b/nuttx/arch/arm/src/sam34/sam4s_gpio.h @@ -64,7 +64,7 @@ * MMM. .... .... .... .... */ -#define GPIO_MODE_SHIFT (17) /* Bits 17-23: GPIO mode */ +#define GPIO_MODE_SHIFT (17) /* Bits 17-19: GPIO mode */ #define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT) # define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */ # define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */ diff --git a/nuttx/arch/arm/src/sam34/sam_allocateheap.c b/nuttx/arch/arm/src/sam34/sam_allocateheap.c index edacfc617..47e01e23b 100644 --- a/nuttx/arch/arm/src/sam34/sam_allocateheap.c +++ b/nuttx/arch/arm/src/sam34/sam_allocateheap.c @@ -47,30 +47,109 @@ #include <arch/board/board.h> -#include "chip.h" #include "mpu.h" #include "up_arch.h" #include "up_internal.h" + +#include "chip.h" #include "sam_mpuinit.h" +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +#endif + /**************************************************************************** * Private Definitions ****************************************************************************/ +/* All SAM's have SRAM0. The SAM3U family also have SRAM1 and possibly + * NFCSRAM. NFCSRAM may not be used, however, if NAND support is enabled. + * In addition, the SAM3U and SAM4S have external SRAM at CS0 (EXTSRAM0). + * Support for external SRAM at CS1-3 is not fully implemented. + */ + +#undef HAVE_SRAM1_REGION /* Assume no internal SRAM1 */ +#undef HAVE_NFCSRAM_REGION /* Assume no NFC SRAM */ +#undef HAVE_EXTSRAM0_REGION /* Assume no external SRAM at CS0 */ +#undef HAVE_EXTSRAM1_REGION /* Assume no external SRAM at CS1 */ +#undef HAVE_EXTSRAM2_REGION /* Assume no external SRAM at CS2 */ +#undef HAVE_EXTSRAM3_REGION /* Assume no external SRAM at CS3 */ + +/* Check if external SRAM is supported and, if so, it is is intended + * to be used as heap. + */ + +#if !defined(CONFIG_ARCH_EXTSRAM0) || !defined(CONFIG_ARCH_EXTSRAM0HEAP) +# undef CONFIG_ARCH_EXTSRAM0SIZE +# define CONFIG_ARCH_EXTSRAM0SIZE 0 +#endif -#if CONFIG_MM_REGIONS < 2 && SAM34_SRAM1_SIZE > 0 -# warning "CONFIG_MM_REGIONS < 2: SRAM1 not included in HEAP" +#if !defined(CONFIG_ARCH_EXTSRAM1) || !defined(CONFIG_ARCH_EXTSRAM1HEAP) +# undef CONFIG_ARCH_EXTSRAM1SIZE +# define CONFIG_ARCH_EXTSRAM1SIZE 0 #endif -#if CONFIG_MM_REGIONS < 3 && !defined(CONFIG_SAM34_NAND) -# warning "CONFIG_MM_REGIONS < 3: NFC SRAM not included in HEAP" +#if !defined(CONFIG_ARCH_EXTSRAM2) || !defined(CONFIG_ARCH_EXTSRAM2HEAP) +# undef CONFIG_ARCH_EXTSRAM2SIZE +# define CONFIG_ARCH_EXTSRAM2SIZE 0 #endif -#if CONFIG_MM_REGIONS > 2 && defined(CONFIG_SAM34_NAND) -# error "CONFIG_MM_REGIONS > 2 but cannot use NFC SRAM" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 2 +#if !defined(CONFIG_ARCH_EXTSRAM3) || !defined(CONFIG_ARCH_EXTSRAM3HEAP) +# undef CONFIG_ARCH_EXTSRAM3SIZE +# define CONFIG_ARCH_EXTSRAM3SIZE 0 +#endif + +/* SAM3U Unique memory configurations */ + +#ifdef CONFIG_ARCH_CHIP_SAM3U +# ifdef CONFIG_SAM34_NAND +# undef SAM34_NFCSRAM_SIZE +# define SAM34_NFCSRAM_SIZE 0 +# endif + +# if SAM34_SRAM1_SIZE > 0 +# if CONFIG_MM_REGIONS > 1 +# define HAVE_SRAM1_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 2: SRAM1 not included in HEAP" +# endif +# endif + +# if SAM34_NFCSRAM_SIZE > 0 +# if CONFIG_MM_REGIONS > 2 +# define HAVE_NFCSRAM_REGION +# else +# warning "CONFIG_MM_REGIONS < 3: NFC SRAM not included in HEAP" +# endif + +# if CONFIG_ARCH_EXTSRAM0SIZE > 0 +# if CONFIG_MM_REGIONS > 3 +# define HAVE_EXTSRAM0_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 4: External SRAM not included in HEAP" +# endif +# endif + +# elif CONFIG_ARCH_EXTSRAM0SIZE > 0 +# if CONFIG_MM_REGIONS > 2 +# define HAVE_EXTSRAM0_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 3: External SRAM not included in HEAP" +# endif +# endif +#else + +/* The SAM4S and SAM4L may have only internal SRAM0 and external SRAM0 */ + +# if CONFIG_ARCH_EXTSRAM0SIZE > 0 +# if CONFIG_MM_REGIONS > 1 +# define HAVE_EXTSRAM0_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 2: External SRAM not included in HEAP" +# endif +# endif #endif +/* Check common SRAM0 configuration */ + #if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) # error "CONFIG_DRAM_END is beyond the end of SRAM0" # undef CONFIG_DRAM_END @@ -224,7 +303,11 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void up_addregion(void) { -#if SAM34_SRAM1_SIZE > 0 + /* The SAM3U also have SRAM1 and NFCSRAM, We will add these as regions + * the first two additional memory regions if we have them. + */ + +#ifdef HAVE_SRAM1_REGION /* Allow user access to the heap memory */ sam_mpu_uheap(SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); @@ -233,7 +316,9 @@ void up_addregion(void) kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); -#if CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 +#endif /* HAVE_SRAM1_REGION */ + +#ifdef HAVE_NFCSRAM_REGION /* Allow user access to the heap memory */ sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); @@ -242,7 +327,50 @@ void up_addregion(void) kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); -#endif /* CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 */ -#endif /* SAM34_SRAM1_SIZE > 0 */ +#endif /* HAVE_NFCSRAM_REGION */ + +#ifdef HAVE_EXTSRAM0_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS0_BASE, CONFIG_ARCH_EXTSRAM0SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS0_BASE, CONFIG_ARCH_EXTSRAM0SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ + +#ifdef HAVE_EXTSRAM1_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS1_BASE, CONFIG_ARCH_EXTSRAM1SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS1_BASE, CONFIG_ARCH_EXTSRAM1SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ + +#ifdef HAVE_EXTSRAM2_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS2_BASE, CONFIG_ARCH_EXTSRAM2SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS2_BASE, CONFIG_ARCH_EXTSRAM2SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ + +#ifdef HAVE_EXTSRAM3_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS3_BASE, CONFIG_ARCH_EXTSRAM3SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS3_BASE, CONFIG_ARCH_EXTSRAM3SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ } #endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/nuttx/arch/arm/src/stm32/stm32_ccm.c b/nuttx/arch/arm/src/stm32/stm32_ccm.c index fbb97c0e9..c3f72a398 100755 --- a/nuttx/arch/arm/src/stm32/stm32_ccm.c +++ b/nuttx/arch/arm/src/stm32/stm32_ccm.c @@ -3,7 +3,7 @@ * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> - * Based on a prototype by Petteri Amimonen + * Based on a prototype by Petteri Aimonen * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/arch/arm/src/stm32/stm32_ccm.h b/nuttx/arch/arm/src/stm32/stm32_ccm.h index 5960acd73..131421063 100755 --- a/nuttx/arch/arm/src/stm32/stm32_ccm.h +++ b/nuttx/arch/arm/src/stm32/stm32_ccm.h @@ -3,7 +3,7 @@ * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> - * Based on a prototype by Petteri Amimonen + * Based on a prototype by Petteri Aimonen * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/nuttx/configs/sam4s-xplained/README.txt b/nuttx/configs/sam4s-xplained/README.txt index edc7c753c..c07aae4c1 100644 --- a/nuttx/configs/sam4s-xplained/README.txt +++ b/nuttx/configs/sam4s-xplained/README.txt @@ -322,9 +322,8 @@ Buttons and LEDs Serial Consoles ^^^^^^^^^^^^^^^ - USART0 - ------ - + UART1 + ----- If you have a TTL to RS-232 convertor then this is the most convenient serial console to use. UART1 is the default in all of these configurations. @@ -334,6 +333,8 @@ Serial Consoles GND J1 pin 9 J4 pin 9 Vdd J1 pin 10 J4 pin 10 + USART1 + ------ USART1 is another option: USART1 RXD PA21 J2 pin 6 @@ -341,13 +342,12 @@ Serial Consoles GND J2 pin 9 Vdd J2 pin 10 + Virtual COM Port + ---------------- Yet another option is to use UART0 and the virtual COM port. This option may be more convenient for long term development, but was painful to use during board bring-up. - Virtual COM Port - ---------------- - The SAM4S Xplained contains an Embedded Debugger (EDBG) that can be used to program and debug the ATSAM4S16C using Serial Wire Debug (SWD). The Embedded debugger also include a Virtual Com port interface over @@ -587,5 +587,56 @@ Configuration sub-directories nsh: This configuration directory will built the NuttShell. See NOTES above. - nsh: - This configuration directory will built the NuttShell. See NOTES above. + NOTES: + 1. The configuration configuration can be modified to include support + for the on-board SRAM (1MB). + + System Type -> External Memory Configuration + CONFIG_ARCH_EXTSRAM0=y : Select SRAM on CS0 + CONFIG_ARCH_EXTSRAM0SIZE=1048576 : Size=1MB + + Now what are you going to do with the SRAM. There are two choices: + + a) To enable the NuttX RAM test that may be used to verify the + external SRAM: + + System Type -> External Memory Configuration + CONFIG_ARCH_EXTSRAM0HEAP=n : Don't add to heap + + Application Configuration -> System NSH Add-Ons + CONFIG_SYSTEM_RAMTEST=y : Enable the RAM test built-in + + In this configuration, the SDRAM is not added to heap and so is + not excessible to the applications. So the RAM test can be + freely executed against the SRAM memory beginning at address + 0x6000:0000 (CS0). + + nsh> ramtest -h + Usage: <noname> [-w|h|b] <hex-address> <decimal-size> + + Where: + <hex-address> starting address of the test. + <decimal-size> number of memory locations (in bytes). + -w Sets the width of a memory location to 32-bits. + -h Sets the width of a memory location to 16-bits (default). + -b Sets the width of a memory location to 8-bits. + + To test the entire external SRAM: + + nsh> ramtest 60000000 1048576 + RAMTest: Marching ones: 60000000 1048576 + RAMTest: Marching zeroes: 60000000 1048576 + RAMTest: Pattern test: 60000000 1048576 55555555 aaaaaaaa + RAMTest: Pattern test: 60000000 1048576 66666666 99999999 + RAMTest: Pattern test: 60000000 1048576 33333333 cccccccc + RAMTest: Address-in-address test: 60000000 1048576 + + b) To add this RAM to the NuttX heap, you would need to change the + configuration as follows: + + System Type -> External Memory Configuration + CONFIG_ARCH_EXTSRAM0HEAP=y : Add external RAM to heap + + Memory Management + -CONFIG_MM_REGIONS=1 : Only the internal SRAM + +CONFIG_MM_REGIONS=2 : Also include external SRAM diff --git a/nuttx/configs/sam4s-xplained/nsh/defconfig b/nuttx/configs/sam4s-xplained/nsh/defconfig index f064d3f01..dbe1d14a9 100644 --- a/nuttx/configs/sam4s-xplained/nsh/defconfig +++ b/nuttx/configs/sam4s-xplained/nsh/defconfig @@ -92,6 +92,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set CONFIG_ARMV7M_OABI_TOOLCHAIN=y +# CONFIG_GPIO_IRQ is not set # # AT91SAM3/4 Configuration Options @@ -162,13 +163,18 @@ CONFIG_SAM34_UART1=y # # AT91SAM3/4 GPIO Interrupt Configuration # -# CONFIG_GPIOA_IRQ is not set -# CONFIG_GPIOB_IRQ is not set -# CONFIG_GPIOC_IRQ is not set # # External Memory Configuration # +CONFIG_ARCH_HAVE_EXTNAND=y +CONFIG_ARCH_HAVE_EXTNOR=y +CONFIG_ARCH_HAVE_EXTSRAM0=y +CONFIG_ARCH_HAVE_EXTSRAM1=y +# CONFIG_ARCH_EXTNAND is not set +# CONFIG_ARCH_EXTNOR is not set +# CONFIG_ARCH_EXTSRAM0 is not set +# CONFIG_ARCH_EXTSRAM1 is not set # # Architecture Options @@ -247,7 +253,7 @@ CONFIG_DEV_CONSOLE=y # CONFIG_FDCLONE_DISABLE is not set # CONFIG_FDCLONE_STDIO is not set CONFIG_SDCLONE_DISABLE=y -# CONFIG_SCHED_WAITPID is not set +CONFIG_SCHED_WAITPID=y # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set @@ -383,7 +389,7 @@ CONFIG_DISABLE_MOUNTPOINT=y # # CONFIG_MM_MULTIHEAP is not set # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=3 +CONFIG_MM_REGIONS=1 # CONFIG_GRAN is not set # diff --git a/nuttx/configs/sam4s-xplained/nsh/setenv.sh b/nuttx/configs/sam4s-xplained/nsh/setenv.sh index 493fe18c1..0e97bb38b 100755 --- a/nuttx/configs/sam4s-xplained/nsh/setenv.sh +++ b/nuttx/configs/sam4s-xplained/nsh/setenv.sh @@ -31,6 +31,20 @@ # ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi # This is the Cygwin path to the location where I installed the Atmel GCC # toolchain under Windows. You will also have to edit this if you install diff --git a/nuttx/configs/sam4s-xplained/ostest/defconfig b/nuttx/configs/sam4s-xplained/ostest/defconfig index b26c9c827..eb3ddaf6e 100644 --- a/nuttx/configs/sam4s-xplained/ostest/defconfig +++ b/nuttx/configs/sam4s-xplained/ostest/defconfig @@ -379,7 +379,7 @@ CONFIG_DISABLE_MOUNTPOINT=y # # CONFIG_MM_MULTIHEAP is not set # CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=3 +CONFIG_MM_REGIONS=1 # CONFIG_GRAN is not set # diff --git a/nuttx/configs/sam4s-xplained/src/Makefile b/nuttx/configs/sam4s-xplained/src/Makefile index 80d8f4719..4103dd7cf 100644 --- a/nuttx/configs/sam4s-xplained/src/Makefile +++ b/nuttx/configs/sam4s-xplained/src/Makefile @@ -42,6 +42,10 @@ AOBJS = $(ASRCS:.S=$(OBJEXT)) CSRCS = sam_boot.c +ifeq ($(CONFIG_ARCH_EXTSRAM0),y) +CSRCS += sam_sram.c +endif + ifeq ($(CONFIG_HAVE_CXX),y) CSRCS += sam_cxxinitialize.c endif diff --git a/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h b/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h index 1d6877d33..ace4bb186 100644 --- a/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h +++ b/nuttx/configs/sam4s-xplained/src/sam4s-xplained.h @@ -87,10 +87,10 @@ */ -#define GPIO_D9 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ - GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_D10 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ - GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_D9 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_D10 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOC | GPIO_PIN17) /* Mechanical buttons: * @@ -101,9 +101,14 @@ * PA5 BP2 */ -#define GPIO_BP2 (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_CFG_DEGLITCH | \ - GPIO_INT_BOTHEDGES | GPIO_PORT_PIOA | GPIO_PIN5) -#define IRQ_BP2 SAM_IRQ_PA5 +#define GPIO_BP2 (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_CFG_DEGLITCH | \ + GPIO_INT_BOTHEDGES | GPIO_PORT_PIOA | GPIO_PIN5) +#define IRQ_BP2 SAM_IRQ_PA5 + +/* SRAM Enable. EBI_NLB PC16. Active=low; Standby=high */ + +#define GPIO_EBI_NLB (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \ + GPIO_PORT_PIOC | GPIO_PIN16) /************************************************************************************ * Public Types @@ -119,9 +124,21 @@ * Public Functions ************************************************************************************/ -/**************************************************************************** +/************************************************************************************ + * Name: sam_sram_initialize + * + * Description: + * Configure and enable SRAM on board the SAM4S Xplained + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_EXTSRAM0 +void sam_sram_initialize(void); +#endif + +/************************************************************************************ * Name: up_ledinit - ****************************************************************************/ + ************************************************************************************/ #ifdef CONFIG_ARCH_LEDS void up_ledinit(void); diff --git a/nuttx/configs/sam4s-xplained/src/sam_boot.c b/nuttx/configs/sam4s-xplained/src/sam_boot.c index 54d29053e..a302d3efb 100644 --- a/nuttx/configs/sam4s-xplained/src/sam_boot.c +++ b/nuttx/configs/sam4s-xplained/src/sam_boot.c @@ -67,9 +67,15 @@ void sam_boardinitialize(void) { - /* Configure on-board LEDs if LED support has been selected. */ +#ifdef CONFIG_ARCH_EXTSRAM0 + /* Configure and enable SRAM on board the SAM4S Xplained */ + + sam_sram_initialize(); +#endif #ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + up_ledinit(); #endif } diff --git a/nuttx/configs/sure-pic32mx/README.txt b/nuttx/configs/sure-pic32mx/README.txt index 48877a498..a57815657 100644 --- a/nuttx/configs/sure-pic32mx/README.txt +++ b/nuttx/configs/sure-pic32mx/README.txt @@ -896,7 +896,7 @@ Where <subdir> is one of the following: device will save encoded trace output in in-memory buffer; if the USB monitor is enabled, that trace buffer will be periodically emptied and dumped to the system logging device (UART2 in this - configuraion): + configuration): Device Drivers -> "USB Device Driver Support: CONFIG_USBDEV_TRACE=y : Enable USB trace feature @@ -931,5 +931,29 @@ Where <subdir> is one of the following: System Type -> PIC32MX Peripheral Support: CONFIG_PIC32MX_UART2=n : Disable UART2 + The SYSLOG output on UART2 cannot by used. You have two choices, + first, you can simply disable the SYSLOG device. Then 1) debug + output will come the USB console, and 2) all debug output prior + to connecting the USB console will be lost: + Device Drivers -> System Logging Device Options: CONFIG_SYSLOG=n : Disable SYSLOG output + + The second options is to configure a RAM SYLOG device. This is + a circular buffer that accumulated debug output in memory. The + contents of the circular buffer can be dumped from the NSH command + line using the 'dmesg' command. + + Device Drivers -> System Logging Device Options: + CONFIG_SYSLOG=y : Enables the System Logging feature. + CONFIG_RAMLOG=y : Enable the RAM-based logging feature. + CONFIG_RAMLOG_CONSOLE=n : (there is no default console device) + CONFIG_RAMLOG_SYSLOG=y : This enables the RAM-based logger as the + system logger. + + Logging is currently can be set up to use any amount of memorym (here 8KB): + + CONFIG_RAMLOG_CONSOLE_BUFSIZE=8192 + + 7. See the notes for the nsh configuration. Most also apply to the usbnsh + configuration. |