diff options
| -rw-r--r-- | nuttx/ChangeLog | 3 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/chip/sam3u_pio.h | 3 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/sam34/sam3u_gpio.c | 13 |
3 files changed, 18 insertions, 1 deletions
diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 67dd3c6c9..b213057e9 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -5085,3 +5085,6 @@ * arch/arm/src/sam34/sam_allocateheap.c: Clocking must be applied to the SMC module for the 3X and 3A family in order for the NFC SRAM to be functional (2013-6-28). + * arch/arm/src/sam34/sam3u_gpio.c: Need to disable write + protection before configuring PIO pins. + diff --git a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h index 0ce331d18..c1cc045e7 100644 --- a/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h +++ b/nuttx/arch/arm/src/sam34/chip/sam3u_pio.h @@ -58,7 +58,7 @@ /* 0x000c: Reserved */ #define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */ #define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */ -#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */ +#define SAM_PIO_OSR_OFFSET 0x0018 /* Output Status Register */ /* 0x001c: Reserved */ #define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */ #define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */ @@ -444,6 +444,7 @@ #define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */ #define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */ #define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT) +# define PIO_WPMR_WPKEY (0x50494f << PIO_WPMR_WPKEY_SHIFT) /* PIO Write Protect Status Register */ diff --git a/nuttx/arch/arm/src/sam34/sam3u_gpio.c b/nuttx/arch/arm/src/sam34/sam3u_gpio.c index a1ce7953f..d94f2a3f8 100644 --- a/nuttx/arch/arm/src/sam34/sam3u_gpio.c +++ b/nuttx/arch/arm/src/sam34/sam3u_gpio.c @@ -377,6 +377,14 @@ int sam_configgpio(gpio_pinset_t cfgset) uint32_t pin = sam_gpiopin(cfgset); int ret; + /* Enable writing to GPIO registers + * TODO: This probably requires some protection against re-entry. + */ + + putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET); + + /* Handle the pin configuration according to pin type */ + switch (cfgset & GPIO_MODE_MASK) { case GPIO_INPUT: @@ -400,6 +408,11 @@ int sam_configgpio(gpio_pinset_t cfgset) ret = -EINVAL; break; } + + /* Enable writing to GPIO registers */ + + putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET); + return ret; } |